JPS5458376A - Semiconductor memory unit and its writing method - Google Patents
Semiconductor memory unit and its writing methodInfo
- Publication number
- JPS5458376A JPS5458376A JP12448477A JP12448477A JPS5458376A JP S5458376 A JPS5458376 A JP S5458376A JP 12448477 A JP12448477 A JP 12448477A JP 12448477 A JP12448477 A JP 12448477A JP S5458376 A JPS5458376 A JP S5458376A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- type
- layers
- depletion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000007812 deficiency Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Electrodes Of Semiconductors (AREA)
- Read Only Memory (AREA)
Abstract
PURPOSE:To prevent earlier deficiency of insulation film and to increase the number of rewriting, by providing the auxiliary region for charge supply in contact with at least a part or one of one of the source and drain. CONSTITUTION:The SiO2 4 and Si3N4 5 are laminated by bridging the p<+> type source and drain 2 and 3 on the n type substrate 1, and the gate electrode 7 is provided. At the boundary of the films 4 and 5 or a part of the film 5, charges are stored and held 6 and memorized. The layers 2 and 3 are provided with the n type auxiliary region 10 and charges are supplied. The region 10 is present under the gate and the end of the region 10 is present in the depletion layer 11 formed by the layers 2 and 3. In writing in, the layers 2 and 3 are back biased to the substrate 1, spreading the depletion layer under the charge holding means 6 and keeping the layer 10 at the same polarity and same potential as the back bias. The gate 7 is held at the potential close to the substrate 1. Thus, the n type carrier is induced with the different potential from the substrate region on the depletion layer of the substrate surface and the n type carrier is injected to the holding means 6. Accordingly, the bias can be less than the avalanche breakdown, no current concentration is caused and the insulation film is not deteriorated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12448477A JPS5458376A (en) | 1977-10-19 | 1977-10-19 | Semiconductor memory unit and its writing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12448477A JPS5458376A (en) | 1977-10-19 | 1977-10-19 | Semiconductor memory unit and its writing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5458376A true JPS5458376A (en) | 1979-05-11 |
| JPS576710B2 JPS576710B2 (en) | 1982-02-06 |
Family
ID=14886649
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12448477A Granted JPS5458376A (en) | 1977-10-19 | 1977-10-19 | Semiconductor memory unit and its writing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5458376A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58203819A (en) * | 1982-05-21 | 1983-11-28 | 株式会社幸和工業 | Method of arranging cup for confectionery |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840387A (en) * | 1971-09-23 | 1973-06-13 | ||
| JPS5057779A (en) * | 1973-09-21 | 1975-05-20 |
-
1977
- 1977-10-19 JP JP12448477A patent/JPS5458376A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4840387A (en) * | 1971-09-23 | 1973-06-13 | ||
| JPS5057779A (en) * | 1973-09-21 | 1975-05-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS576710B2 (en) | 1982-02-06 |
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