JPS5445571A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5445571A
JPS5445571A JP11188777A JP11188777A JPS5445571A JP S5445571 A JPS5445571 A JP S5445571A JP 11188777 A JP11188777 A JP 11188777A JP 11188777 A JP11188777 A JP 11188777A JP S5445571 A JPS5445571 A JP S5445571A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
layers
ion
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11188777A
Other languages
Japanese (ja)
Inventor
Takashi Sato
Norishige Hisatsugu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11188777A priority Critical patent/JPS5445571A/en
Publication of JPS5445571A publication Critical patent/JPS5445571A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: Go manufacture semiconductor device by forming the regions defferent in conduction type on the substrate surface with one ion injections.
CONSTITUTION: The Si epitaxial layer 2 is formed on the sapphire substrate 1, Sb thin layer 5 is evaporated via the resist mask 3, the film 5' is formed by remove- ing the mask. Next, the resist 6 is selectively coated and window 7 is provided, B ion is radiated on the entire surface, P+ layer 8 is formed and it is implanted on the layer 5'. At this time, N+ layer 9 is caused by knocking on the Sb atoms in the layer 5' by B ions. By removing the layers 5' and 6 and activating layers 8 and 9 with annealing, the PN junction transversal and very shallow can be formed
COPYRIGHT: (C)1979,JPO&Japio
JP11188777A 1977-09-17 1977-09-17 Manufacture for semiconductor device Pending JPS5445571A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11188777A JPS5445571A (en) 1977-09-17 1977-09-17 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11188777A JPS5445571A (en) 1977-09-17 1977-09-17 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5445571A true JPS5445571A (en) 1979-04-10

Family

ID=14572627

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11188777A Pending JPS5445571A (en) 1977-09-17 1977-09-17 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5445571A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016072630A (en) * 2014-09-26 2016-05-09 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブＣｏｍｍｉｓｓａｒｉａｔ Ａ Ｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓ Ａｌｔｅｒｎａｔｉｖｅｓ METHOD FOR DOPING GaN-BASE SEMICONDUCTOR

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016072630A (en) * 2014-09-26 2016-05-09 コミサリア ア レネルジー アトミック エ オ ゼネルジー アルテルナティブＣｏｍｍｉｓｓａｒｉａｔ Ａ Ｌ’Ｅｎｅｒｇｉｅ Ａｔｏｍｉｑｕｅ Ｅｔ Ａｕｘ Ｅｎｅｒｇｉｅｓ Ａｌｔｅｒｎａｔｉｖｅｓ METHOD FOR DOPING GaN-BASE SEMICONDUCTOR

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