JPS54162459A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54162459A
JPS54162459A JP7168278A JP7168278A JPS54162459A JP S54162459 A JPS54162459 A JP S54162459A JP 7168278 A JP7168278 A JP 7168278A JP 7168278 A JP7168278 A JP 7168278A JP S54162459 A JPS54162459 A JP S54162459A
Authority
JP
Japan
Prior art keywords
bump
region
layer
film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7168278A
Other languages
Japanese (ja)
Other versions
JPS617744B2 (en
Inventor
Hiroyasu Karimoto
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7168278A priority Critical patent/JPS54162459A/en
Publication of JPS54162459A publication Critical patent/JPS54162459A/en
Publication of JPS617744B2 publication Critical patent/JPS617744B2/ja
Granted legal-status Critical Current

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  • Weting (AREA)

Abstract

PURPOSE: To prevent the short circuit of bump and corrosion of wiring, by removing the barrier metal layer between the bump forming regions selectively, and forming the bump after the connection of the barrier metal layer at the bump forming region through leaving it at the scribing region of substrate.
CONSTITUTION: On the substrate 51 having the element region 50, the Al layers 53, 53' are provided via the insulation film 52, the layers are coated with the SiO2 54, and opening 57 is made on the film 54 with the resist mask 55. The hole 56 is made on the film 54 through the hole of the mask 55. The mask 55 is removed, to form the bump forming region slightly greater than the window 57, scribing line region and the resist mask 58 opened on the junction region of the both regions. Further, the Cu layer 20 is formed, the film 20 is lifted off through the removal of the mask 58 to form the layer 20A to 20I. The gold bump electrode 60 is formed on the layer 20A 20D by coating the layers 20E and 20F 20I. With this method, the Al layer is not etched with the lift off method even on the small holes on the film 54, then the bump short-circuit is not caused at plating since no barrier metal is present at the bump forming region.
COPYRIGHT: (C)1979,JPO&Japio
JP7168278A 1978-06-13 1978-06-13 Manufacture for semiconductor device Granted JPS54162459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7168278A JPS54162459A (en) 1978-06-13 1978-06-13 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7168278A JPS54162459A (en) 1978-06-13 1978-06-13 Manufacture for semiconductor device

Publications (2)

Publication Number Publication Date
JPS54162459A true JPS54162459A (en) 1979-12-24
JPS617744B2 JPS617744B2 (en) 1986-03-08

Family

ID=13467570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7168278A Granted JPS54162459A (en) 1978-06-13 1978-06-13 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54162459A (en)

Also Published As

Publication number Publication date
JPS617744B2 (en) 1986-03-08

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