JPS54158875A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54158875A
JPS54158875A JP6796678A JP6796678A JPS54158875A JP S54158875 A JPS54158875 A JP S54158875A JP 6796678 A JP6796678 A JP 6796678A JP 6796678 A JP6796678 A JP 6796678A JP S54158875 A JPS54158875 A JP S54158875A
Authority
JP
Japan
Prior art keywords
electrode
layer
region
type
regions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6796678A
Other languages
Japanese (ja)
Inventor
Seiichi Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6796678A priority Critical patent/JPS54158875A/en
Publication of JPS54158875A publication Critical patent/JPS54158875A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE: To reduce a power loss in a graft base region by wiring electrodes, formed in an emitter region and a bse region, in three imentions and by expanding an emitter electrode over the graft base region via an insulator layer.
CONSTITUTION: On N+-type semiconductor substrate 11, N-type layer 12 is grown, in which P-type base region 13 is formed by diffusion. In this region 13, several N-type emitter regions 14 are formed by diffusion and among them, P-type graft base regions 15a intruding into layer 12 are provided. Then, emitter electrode 17 and base electrode 19 are formed in regions 14 and regions 15a respectively in three dimentions. Namely, a metal electrode is bonded where electrodes 18 and 19 are formed, the entire surface is covered with insulator layer 19, and only layer 19 on electrode 17 is removed by photolithographing. On layer 19, independent eimitter electrode 20 meeting electrode 17 is formed expanding over electrode 19.
COPYRIGHT: (C)1979,JPO&Japio
JP6796678A 1978-06-05 1978-06-05 Semiconductor device Pending JPS54158875A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6796678A JPS54158875A (en) 1978-06-05 1978-06-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6796678A JPS54158875A (en) 1978-06-05 1978-06-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54158875A true JPS54158875A (en) 1979-12-15

Family

ID=13360212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6796678A Pending JPS54158875A (en) 1978-06-05 1978-06-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54158875A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844274A (en) * 1971-10-12 1973-06-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4844274A (en) * 1971-10-12 1973-06-26

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