JPS54155783A - Manufacture of insulating-gate type semiconductor device - Google Patents

Manufacture of insulating-gate type semiconductor device

Info

Publication number
JPS54155783A
JPS54155783A JP6455978A JP6455978A JPS54155783A JP S54155783 A JPS54155783 A JP S54155783A JP 6455978 A JP6455978 A JP 6455978A JP 6455978 A JP6455978 A JP 6455978A JP S54155783 A JPS54155783 A JP S54155783A
Authority
JP
Japan
Prior art keywords
film
region
poly
crystal
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6455978A
Other languages
Japanese (ja)
Inventor
Takashi Osone
Takashi Hirao
Kazuhiko Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6455978A priority Critical patent/JPS54155783A/en
Publication of JPS54155783A publication Critical patent/JPS54155783A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a high-density device by using an ion-injecting method for the threshold-level control of a MOS transistor and by using a poly-crystal Si film with impurities for a load resistance. CONSTITUTION:Onto P-type Si substrate 11, lamination film 22 of SiO2 and Si3N4 is bonded, an opening is made and in substrate 11, B<+>-ion injected region 23 for the threshold-level control of a field region is formed. On region 23, thick field oxidized film 13 is formed by heating and after film 22 is removed, B<+> or P<+>-ion injected region 24 for the threshold-level control of a MOS transistor is formed in substrate 11 and then covered with gate SiO2 film 25. On film 25, poly-crystal Si gate electrode 27a is fitted and onto films 13 at both the edge, poly-crystal Si wirings 27b and 27c are provided; and P<+> or As<+> ions are injected to form N-type source and drain regions 28a and 28b and wiring region 28c of MOS element 1. The entire surface is covered with SiO2 film 29, an opening is made, and poly-crystal Si film 31 containing impurities is bonded to the entire surface and made into load resistance 10.
JP6455978A 1978-05-29 1978-05-29 Manufacture of insulating-gate type semiconductor device Pending JPS54155783A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6455978A JPS54155783A (en) 1978-05-29 1978-05-29 Manufacture of insulating-gate type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6455978A JPS54155783A (en) 1978-05-29 1978-05-29 Manufacture of insulating-gate type semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP60269701A Division JPS61166063A (en) 1985-11-29 1985-11-29 Manufacture of insulated gate type semiconductor device

Publications (1)

Publication Number Publication Date
JPS54155783A true JPS54155783A (en) 1979-12-08

Family

ID=13261700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6455978A Pending JPS54155783A (en) 1978-05-29 1978-05-29 Manufacture of insulating-gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS54155783A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696850A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS61166063A (en) * 1985-11-29 1986-07-26 Matsushita Electric Ind Co Ltd Manufacture of insulated gate type semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696850A (en) * 1979-12-30 1981-08-05 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS6243547B2 (en) * 1979-12-30 1987-09-14 Fujitsu Ltd
JPS61166063A (en) * 1985-11-29 1986-07-26 Matsushita Electric Ind Co Ltd Manufacture of insulated gate type semiconductor device
JPH0432535B2 (en) * 1985-11-29 1992-05-29

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