JPS54152473A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS54152473A
JPS54152473A JP6148978A JP6148978A JPS54152473A JP S54152473 A JPS54152473 A JP S54152473A JP 6148978 A JP6148978 A JP 6148978A JP 6148978 A JP6148978 A JP 6148978A JP S54152473 A JPS54152473 A JP S54152473A
Authority
JP
Japan
Prior art keywords
sealing
circumference
cover
opening
increase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6148978A
Other languages
Japanese (ja)
Inventor
Hiroshi Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6148978A priority Critical patent/JPS54152473A/en
Publication of JPS54152473A publication Critical patent/JPS54152473A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To attain glass sealing with high reliability by brazing a metal ring to the circumference of the opening part of a ceramic cover and by sealing a metallic cap to this ring by welding.
CONSTITUTION: Ceramic cover 17 is provided with the chip mount part of the container and an opening matched with the junction effective part for a lead frame and metal ring 18 is brazed to the circumference of the opening by a silver-copper brazing material. At the circumference of cover 17, low-fusion-point glass is glazed. The container covered with cover 17 is taken into a furnace, where sealing is carried out. Next, semiconductor chip 15 is mounted making use of the opening part and after metallic thin wire 19 is connected, metallic cap 20 is seam-welded. As a result, since there is no need to increase the temperature up to 500°C after the connection to carry out the sealing, even an Au-Al connection forms no inter-metal compound, so that operation efficiency will improve while reliability increase.
COPYRIGHT: (C)1979,JPO&Japio
JP6148978A 1978-05-22 1978-05-22 Package for semiconductor device Pending JPS54152473A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6148978A JPS54152473A (en) 1978-05-22 1978-05-22 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6148978A JPS54152473A (en) 1978-05-22 1978-05-22 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54152473A true JPS54152473A (en) 1979-11-30

Family

ID=13172542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6148978A Pending JPS54152473A (en) 1978-05-22 1978-05-22 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54152473A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4768063A (en) * 1983-03-28 1988-08-30 Canon Kabushiki Kaisha Sheet material receiving device
US4801996A (en) * 1987-10-14 1989-01-31 Hewlett-Packard Company Gigahertz rate integrated circuit package incorporating semiconductive MIS power-line substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4768063A (en) * 1983-03-28 1988-08-30 Canon Kabushiki Kaisha Sheet material receiving device
US4801996A (en) * 1987-10-14 1989-01-31 Hewlett-Packard Company Gigahertz rate integrated circuit package incorporating semiconductive MIS power-line substrate

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