JPS63262858A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63262858A JPS63262858A JP9881287A JP9881287A JPS63262858A JP S63262858 A JPS63262858 A JP S63262858A JP 9881287 A JP9881287 A JP 9881287A JP 9881287 A JP9881287 A JP 9881287A JP S63262858 A JPS63262858 A JP S63262858A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- ceramic
- pellet
- temperature
- base body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 239000008188 pellet Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000000919 ceramic Substances 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 27
- 238000002844 melting Methods 0.000 claims abstract description 18
- 230000008018 melting Effects 0.000 claims abstract description 16
- 238000003466 welding Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005219 brazing Methods 0.000 claims description 14
- 239000003566 sealing material Substances 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 abstract description 8
- 230000001070 adhesive effect Effects 0.000 abstract description 8
- 238000007789 sealing Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract 3
- 230000000694 effects Effects 0.000 description 4
- 229910017709 Ni Co Inorganic materials 0.000 description 3
- 229910003267 Ni-Co Inorganic materials 0.000 description 3
- 229910003262 Ni‐Co Inorganic materials 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910017944 Ag—Cu Inorganic materials 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 231100000989 no adverse effect Toxicity 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特にセラミックケースを形
成した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a ceramic case.
従来のかかるセラミックケースを形成した半導体装置は
、大半導体ペレット用、大電力半導体ペレット用として
Ｃｕ −Ｗ 、又はＦｅ−Ｎｉ−Ｃｏ。Conventional semiconductor devices formed with such ceramic cases are made of Cu-W or Fe-Ni-Co for large semiconductor pellets or high power semiconductor pellets.
Ｍｏ等の基板をセラミック基体にペレットのマウント温
度よりも高い５００〜６００℃程度の高融点ろう材、例
えばＡｇ−Ｃｕ又はＡｇろう材により固定しキャップを
かぶせてセラミックケースを構成していた。A ceramic case was constructed by fixing a substrate made of Mo or the like to a ceramic base using a high melting point brazing material such as Ag-Cu or Ag brazing material having a temperature of about 500 to 600° C. higher than the mounting temperature of the pellets, and then covering it with a cap.
上述したセラミックケースのマウント部は前記Ｃｕ−Ｗ
等の基板をセラミック基体に高融点ろう材で接着する構
成であるため、前記セラミック基体と前記マウント部を
構成する基板との平行度にばらつきを生ずることが多か
った。このため金−シリコン共晶によりマウントを行な
う場合、ペレット裏面全体がマウントされず部分的にマ
ウ〉・トされている場合が多い。従って、かかる部分的
マラントの場合、電気的接続が不十分で電気抵抗が増大
したり、ペレットからの発熱の伝導が不十分となったり
する欠点がある。The mount portion of the ceramic case described above is made of the Cu-W
Since the structure is such that a substrate such as the above is bonded to a ceramic substrate using a high melting point brazing material, variations in the parallelism between the ceramic substrate and the substrate constituting the mount portion often occur. For this reason, when mounting is performed using gold-silicon eutectic, the entire back surface of the pellet is often not mounted but only partially mounted. Therefore, in the case of such a partial marant, there are disadvantages such as insufficient electrical connection, increased electrical resistance, and insufficient conduction of heat from the pellet.
また、ペレットサイズが１０ｍｍ角以上の大きなものや
、短辺と長辺の比率が大きい細長いペレットの場合には
、ともにペレットクラック、ペレット剥離が発生する欠
点がある。In addition, in the case of large pellets with a size of 10 mm square or more, or elongated pellets with a large ratio of short side to long side, both have the disadvantage that pellet cracks and pellet peeling occur.
本発明の目的は、電気的接続や機械的接続を十分にし、
熱伝導性を改善しうるとともに、ペレットクラックやペ
レット剥離を生じにくい半導体装置を提供することにあ
る。The purpose of the invention is to provide sufficient electrical and mechanical connections;
An object of the present invention is to provide a semiconductor device that can improve thermal conductivity and is less likely to cause pellet cracks or pellet peeling.
本発明の半導体装置は、半導体ペレットをマウント材に
より載置する金属基板と、前記半導体ペレットのボンデ
ィングワイヤに接続される外部リードを備え、前記マウ
ント材の溶融温度よりも低い低融点ろう材もしくはシー
ムウェルド接着されるシール材により前記金属基板を固
定するセラミック基体と、シール材もしくは低融点ろう
材により前記セラミック基体に接着されるキャップとを
含み、前記金属基板と前記セラミックスと前記キャップ
とによりセラミックケースを形成するように構成される
。The semiconductor device of the present invention includes a metal substrate on which a semiconductor pellet is mounted using a mounting material, an external lead connected to a bonding wire of the semiconductor pellet, and a low melting point brazing material or a seam having a melting temperature lower than the melting temperature of the mounting material. A ceramic case is formed by the metal substrate, the ceramic, and the cap, including a ceramic base that fixes the metal substrate with a sealing material welded and a cap that is adhered to the ceramic base with a sealing material or a low-melting brazing material. configured to form a
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の第一の実施例を説明するための半導体
装置の断面図である。FIG. 1 is a sectional view of a semiconductor device for explaining a first embodiment of the present invention.
第１図に示すように、半導体べ“レット３をマウントす
るセラミック基体１とは分離独立した金属基板２はＦｅ
−Ｎｉ−Ｃｏ、Ｍｏ、またはＣｕ−Ｗから成り、その表
面はＮｉめっき、Ａｕメッキが順次形成されている。こ
の金属基板２上に、例えばＡｕまたはＡｕ−３ｉよりな
るマウント材４を使用して半導体ペレット３をマウント
する。次に、半導体ペレット３がマウントされた前記金
属基板２をセラミック基板１に低融点ろう材５により外
付けする。このときの接着材はマウント温度（Ａｕ−３
ｉ共晶温度約３８０℃）よりも低い温度で接着可能な低
融点ろう材、例えばＡｕ−５ｎ、Ａｕ−３ｎ−Ａｅ、Ｐ
ｂ−Ａｇ等の枠状プリフォームを用いる。従って、これ
らの低融点ろう材を使用するため、マウントされた半導
体ペレット３に対する悪影響は無い。次に、かかるセラ
ミック基体１に金属キャップ６を接着しセラミックケー
スとして封止する接着材は低融点ろう材よりもさらに低
温度（３００℃以下）で封止可能なシームウェルド接着
によるシールリング７を用いる。As shown in FIG.
- It is made of Ni-Co, Mo, or Cu-W, and its surface is sequentially plated with Ni and Au. A semiconductor pellet 3 is mounted on this metal substrate 2 using a mounting material 4 made of, for example, Au or Au-3i. Next, the metal substrate 2 on which the semiconductor pellet 3 is mounted is externally attached to the ceramic substrate 1 using a low melting point brazing material 5. At this time, the adhesive was used at the mount temperature (Au-3
Low melting point brazing filler metals that can be bonded at temperatures lower than the i-eutectic temperature (approximately 380°C), such as Au-5n, Au-3n-Ae, P
A frame-shaped preform such as b-Ag is used. Therefore, since these low melting point brazing materials are used, there is no adverse effect on the mounted semiconductor pellets 3. Next, the adhesive used to bond the metal cap 6 to the ceramic base 1 and seal it as a ceramic case is a seam-weld seal ring 7 that can be sealed at a lower temperature (below 300°C) than a low melting point brazing material. use
このように、セラミックケースとして封止する接着材が
半導体ペレット３を金属基板２にマウントする温度より
も実質的に低くした接着材を用いることにより、セラミ
ック基体１と、半導体ペレット３をマウントした金属基
板２との平行性を安定させることができる。In this way, by using an adhesive for sealing the ceramic case at a temperature substantially lower than that for mounting the semiconductor pellet 3 on the metal substrate 2, the ceramic base 1 and the metal on which the semiconductor pellet 3 is mounted can be bonded. Parallelism with the substrate 2 can be stabilized.
第２図は本発明の第二の実施例を説明するための半導体
装置の断面図である。FIG. 2 is a sectional view of a semiconductor device for explaining a second embodiment of the present invention.
第２図に示すように、半導体ペレット３をマウントする
金属基板２はＦｅ−Ｎｉ−Ｃｏから成り、その表面はＮ
ｉめつき、Ａｕめっきが順次形成されでいる。この金属
基板２上に、例えばＡｕまたはＡｕ−３ｔよりなるマウ
ント材４を使用して半導体ペレット３をマウントする。As shown in FIG. 2, the metal substrate 2 on which the semiconductor pellet 3 is mounted is made of Fe-Ni-Co, and its surface is made of N
i-plating and Au plating are successively formed. A semiconductor pellet 3 is mounted on this metal substrate 2 using a mounting material 4 made of, for example, Au or Au-3t.
次に、半導体ペレット３がマウントされた金属基板２を
シールリング７によりシームウェルド法でセラミック基
板１に接着しセラミックケースを形成する。かかるシー
ムウェルド法では前記ペレット３のマウント温度（Ａｕ
−Ｓｉ共晶温度約３８０℃）よりも低い温度で接着可能
であり、また作業雰囲気が不活性雰囲気で行なうため、
マウントされたペレット３に対する悪影響はない。かか
る構造のセラミックケースの封止は金属キャップ６を低
融点ろう材５を用いシームウェルド法やマウント温度よ
りも低温で且つシームウェルド部を酸化させたい不活性
雰囲気で接着すればよい。尚、この低融点よう材５は、
例えば、Ａｕ−３ｎ、Ａｕ−５ｎ−Ａｆ、Ｐｂ−Ａｇ等
を使用することができる。Next, the metal substrate 2 on which the semiconductor pellet 3 is mounted is bonded to the ceramic substrate 1 by the seam welding method using the seal ring 7 to form a ceramic case. In this seam welding method, the mounting temperature of the pellet 3 (Au
-Si eutectic temperature (approx. 380°C) can be bonded at a temperature lower than that, and the working atmosphere is an inert atmosphere.
There is no negative effect on the mounted pellets 3. The ceramic case having such a structure may be sealed by bonding the metal cap 6 using the low melting point brazing material 5 by seam welding or in an inert atmosphere at a temperature lower than the mounting temperature and in which the seam weld portion is desired to be oxidized. In addition, this low melting point filler material 5 is
For example, Au-3n, Au-5n-Af, Pb-Ag, etc. can be used.
かかる第二の実施例においても前述の第一の実施例と同
様にセラミック基体１と金属基板２との平行性を安定さ
せることができる。In this second embodiment as well, the parallelism between the ceramic substrate 1 and the metal substrate 2 can be stabilized as in the first embodiment.
以上説明したように、本発明の半導体装置は半導体ペレ
ットを載置する金属基板がセラミック基体に金−すす等
の低融点ろう材もしくはシームウェルド接着シール材に
より固定されてセラミックケースを構成することにより
、半導体ペレットをマウントするマウント部の金属基板
単体の平滑性が優れているため、安定したマウント性と
電気的接続や発熱の伝導性を向上させることができる効
果がある。また、本発明は上述の構成によりペレットク
ラックおよびペレット剥離の問題も解消しうる効果があ
る。As explained above, in the semiconductor device of the present invention, a metal substrate on which a semiconductor pellet is mounted is fixed to a ceramic base with a low melting point brazing material such as gold-soot or a seam weld adhesive sealing material to form a ceramic case. Since the metal substrate of the mount part on which the semiconductor pellet is mounted has excellent smoothness, it has the effect of improving stable mounting performance and electrical connection and heat conductivity. Furthermore, the present invention has the effect of solving the problems of pellet cracking and pellet peeling due to the above-described structure.
第１図は本発明の第一の実施例を説明するための半導体
装置の断面図、第２図は本発明の第二の実施例を説明す
るための半導体装置の断面図である。
１・・・セラミック基体、２・・・金属基板、３・・・
半導体ペレット、４・・・マウント材、５・・・低融点
ろう材、６・・・キャップ、７・・・シールリング、８
・・・ワイヤー、９・・・外部リード。FIG. 1 is a cross-sectional view of a semiconductor device for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a semiconductor device for explaining a second embodiment of the present invention. 1... Ceramic base, 2... Metal substrate, 3...
Semiconductor pellet, 4... Mounting material, 5... Low melting point brazing filler metal, 6... Cap, 7... Seal ring, 8
...Wire, 9...External lead.
Claims (1)
と、前記半導体ペレットのボンディングワイヤに接続さ
れる外部リードを備え、前記マウント材の溶融温度より
も低い低融点ろう材もしくはシームウェルド接着される
シール材により前記金属基板を固定するセラミック基体
と、シール材もしくは低融点ろう材により前記セラミッ
ク基体に接着されるキャップとを含み、前記金属基板と
前記セラミックスと前記キャップとによりセラミックケ
ースを形成していることを特徴とする半導体装置。A metal substrate on which a semiconductor pellet is placed using a mounting material, and an external lead connected to a bonding wire of the semiconductor pellet, using a low melting point brazing material lower than the melting temperature of the mounting material or a sealing material bonded by seam welding. A ceramic case is formed by the metal substrate, the ceramic, and the cap, including a ceramic base that fixes the metal substrate, and a cap that is bonded to the ceramic base using a sealing material or a low-melting brazing material. Characteristic semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9881287A JPS63262858A (en) | 1987-04-21 | 1987-04-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9881287A JPS63262858A (en) | 1987-04-21 | 1987-04-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63262858A true JPS63262858A (en) | 1988-10-31 |
Family
ID=14229740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9881287A Pending JPS63262858A (en) | 1987-04-21 | 1987-04-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63262858A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143547A (en) * | 1988-11-25 | 1990-06-01 | Nec Corp | Container for semiconductor integrated circuit |
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
| JP2010034212A (en) * | 2008-07-28 | 2010-02-12 | Toshiba Corp | High-frequency ceramic package and method of fabricating the same |
| WO2020045563A1 (en) * | 2018-08-30 | 2020-03-05 | 京セラ株式会社 | Semiconductor package and semiconductor device provided with same |
-
1987
- 1987-04-21 JP JP9881287A patent/JPS63262858A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02143547A (en) * | 1988-11-25 | 1990-06-01 | Nec Corp | Container for semiconductor integrated circuit |
| US5885853A (en) * | 1990-06-22 | 1999-03-23 | Digital Equipment Corporation | Hollow chip package and method of manufacture |
| JP2010034212A (en) * | 2008-07-28 | 2010-02-12 | Toshiba Corp | High-frequency ceramic package and method of fabricating the same |
| US8476755B2 (en) | 2008-07-28 | 2013-07-02 | Kabushiki Kaisha Toshiba | High frequency ceramic package and fabrication method for the same |
| WO2020045563A1 (en) * | 2018-08-30 | 2020-03-05 | 京セラ株式会社 | Semiconductor package and semiconductor device provided with same |
| JPWO2020045563A1 (en) * | 2018-08-30 | 2021-08-12 | 京セラ株式会社 | Semiconductor package and semiconductor device equipped with it |
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