JPS54148357A - Method for driving high-speed switching semiconductor device - Google Patents

Method for driving high-speed switching semiconductor device

Info

Publication number
JPS54148357A
JPS54148357A JP5677978A JP5677978A JPS54148357A JP S54148357 A JPS54148357 A JP S54148357A JP 5677978 A JP5677978 A JP 5677978A JP 5677978 A JP5677978 A JP 5677978A JP S54148357 A JPS54148357 A JP S54148357A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor device
speed switching
gate
switching semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5677978A
Other languages
Japanese (ja)
Inventor
Ryuichiro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5677978A priority Critical patent/JPS54148357A/en
Publication of JPS54148357A publication Critical patent/JPS54148357A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To reduce both the power consumption and the propagation delay time by applying the voltage, which is adverse polarity to the drain electrode and also just enough to form the necessary depletion layer, to the 2nd gate electrode of FET. CONSTITUTION:The voltage which is adverse polarity to the electrode of drain 9 and also just enough to form the necessary depletion layer is applied to the electrode of gate 7 of the FET which contains gate 6 positioning at the first place from the electrode of source 8 and between electrodes of source 8 and drain 9 plus gate electrode 7 positioning at the second place each. Thus, both the power consumption and the propagation delay time can be reduced.
JP5677978A 1978-05-12 1978-05-12 Method for driving high-speed switching semiconductor device Pending JPS54148357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5677978A JPS54148357A (en) 1978-05-12 1978-05-12 Method for driving high-speed switching semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5677978A JPS54148357A (en) 1978-05-12 1978-05-12 Method for driving high-speed switching semiconductor device

Publications (1)

Publication Number Publication Date
JPS54148357A true JPS54148357A (en) 1979-11-20

Family

ID=13036916

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5677978A Pending JPS54148357A (en) 1978-05-12 1978-05-12 Method for driving high-speed switching semiconductor device

Country Status (1)

Country Link
JP (1) JPS54148357A (en)

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