JPS54133866A - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPS54133866A
JPS54133866A JP4202178A JP4202178A JPS54133866A JP S54133866 A JPS54133866 A JP S54133866A JP 4202178 A JP4202178 A JP 4202178A JP 4202178 A JP4202178 A JP 4202178A JP S54133866 A JPS54133866 A JP S54133866A
Authority
JP
Japan
Prior art keywords
circuit
correlator
circuits
error
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4202178A
Other languages
Japanese (ja)
Other versions
JPS6244444B2 (en
Inventor
Akio Sabato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4202178A priority Critical patent/JPS54133866A/en
Publication of JPS54133866A publication Critical patent/JPS54133866A/en
Publication of JPS6244444B2 publication Critical patent/JPS6244444B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure

Abstract

PURPOSE:To shorten a lead-in time without deteriorating state characteristics of an automatic equalizer, by supplying a multilevel error pulse, which varies in its occupation ratio corresponding the error of an output signal, to a correlator. CONSTITUTION:To input terminal IN, delay circuits 1a, 1b...ln-1 are cascade- connected and its terminal is connected to terminating set 2. To connection points of respective circuits 1a to 1n-1, adder circuit 4 is connected via tap weighting circuits 3a, 3b...3n, and the output of circuit 4 is connected to output terminal OUT via multi-level discrimination circuit 5. Polarity information P of a multi-level discrimination signal is applied from circuit 5 of this constitution to correlator 6, two kinds of discrimination error pulses A and B are applied to selector circuit 7, and either one is selected by circuit 7 and applied to correlator 6. The output signal of terminal OUT is branched and supplied to the control input of circuit 7 via supervisory circuit 8 and shift pulse SH is inputted to correlator 6, so that the n- number outputs of correlator 6 will be applied to control inputs of circuits 3a to 3n via averaging circuits 9a to 9n.
JP4202178A 1978-04-10 1978-04-10 Automatic equalizer Granted JPS54133866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4202178A JPS54133866A (en) 1978-04-10 1978-04-10 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4202178A JPS54133866A (en) 1978-04-10 1978-04-10 Automatic equalizer

Publications (2)

Publication Number Publication Date
JPS54133866A true JPS54133866A (en) 1979-10-17
JPS6244444B2 JPS6244444B2 (en) 1987-09-21

Family

ID=12624507

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4202178A Granted JPS54133866A (en) 1978-04-10 1978-04-10 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS54133866A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572136A (en) * 1980-06-04 1982-01-07 Toshiba Corp Demodulating device
JPS5741022A (en) * 1980-08-26 1982-03-06 Nec Corp Automatic equalizer
EP0098588A2 (en) * 1982-07-08 1984-01-18 Siemens Aktiengesellschaft Adaptive equalizer for the equalization of multilevel signals

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507447A (en) * 1973-05-18 1975-01-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507447A (en) * 1973-05-18 1975-01-25

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS572136A (en) * 1980-06-04 1982-01-07 Toshiba Corp Demodulating device
JPS5741022A (en) * 1980-08-26 1982-03-06 Nec Corp Automatic equalizer
JPH0226406B2 (en) * 1980-08-26 1990-06-11 Nippon Electric Co
EP0098588A2 (en) * 1982-07-08 1984-01-18 Siemens Aktiengesellschaft Adaptive equalizer for the equalization of multilevel signals

Also Published As

Publication number Publication date
JPS6244444B2 (en) 1987-09-21

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