JPS6425629A - Automatic equalizer - Google Patents

Automatic equalizer

Info

Publication number
JPS6425629A
JPS6425629A JP62181140A JP18114087A JPS6425629A JP S6425629 A JPS6425629 A JP S6425629A JP 62181140 A JP62181140 A JP 62181140A JP 18114087 A JP18114087 A JP 18114087A JP S6425629 A JPS6425629 A JP S6425629A
Authority
JP
Japan
Prior art keywords
tap gain
register
initial
data
shifted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181140A
Other languages
Japanese (ja)
Inventor
Yutaka Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP62181140A priority Critical patent/JPS6425629A/en
Publication of JPS6425629A publication Critical patent/JPS6425629A/en
Pending legal-status Critical Current

Links

Landscapes

  • Facsimile Transmission Control (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

PURPOSE:To remarkably reduce the delay time till the data output by shifting the maximum value of the initial tap gain shifted to each tap gain register to the data input side by a prescribed quantity. CONSTITUTION:A reception data is inputted to a control section 201 and a training signal is sent, then the initial value of the predetermined tap gain is loaded respectively to each register element of a tap gain register 150 from a memory 200. Then the equalizing processing by applying tap gain calculation is repeated by number of times of training decided in advance. In this case, the equalizing output signal is extracted from an adder 160 from the point of time when a first reception data is shifted up to a shift register 130 corresponding to the peak of the maximum value of the initial tap gain loaded to the register. Thus, the data output is quickened and the delay time is shortened.
JP62181140A 1987-07-22 1987-07-22 Automatic equalizer Pending JPS6425629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181140A JPS6425629A (en) 1987-07-22 1987-07-22 Automatic equalizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181140A JPS6425629A (en) 1987-07-22 1987-07-22 Automatic equalizer

Publications (1)

Publication Number Publication Date
JPS6425629A true JPS6425629A (en) 1989-01-27

Family

ID=16095587

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181140A Pending JPS6425629A (en) 1987-07-22 1987-07-22 Automatic equalizer

Country Status (1)

Country Link
JP (1) JPS6425629A (en)

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