JPH0226406B2 - - Google Patents
Info
- Publication number
- JPH0226406B2 JPH0226406B2 JP55117382A JP11738280A JPH0226406B2 JP H0226406 B2 JPH0226406 B2 JP H0226406B2 JP 55117382 A JP55117382 A JP 55117382A JP 11738280 A JP11738280 A JP 11738280A JP H0226406 B2 JPH0226406 B2 JP H0226406B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- value
- error
- error signal
- equalization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 6
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03038—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a non-recursive structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Description
【発明の詳細な説明】
本発明は通信伝送路に生じる振幅歪および遅延
歪を自動的に補償する自動等化器に関し、特に高
速度データ伝送に適する自動等化器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic equalizer that automatically compensates for amplitude distortion and delay distortion occurring in a communication transmission path, and particularly to an automatic equalizer suitable for high-speed data transmission.
伝送路を通過した受信信号は、伝送路の振幅歪
および遅延歪により信号に歪が生じて受信端に到
達する。このため、受信装置にはこの歪を補償す
るための等化器が用いられる。近年高速度データ
伝送には、受信信号について一定のタイムスロツ
ト毎にリアルタイム演算処理を行ない、フイード
バツク系により自動等化を行う等化器が利用され
るようになつた。 A received signal that has passed through the transmission path reaches the receiving end with distortion occurring in the signal due to amplitude distortion and delay distortion of the transmission path. Therefore, an equalizer is used in the receiving device to compensate for this distortion. In recent years, high-speed data transmission has come to use equalizers that perform real-time arithmetic processing on received signals at fixed time slots and perform automatic equalization using a feedback system.
第１図は、従来の自動等化器を示すブロツク図
である。受信データRDは受信データのレジスタ
１に与えられ、その受信データの１タイムスロツ
ト毎に、このレジスタ１の内部を図の左から右
け、各エレメントX-2、X-1、X0、X1、X2を順に
シフトする。レジスタ２には等化修正量が各エレ
メントC-2〜C2に蓄えられていて、上記レジスタ
１の各エレメントとレジスタ２の各エレメントの
内容は、掛算器３で演算されて、加算器４に与え
られるように構成されている。加算器４の出力
は、等化補償された受信データRD′であり、出力
として利用される。受信データ用レジスタ１のセ
ンターにあるエレメントX0に蓄えられる受信デ
ータx0に対する等化結果は
2
〓n=-2
Coxo
となる。この値は、識別器５で理想値と比較さ
れ、誤差量が得られ、これが加算器６に送られて
修正量に加えられ、レジスタ２に蓄えられた修正
量Coがさらに最適値に修正される。この動作の
くり返しにより、自動等化器の出力データはタイ
ムスロツト毎に誤差量が最小化され、定常的に最
小の誤差量の等化を行うことができる。 FIG. 1 is a block diagram showing a conventional automatic equalizer. The received data RD is given to the received data register 1, and for each time slot of the received data, the inside of this register 1 is divided into elements X -2 , X -1 , X 0 , and X from left to right in the figure. Shift 1 and X 2 in order. In register 2, the equalization correction amount is stored in each element C -2 to C 2 , and the contents of each element of register 1 and each element of register 2 are calculated by multiplier 3 and added to adder 4. It is configured to be given to The output of the adder 4 is equalization-compensated received data RD', and is used as an output. The equalization result for the received data x 0 stored in the element X 0 at the center of the received data register 1 is 2 〓 n=-2 C o x o . This value is compared with the ideal value in the discriminator 5 to obtain the error amount, which is sent to the adder 6 and added to the correction amount, and the correction amount Co stored in the register 2 is further corrected to the optimal value. be done. By repeating this operation, the error amount of the output data of the automatic equalizer is minimized for each time slot, and equalization with the minimum error amount can be constantly performed.
このような従来装置では、伝送路の状態がわず
かずつ変化している場合には、最適等化を行なう
ことができるが、伝送路に急激な変化が生じる
と、この影響を受けた受信データはレジスタ１に
入力され、修正値Coによつて修正される。しか
し、その修正を受けた値は理想値より極端にずれ
ているので、識別器５からは過大な誤差量が送出
され、これが修正値Coに加算され異常な値にな
る。伝送路のじよう乱が除かれても修正値Coは
異常な値であり、これが定常な値に戻ることがで
きたとしても、かなりの時間を要し、この間の受
信データが適正に等化されず多くは失なわれる。
したがつて伝送路に何らかの原因で急激な変化あ
るいはじよう乱が生じ、短い時間でこれが消滅し
て、平常の伝送路の状態に回復するようなことが
起こると、その後は上述の自動等化機能が最小値
に収束せず、系が発散したり、そうでない場合で
も定常に復旧するまでに長い時間を要したりする
欠点がある。 With such conventional devices, optimal equalization can be performed when the state of the transmission path changes little by little, but when a sudden change occurs in the transmission path, the received data affected by this change is It is input into register 1 and modified by the modification value C o . However, since the corrected value is extremely deviated from the ideal value, an excessive amount of error is sent from the discriminator 5, and this is added to the corrected value Co , resulting in an abnormal value. Even if the disturbance in the transmission path is removed, the correction value C o is an abnormal value, and even if it can return to a steady value, it will take a considerable amount of time to ensure that the received data is properly equalized during this time. Much of it is lost because it is not transformed.
Therefore, if a sudden change or disturbance occurs in the transmission line for some reason, and this disappears in a short period of time and the normal transmission line condition is restored, the automatic equalization described above will be applied. The disadvantage is that the function does not converge to the minimum value, the system diverges, and even if it does not, it takes a long time to return to steady state.
本発明の目的は伝送路に一時的なじよう乱が生
じても、自動等化器の過修正または系の発散を防
ぎ、じよう乱の回復後に直ちに正常な動作に戻る
ことのできる自動等化器を提供することにある。 The purpose of the present invention is to provide an automatic equalizer that can prevent over-correction of the automatic equalizer or system divergence even if temporary disturbance occurs in the transmission path, and that can immediately return to normal operation after the disturbance is recovered. It is about providing the equipment.
本発明は、等化すべき受信信号を入力するタツ
プ付遅延手段と、その各タツプ出力に等化修正量
を掛算する掛算手段と、前記等化修正量を記憶す
る記憶手段と、前記掛算手段の出力を加算する第
一の加算手段と、この加算手段の出力を理想値と
比較して誤差信号を出力する識別手段と、前記誤
差信号と基準値との大小関係を判定する判定手段
と、前記大小関係に応じて前記基準値および前記
誤差信号の値の小さい方を選択して出力する選択
手段と、この選択手段の出力を前記等化修正量に
加算してこれを修正する第二の加算手段とを有
し、前記第一の加算手段の出力に等化された受信
信号を得るようにしたことを特徴とする自動等化
器である。 The present invention provides a delay means with a tap for inputting a received signal to be equalized, a multiplication means for multiplying each tap output by an equalization correction amount, a storage means for storing the equalization correction amount, and a multiplication means for storing the equalization correction amount. a first addition means for adding the outputs; an identification means for comparing the output of the addition means with an ideal value and outputting an error signal; a determination means for determining the magnitude relationship between the error signal and the reference value; a selection means for selecting and outputting the smaller of the reference value and the error signal value according to the magnitude relationship; and a second addition for adding the output of the selection means to the equalization correction amount to correct it. and means for obtaining an equalized received signal as an output of the first adding means.
本発明の実施例について図面により詳しく説明
する。 Embodiments of the present invention will be described in detail with reference to the drawings.
第２図は本発明の実施例を示すブロツク図であ
る。受信データのレジスタ１、修正量のレジスタ
２、掛算器３、加算器４、識別器５および加算器
６については、第１図に示す従来例と同様である
ので説明のくり返しを省く。本発明の特徴ある構
成は、識別器５の出力に得られる誤差量を加算器
６の各エレメントに与える回路にある。すなわ
ち、識別器５の出力は選択回路１０を介して加算
器６の各エレメントに与えられる。この選択回路
１０は、識別器５の出力が導かれた判定回路１１
により制御されるように構成されている。判定回
路１１は、識別器６の出力にえられる誤差量があ
る一定の基準を越えているか否かを判定する回路
である。 FIG. 2 is a block diagram showing an embodiment of the present invention. The received data register 1, the correction amount register 2, the multiplier 3, the adder 4, the discriminator 5, and the adder 6 are the same as those in the conventional example shown in FIG. 1, so their explanations will not be repeated. A characteristic configuration of the present invention resides in a circuit that provides the error amount obtained in the output of the discriminator 5 to each element of the adder 6. That is, the output of the discriminator 5 is given to each element of the adder 6 via the selection circuit 10. This selection circuit 10 includes a determination circuit 11 to which the output of the discriminator 5 is derived.
It is configured to be controlled by. The determination circuit 11 is a circuit that determines whether the amount of error obtained in the output of the discriminator 6 exceeds a certain standard.
第３図は判定回路１１、選択回路１０の詳細例
を示すブロツク図である。判定回路１１では、基
準値（ある一定値）を用いて誤差量と引算を行
い、誤差量が大きいと判定すれば出力は“０”、
小さいと判定すれば“１”を出力する。選択回路
１０ではセレクタSELがありBioには誤差量、Aio
には前記基準値が入力されており前記判定回路１
１の出力によつて“０”でAio（即ち基準値）、
“１”でBio（即ち誤差量）が出力される。 FIG. 3 is a block diagram showing a detailed example of the determination circuit 11 and selection circuit 10. The determination circuit 11 subtracts the error amount using a reference value (certain constant value), and if it is determined that the error amount is large, the output is "0".
If it is determined that it is smaller, "1" is output. In the selection circuit 10, there is a selector SEL, B io has an error amount, A io
The reference value is input to the judgment circuit 1.
A io (i.e. reference value) at “0” by the output of 1,
When "1", B io (ie, error amount) is output.
このように構成された装置では、自動等化器と
して安定な動作が行なわれているときには、選択
回路１０が開いたままであり、全体の動作は第１
図で説明した従来例と同様である。すなわち、受
信データRDは１タイムスロツト毎に、レジスタ
１の各エレメントを左から右へ順にシフトする。
レジスタ２には修正量が蓄積されていて、これが
掛算器３で演算され、加算器４に与えられて加算
される。従つて等化後の出力信号は
2
〓n=-2
Coxo
となる。この出力信号は識別器５で理想値と比較
され、その誤差が選択回路１０から加算器６の各
エレメントに送られ、修正値（Co）に加算され、
常に識別器５の出力誤差が最小になるようにフイ
ードバツク制御される。 In the device configured in this way, when the automatic equalizer is operating stably, the selection circuit 10 remains open, and the overall operation is the same as the first one.
This is the same as the conventional example explained in the figure. That is, the received data RD sequentially shifts each element of register 1 from left to right every time slot.
A correction amount is stored in a register 2, which is calculated by a multiplier 3, and then supplied to an adder 4 for addition. Therefore, the output signal after equalization is 2 〓 n=-2 C o x o . This output signal is compared with the ideal value by the discriminator 5, and the error is sent from the selection circuit 10 to each element of the adder 6 and added to the corrected value (C o ).
Feedback control is performed so that the output error of the discriminator 5 is always minimized.
ここで、伝送路にじよう乱が生じて、受信デー
タに急激な変化が起きた場合を考える。このとき
は加算器４の出力には大きな変化が生じ、これは
理想値と著しく相違する値となるので、識別器５
の出力には大きな誤差量が送出される。これは判
定回路１１により異常と判定され、判定回路１１
の出力に信号が送出され、選択回路１０を駆動し
一定値の誤差量を選択回路１０の出力とする。従
つてこの異常に大きな誤差量は加算器６に送られ
ない。レジスタ２に蓄積された修正量も、ある範
囲を越えることはない。伝送路のじよう乱が回復
して受信データが正常に戻ると、識別器５の送出
する誤差量は小さくなり、判定回路１１は出力信
号の送出を停止する。これにより選択回路１０は
開かれる。このようにしてフイードバツクループ
が再び構成されると、このときの状態は異常の発
生する直前の状態とほとんど等しく、直ちに適正
な自動等化制御の状態に入り、制御系が乱された
り、あるいは発散するようなことがない。 Now, let us consider a case where a disturbance occurs in the transmission path and a sudden change occurs in the received data. At this time, a large change occurs in the output of the adder 4, which is a value significantly different from the ideal value, so the discriminator 5
A large amount of error is sent to the output. This is determined to be abnormal by the determination circuit 11, and the determination circuit 11
A signal is sent to the output of the selection circuit 10 to drive the selection circuit 10 and set a constant error amount as the output of the selection circuit 10. Therefore, this abnormally large amount of error is not sent to the adder 6. The amount of modification stored in register 2 also does not exceed a certain range. When the disturbance in the transmission path is recovered and the received data returns to normal, the amount of error sent out by the discriminator 5 becomes smaller and the determination circuit 11 stops sending out the output signal. This opens the selection circuit 10. When the feedback loop is reconfigured in this way, the state at this time is almost the same as the state immediately before the abnormality occurred, and it immediately enters a proper automatic equalization control state, which prevents the control system from being disturbed. Or there is no divergence.
本発明によれば伝送路に一時的なじよう乱が生
じても、自動等化器の過修正または系の発散を防
ぎ、じよう乱の回復後に直ちに正常な動作に戻る
ことができる自動等化器が得られる。本発明は上
記じよう乱に対して最も影響を受け易い自動等化
器をもつ高速度データ通信の受信装置に実施して
特に効果的である。 According to the present invention, automatic equalization prevents over-correction of the automatic equalizer or system divergence even if a temporary disturbance occurs in the transmission path, and immediately returns to normal operation after the disturbance is recovered. A vessel is obtained. The present invention is particularly effective when implemented in high-speed data communication receiving apparatuses having automatic equalizers, which are most susceptible to the above-mentioned disturbances.
第１図は従来例の自動等化器を示す回路図、第
２図は本発明の実施例を示す回路図、第３図は第
２図の判定回路および選択回路の詳細例を示すブ
ロツク図である。
１，２……レジスタ、３……掛算器、４，６…
…加算器、５……識別器、１０……選択回路、１
１……判定回路。
FIG. 1 is a circuit diagram showing a conventional automatic equalizer, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a detailed example of the determination circuit and selection circuit shown in FIG. It is. 1, 2...Register, 3...Multiplier, 4,6...
... Adder, 5 ... Discriminator, 10 ... Selection circuit, 1
1... Judgment circuit.
Claims (1)
手段と、その各タツプ出力に等化修正量を掛算す
る掛算手段と、前記等化修正量を記憶する記憶手
段と、前記掛算手段の出力を加算する第一の加算
手段と、この加算手段の出力を理想値と比較して
誤差信号を出力する識別手段と、前記誤差信号と
基準値との大小関係を判定する判定手段と、前記
基準値より前記誤差信号が大きい場合前記基準値
を選択し、前記基準値より前記誤差信号が小さい
場合前記誤差信号を選択する選択手段と、その選
択手段の出力を前記等化修正量に加算してこれを
修正する第二の加算手段とを有し、前記第一の加
算手段の出力に等化された受信信号を得るように
したことを特徴とする自動等化器。1. Delay means with taps for inputting the received signal to be equalized, multiplication means for multiplying each tap output by an equalization correction amount, storage means for storing the equalization correction amount, and adding the outputs of the multiplication means. a first addition means for comparing the output of the addition means with an ideal value and outputting an error signal; a determination means for determining the magnitude relationship between the error signal and a reference value; a selection means for selecting the reference value when the error signal is large and selecting the error signal when the error signal is smaller than the reference value; and a selection means for adding the output of the selection means to the equalization correction amount. an automatic equalizer comprising a second adding means for correcting, and an equalized received signal is obtained as an output of the first adding means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11738280A JPS5741022A (en) | 1980-08-26 | 1980-08-26 | Automatic equalizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11738280A JPS5741022A (en) | 1980-08-26 | 1980-08-26 | Automatic equalizer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5741022A JPS5741022A (en) | 1982-03-06 |
| JPH0226406B2 true JPH0226406B2 (en) | 1990-06-11 |
Family
ID=14710259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11738280A Granted JPS5741022A (en) | 1980-08-26 | 1980-08-26 | Automatic equalizer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5741022A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61206321U (en) * | 1985-06-12 | 1986-12-26 | ||
| JP2616152B2 (en) * | 1990-06-15 | 1997-06-04 | 日本電気株式会社 | Automatic equalizer |
| JP2833609B2 (en) * | 1991-09-12 | 1998-12-09 | 日本電気株式会社 | Decision feedback type automatic equalizer |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52130515A (en) * | 1976-04-27 | 1977-11-01 | Toshiba Corp | Control system for automatic equalizer |
| JPS54133866A (en) * | 1978-04-10 | 1979-10-17 | Nec Corp | Automatic equalizer |
-
1980
- 1980-08-26 JP JP11738280A patent/JPS5741022A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52130515A (en) * | 1976-04-27 | 1977-11-01 | Toshiba Corp | Control system for automatic equalizer |
| JPS54133866A (en) * | 1978-04-10 | 1979-10-17 | Nec Corp | Automatic equalizer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5741022A (en) | 1982-03-06 |
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