JPS54101278A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54101278A
JPS54101278A JP796978A JP796978A JPS54101278A JP S54101278 A JPS54101278 A JP S54101278A JP 796978 A JP796978 A JP 796978A JP 796978 A JP796978 A JP 796978A JP S54101278 A JPS54101278 A JP S54101278A
Authority
JP
Japan
Prior art keywords
impurity diffusion
diffusion layer
impurity
manufacture
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP796978A
Other languages
Japanese (ja)
Inventor
Haruki Horikiri
Yasutomo Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP796978A priority Critical patent/JPS54101278A/en
Publication of JPS54101278A publication Critical patent/JPS54101278A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8611—Planar PN junction diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To establish high dielectric strength, by making the substrate surface concentration high for the center and low for the circumference, through the use of planar type semiconductor manufacturing method advantageous in performance and manufacture technology. CONSTITUTION:In forming the impurity diffusion layer of opposite conduction type as the semiconductor substrate 1, two or more impurity diffusion works are made by using photo etching method, and the impurity concentration is lowered to the external side of the surface of impurity diffusion layer and desired angle is taken to the P-N junction toward diffusion depth.
JP796978A 1978-01-26 1978-01-26 Manufacture for semiconductor device Pending JPS54101278A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP796978A JPS54101278A (en) 1978-01-26 1978-01-26 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP796978A JPS54101278A (en) 1978-01-26 1978-01-26 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS54101278A true JPS54101278A (en) 1979-08-09

Family

ID=11680284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP796978A Pending JPS54101278A (en) 1978-01-26 1978-01-26 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54101278A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723262A (en) * 1980-07-16 1982-02-06 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS60198786A (en) * 1984-03-22 1985-10-08 Nec Corp Semiconductor photo receiving element
JPS61101085A (en) * 1984-10-24 1986-05-19 Nec Corp Manufacture of group iii-v semiconductor light-receiving element
JPS63194361A (en) * 1987-02-09 1988-08-11 Toshiba Corp High breakdown voltage planar type semiconductor element

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017583A (en) * 1973-06-14 1975-02-24
JPS5034175A (en) * 1973-07-27 1975-04-02
JPS5081264A (en) * 1973-11-16 1975-07-01

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017583A (en) * 1973-06-14 1975-02-24
JPS5034175A (en) * 1973-07-27 1975-04-02
JPS5081264A (en) * 1973-11-16 1975-07-01

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723262A (en) * 1980-07-16 1982-02-06 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS60198786A (en) * 1984-03-22 1985-10-08 Nec Corp Semiconductor photo receiving element
JPS61101085A (en) * 1984-10-24 1986-05-19 Nec Corp Manufacture of group iii-v semiconductor light-receiving element
JPS63194361A (en) * 1987-02-09 1988-08-11 Toshiba Corp High breakdown voltage planar type semiconductor element

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