JPS61101085A - Manufacture of group iii-v semiconductor light-receiving element - Google Patents
Manufacture of group iii-v semiconductor light-receiving elementInfo
- Publication number
- JPS61101085A JPS61101085A JP59223230A JP22323084A JPS61101085A JP S61101085 A JPS61101085 A JP S61101085A JP 59223230 A JP59223230 A JP 59223230A JP 22323084 A JP22323084 A JP 22323084A JP S61101085 A JPS61101085 A JP S61101085A
- Authority
- JP
- Japan
- Prior art keywords
- junction
- guard ring
- layer
- semiconductor light
- receiving element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229910001423 beryllium ion Inorganic materials 0.000 claims abstract description 10
- 230000001133 acceleration Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 238000002513 implantation Methods 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 230000031700 light absorption Effects 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 125000005842 heteroatom Chemical group 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- PWOSZCQLSAMRQW-UHFFFAOYSA-N beryllium(2+) Chemical compound [Be+2] PWOSZCQLSAMRQW-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は逆バイアス電圧で使用する■−ｖ族半導体受光
素子の、特に、ガードリング効果を有するプレーナ型か
つヘテロ接合型半導体受光素子の製造方法に関する。Detailed Description of the Invention (Industrial Field of Application) The present invention is directed to the manufacture of ■-V group semiconductor photodetectors used at reverse bias voltages, particularly planar and heterojunction semiconductor photodetectors having a guard ring effect. Regarding the method.
（従来技術とその問題点）
現在、元通信用波長域として元ファイバーの伝送損失の
低い１〜１．６μｍ波長域が主流であシ、この波長域に
おいて高速かつ高感度を有する半導体受光素子としてア
バランシ・フォトダイオード（以下ＡＰＤと略記）の研
究開発が進められている。(Prior art and its problems) Currently, the 1 to 1.6 μm wavelength range with low transmission loss of the original fiber is the mainstream wavelength range for communication, and semiconductor photodetectors with high speed and high sensitivity in this wavelength range are used. Research and development of avalanche photodiodes (hereinafter abbreviated as APD) is progressing.
上記波長域に感度を有するＩｎｇ、５３Ｇａ６，４７Ａ
ｓが現在量も多く研究されている。ＩｎＯ，５３Ｇａ０
．４□ＡｓはＩｎＰに格子整合したへテロ接合が可能で
あるため、−ＩｎＧａＡｓ層で光吸収によって発生した
電子−正孔キャリアの正孔のみをＩｎＰ層へ輸送してア
バランシ増倍させるような構造を採用する事により、低
雑音、従って高受信感度を有したＡＰＤが可能となる。Ing, 53Ga6,47A with sensitivity in the above wavelength range
s is currently being studied in large quantities. InO,53Ga0
．． 4□As can form a lattice-matched heterojunction with InP, so a structure is created in which only the electron-hole carrier holes generated by light absorption in the -InGaAs layer are transported to the InP layer and multiplied by avalanche. By adopting this, an APD with low noise and therefore high reception sensitivity becomes possible.
その構造例は、第２図の如くであシ、これは既に特願昭
５４−３９１６９において提案されているｏ 、ｎ ７
ＩｎＰ基板１の上に、ｎ−ＩｎＰバッファ層２ 、 ｎ
”−−１ｎｏ’、５３ＧａＯ，’４７Ａｓ４ａＡｓ−Ｉ
ｎＰｎ電層ｎ−ＩｎＰｎ種層を順次成長した後、ｐ＋型
導電領域５を設けてｐｎ接合を形成している０６は反射
防止を兼ねた表面保護膜、７．８は各々、ｐ側電極、ｎ
側電極である。かかる構造においては電極７−８間に逆
バイアス電圧を印加し、空乏層をＩｎＧａＡｓ層３まで
伸ばす事によって禁制帯幅の狭いＩｎ（１ａＡｓで九を
吸収させ発生した正孔キャリアのみを禁制帯幅の広いＩ
ｎＰ層４内に設けたｐ＋ｎ接合まで輸送し、てアバラン
シ増倍を生じさせている。即ち、禁制帯幅の広いＩｎＰ
で電圧降伏が生じるために、 ＩｎＧａＡｓでのトンネ
ル電流の発生が抑えられ低暗電流受光素子が実現できる
◎しかし、第２図の構造においては、選択的に形成した
ｐｎ接合部の正の曲率を有する部分５ａに高電界が集中
する為、平坦部５ｂよシも低い逆バイアス電圧において
電圧降伏が生じ、受光領域に対応する５ｂの部分で充分
にキャリア増倍が得られないという欠点を有している。An example of its structure is shown in Fig. 2, which has already been proposed in Japanese Patent Application No. 54-39169.
On the InP substrate 1, an n-InP buffer layer 2, n
"--1no', 53GaO, '47As4aAs-I
After successively growing nPn conductive layer n-InPn seed layer, p+ type conductive region 5 is provided to form a pn junction. 06 is a surface protection film which also serves as anti-reflection, 7.8 is a p-side electrode, n
This is the side electrode. In such a structure, by applying a reverse bias voltage between the electrodes 7 and 8 and extending the depletion layer to the InGaAs layer 3, only the hole carriers generated by absorbing In (1aAs), which has a narrow forbidden band width, are absorbed into the forbidden band width. wide I
The light is transported to the p+n junction provided in the nP layer 4, causing avalanche multiplication. In other words, InP with a wide forbidden band width
As voltage breakdown occurs at Since a high electric field is concentrated in the portion 5a, voltage breakdown occurs at a lower reverse bias voltage than in the flat portion 5b, which has the disadvantage that sufficient carrier multiplication cannot be obtained in the portion 5b corresponding to the light-receiving region. ing.
そこで５ａ部が負の曲率を有し、かつ降伏電圧が５ｂ部
よシも高くなる傾斜型接合をｐ＋ｎ接脅接縁周縁部けた
、即ち、第３図に示すような云わゆるガードリング５′
を有する構造が、例えば第３１回応用物理学学術講演会
予稿集３１ｐ−Ｌ−２（昭和５９年３月）に報告されて
いる。しかし、第３図に示す構造においても、周縁降伏
（エツジブレークダウン）の抑えられた均一キャリア増
倍を得るのが困難であった。その理由は以下の通シであ
る０第３図に示すように、第２図の構造にガードリング
５′を適用した場合、ガードリング５′の接合位置が受
光領域５のそれよりもＩｎ（１ａＡｓ層３とＩｎＰｎ電
層のへテロ界面に近接する為、ヘテロ界面に印加される
電界強度は、受光領域５よすもガードリング５′の部分
が高くなる。従って空乏層がＩｎＧａＡｓ層３に達して
いる時、上述した第２図の場合と同様、ガードリングの
曲率部５’ａにおいて電圧降伏が生じてしまい、受光領
域に対応する５ｂの部分でのキャリア増倍が充分に行わ
れないという欠点を有してしまう〇
（発明の目的）
・本発明は、上記の従来の欠点を除去せしめ、ガードリ
ンクにおける電圧降伏が生じる以前に、受光領域で充分
なキャリア増倍を生じさせる構造のＡＰＤの製造方法を
提供することにある。Therefore, a sloped junction in which the portion 5a has a negative curvature and the breakdown voltage is higher than that in the portion 5b is provided at the peripheral edge of the p+n contact, that is, a so-called guard ring 5' as shown in FIG.
A structure having the following is reported, for example, in the Proceedings of the 31st Applied Physics Conference 31p-L-2 (March 1980). However, even in the structure shown in FIG. 3, it was difficult to obtain uniform carrier multiplication with suppressed edge breakdown. The reason for this is as follows.0 As shown in FIG. 3, when the guard ring 5' is applied to the structure shown in FIG. Since the 1aAs layer 3 and the InPn electric layer are close to the hetero interface, the electric field intensity applied to the hetero interface is higher in the light receiving region 5 and in the guard ring 5'. When it reaches that point, voltage breakdown occurs at the curved part 5'a of the guard ring, as in the case of FIG. (Objective of the Invention) - The present invention eliminates the above-mentioned conventional drawbacks and provides a structure that causes sufficient carrier multiplication in the light-receiving region before voltage breakdown occurs in the guard link. An object of the present invention is to provide a method for manufacturing an APD.
（発明の構成）
本発明は、少なくとも、Ｅｇ１＆る禁制帯幅を有する光
吸収層とＥ２（ただし８ｇ２〉Ｅｇｌ）なる禁側帯幅を
有するアバランシ増倍層を積層する工程と、該アバラン
シ増倍層中に選択的にｐ＋ｎ接合を設ける工程とを備え
ている半導体受光素子の製造方法において 、＋ｎ接合
の周縁部にν、なる加速電圧でかつ■）、なる注入量の
ベリリウムイオンを注入して第１の傾斜型ｐｎ接合を設
ける工程及び該第１の傾斜型ｐｎ接合の周縁にＶ２（た
だしＶｍ ”＜ ’Ｖｔ ）なる加速電圧でかつＤ’２
（ただし１）２〈ｒ）ｌ）な□る注入量のベリリウム
イオンを注入して第２の傾斜型ｐｎ接合を設ける工程を
具備することを特徴としている。(Structure of the Invention) The present invention comprises at least a step of laminating a light absorption layer having a forbidden band width of Eg1 & an avalanche multiplication layer having a forbidden band width of E2 (8g2>Egl), and the avalanche multiplication layer. In the method of manufacturing a semiconductor light receiving element, the semiconductor light receiving element is manufactured by implanting beryllium ions into the periphery of the +n junction at an acceleration voltage of ν and an implantation amount of . A step of providing a first inclined pn junction and an acceleration voltage of V2 (however, Vm''<'Vt) and D'2 at the periphery of the first inclined pn junction.
(However, 1) 2〈r)l) The method is characterized by comprising a step of implanting beryllium ions in an implantation amount of □ to form a second graded pn junction.
（発明の作用・原理）
本発明は上述の方法によシ、従来の欠点を解決した◎す
なわち、第３図に示したガードリンク５１の正の曲率を
有する周縁部で生じた電圧降伏を抑える為に、更に該ガ
ードリング（第１のガードリングと称する）周縁部の曲
率を緩和するように、第１のガードリングよシも浅く位
置する新たな第２のガードリングを形成した。(Operation/Principle of the Invention) The present invention solves the conventional drawbacks by using the method described above. In other words, the voltage breakdown that occurs at the peripheral portion of the guard link 51 having a positive curvature as shown in FIG. 3 is suppressed. Therefore, a new second guard ring was formed which is also located shallower than the first guard ring so as to further reduce the curvature of the peripheral edge of the guard ring (referred to as the first guard ring).
ここで、第１及び第２のガードリングをベリリウムのイ
オン注入によって形成した口これは、ベリリウムのイオ
ン注入が最も傾斜型のｐｎ接合を形成し易い事による。Here, the first and second guard rings are formed by beryllium ion implantation. This is because beryllium ion implantation is the easiest to form a sloped pn junction.
第２のガードリングによって第１のガードリングをおお
う為、ガードリングの降伏電圧は第２のガードリングに
よって決まる〇第２のガードリングは、第１のガードリ
ングよシも浅く位置するので、 ＩｎＰ／ＩｎＧａＡ
ａヘテロ界而に印加されるヘテ面電界は、第１のガード
リングのそれよシも小さい。従って第２のガードリング
降伏電圧は。Since the second guard ring covers the first guard ring, the breakdown voltage of the guard ring is determined by the second guard ring. Since the second guard ring is located shallower than the first guard ring, InP /InGaA
The hetero plane electric field applied to the a hetero field is also smaller than that of the first guard ring. Therefore, the second guard ring breakdown voltage is:
第１のガードリングのそれよシも高くなり、受光領域で
のキャリア増倍を充分に行わせる事が可能となる〇
（実施例）
以下、第２図、第３図と同様、Ｉｎｋ／ ＩｎＧａＡｓ
へテロ接合ＡＰＤについて実施例を用いて説明するが、
他ノへテロ接合、例えば、Ａ／ＧａＡｓ／ＧａＡｓ、
Ａ／Ｇａ８ｂ／Ｇａ８ｂ等についても全く同様であるこ
とは容易に理解させる。第１図は本発明による受光素子
の一実施例である。ｎ〜ＩｎＰ基根上に、 ｎ−ＩｎＰ
バッファ層２を１μｍ厚に、３〜５Ｘ１０ ｃｍ
キャリア濃度のｎ−−Ｉｎｏ。５３ＧａＯ０４７Ａｓ層
３を３．５μｍ厚に、波長１．３μｍ相当のＩｎＧａＡ
ｓＰ層３′を０．１〜０．３μｍ厚に、１〜２×１０１
６１３キャリア濃度のｎ−Ｉｎ’Ｐ層４を１．５〜２．
５μｍ厚に、ｌ 〜５ＸｌＯｃｒｔｔ キャリア濃度
のｎ−−ＩｎＰｎ種層を１．５〜２．０μｍ厚に順次形
成した後、第１のガードリング５′及び第２のガードリ
ング５“をベリリウムのイオン注入によって形成した０
第１のガードリングは１００ ｋＶ加速で５ Ｘ １０
” ３−−２ドース量、第２のガードリングは７０に
■加速で３×ｌＯα ドース量のベリリウムを注入し、
しかる後、７００℃２０分間の活性化熱処理を行って、
傾斜型ｒ Ｈ接合を形成した。しかる彼、カドミニウム
を５７０℃の温度で２０分間熱拡散し、所望の深さに接
合が位置する受光領域のｐｎ接合５を形成した。以下、
プラズマ堆積法によるｓ開表面保護膜６及び、電極７９
８を形成し、受光素子を完成させた。The height of the first guard ring also becomes higher, making it possible to sufficiently multiply carriers in the light receiving region.
The heterozygous APD will be explained using an example.
Other heterojunctions, such as A/GaAs/GaAs,
It is easy to understand that the same holds true for A/Ga8b/Ga8b, etc. FIG. 1 shows an embodiment of a light receiving element according to the present invention. n-InP on the n-InP base
Buffer layer 2 is 1 μm thick, 3~5×10 cm
Carrier concentration n--Ino. The 53GaO047As layer 3 has a thickness of 3.5 μm, and the InGaA layer has a wavelength of 1.3 μm.
The sP layer 3' has a thickness of 0.1 to 0.3 μm and is 1 to 2 × 101
The n-In'P layer 4 has a carrier concentration of 1.5 to 2.613.
After successively forming an n--InPn seed layer with a carrier concentration of 1.5 to 2.0 μm to a thickness of 5 μm, the first guard ring 5′ and the second guard ring 5″ are coated with beryllium ions. 0 formed by injection
The first guard ring is 5 x 10 at 100 kV acceleration.
” 3--2 dose, the second guard ring is injected with 3 x lOα dose of beryllium at 70° ■ acceleration,
After that, activation heat treatment was performed at 700°C for 20 minutes,
A tilted rH junction was formed. However, he thermally diffused cadmium at a temperature of 570° C. for 20 minutes to form a pn junction 5 in the light receiving region where the junction was located at a desired depth. below,
S-open surface protection film 6 and electrode 79 by plasma deposition method
8 was formed to complete the light receiving element.
尚、上記の例ではガードリングを形成してからｐ＋ｎ接
合を形成しているが、この逆、すなわち、ｐ＋ｎ接合を
形成した後、ガードリングを形成してもよい。要は、ガ
ードリングをベリリウムのイオン注入工程を２回行って
２つのガードリングを形成することが、本発明のポイン
トである。ｐ＋ｎ接ν飄
合形成前にガードリングを形成するが、後に形成するか
その順序は本質的な問題ではないから、その順序はどち
らでもよいのである。In the above example, the p+n junction is formed after the guard ring is formed, but the guard ring may be formed in the opposite manner, that is, after the p+n junction is formed. The key point of the present invention is to perform the beryllium ion implantation process twice to form two guard rings. Although the guard ring is formed before the formation of the p+n junction v-metal, it is not essential whether it is formed afterwards or in which order, so either order is acceptable.
第１のガードリングのみを形成した時のガードリング降
伏電圧は約１２０■であシ、第２のガードリングも併せ
て形成した時のガードリング降伏電圧は約１５０■であ
って、本発明の効果を実現した。The guard ring breakdown voltage when only the first guard ring is formed is about 120 µ, and the guard ring breakdown voltage when the second guard ring is also formed is about 150 µ, and the guard ring breakdown voltage when only the first guard ring is formed is about 150 µ. achieved the effect.
更に、本発明によって作製したＩｎｋ／ ＩｎＧａＡｓ
ヘテ口接合ＡＰＤの増倍特性は第４図に示す如くであり
、ガードリング部よりも、受光領域における充分なるキ
ャリア増倍が実現された。この時の最大増倍率は４０〜
６０倍であり、従来のｌθ倍程度に比較して著しい改善
がみられた。Furthermore, Ink/InGaAs produced according to the present invention
The multiplication characteristics of the heterojunction APD are as shown in FIG. 4, and more sufficient carrier multiplication was achieved in the light-receiving region than in the guard ring portion. The maximum multiplication factor at this time is 40~
60 times, which is a significant improvement compared to the conventional lθ times.
（発明の効果）
以上、本発明によれば、ガードリング降伏電圧を従来よ
シも高くできるため、受光領域におけるキャリア増倍を
充分に行うことができるという利点を有している。(Effects of the Invention) As described above, according to the present invention, the guard ring breakdown voltage can be made higher than that of the conventional method, so that carrier multiplication in the light-receiving region can be sufficiently performed.
第１図は、本発明により作られたヘテロ接合ＡＰＤの例
を示す図であり、第２図、第３図は、従１は半導体基板
、２は１と同種の半導体バッファ層、３は禁制帯幅の小
さい元吸収層、３′は３と４との中間の禁制帯幅を有す
る半導体層、４は禁制帯幅の大きいアバ２ンシ増倍層、
４′は４と同種で４よりもキャリア濃度の低い半導体層
、５は受光領域のｐｎ接合、５′、５“は各々傾斜型ｐ
ｎ接合を有する第１のガードリング、第２のガードリン
グである。５ａ、５’ａは接合曲率部、５ｂは接合平坦
部、６は表面保護膜、７，８は各々ｐｌｔｔＥ極。
ｎ側電極である〇
代疏人弁理士 白眉 晋
５１図
第２図
鴨３図
粥４図
１こつ、ユノFIG. 1 is a diagram showing an example of a heterojunction APD made according to the present invention, and in FIGS. 2 and 3, subordinate 1 is a semiconductor substrate, 2 is a semiconductor buffer layer of the same type as 1, and 3 is a prohibited 3' is a semiconductor layer with a narrow band width between 3 and 4; 4 is an aberration multiplication layer with a large band gap;
4' is a semiconductor layer of the same type as 4 and has a lower carrier concentration than 4, 5 is a pn junction in the light receiving region, and 5' and 5'' are each a sloped p-n junction.
They are a first guard ring and a second guard ring having an n-junction. 5a and 5'a are joint curvature parts, 5b is a joint flat part, 6 is a surface protective film, and 7 and 8 are respective plttE electrodes. The n-side electrode is a patent attorney who is a patent attorney.
Claims (1)
Ｅ＿ｇ＿２（ただし、Ｅ＿ｇ＿２＞Ｅ＿ｇ＿１）なる禁
制帯幅を有するアバランシ増倍層を積層する工程と、該
アバランシ増倍層中に選択的にｐ＾＋ｎ接合を設ける工
程とを少なくとも備えている半導体受光素子の製造方法
において、ｐ＾＋ｎ接合の周縁部にＶ＿１なる加速電圧
で、かつＤ＿１なる注入量のベリリウムイオンを注入し
て第１の傾斜型ｐｎ接合を設ける工程、及び該第１の傾
斜型ｐｎ接合の周縁にＶ＿２（ただしＶ＿２＜Ｖ＿１）
なる加速電圧で、かつＤ＿２（ただしＤ＿２＜Ｄ＿１）
なる注入量のベリリウムイオンを注入して第２の傾斜型
ｐｎ接合を設ける工程を具備することを特徴とするIII
−Ｖ族半導体受光素子の製造方法。A step of laminating a light absorption layer having a forbidden band width of at least E_g_1 and an avalanche multiplication layer having a forbidden band width of E_g_2 (however, E_g_2>E_g_1), and selectively forming a p^+n junction in the avalanche multiplication layer. In the method of manufacturing a semiconductor light-receiving device, the first graded pn junction is formed by implanting beryllium ions into the peripheral edge of the p^+n junction at an acceleration voltage of V_1 and an implantation amount of D_1. and V_2 (however, V_2<V_1) at the periphery of the first inclined p-n junction.
and D_2 (however, D_2<D_1)
III, characterized by comprising a step of implanting beryllium ions in an implantation amount to form a second graded pn junction.
- A method for manufacturing a group V semiconductor light-receiving element.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223230A JPH06105795B2 (en) | 1984-10-24 | 1984-10-24 | Method for manufacturing group III-V semiconductor light receiving element |
| US06/713,669 US4651187A (en) | 1984-03-22 | 1985-03-19 | Avalanche photodiode |
| DE8585103299T DE3567128D1 (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode and its manufacturing method |
| CA000477076A CA1261450A (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode with double guard ring |
| EP85103299A EP0159544B1 (en) | 1984-03-22 | 1985-03-21 | Avalanche photodiode and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59223230A JPH06105795B2 (en) | 1984-10-24 | 1984-10-24 | Method for manufacturing group III-V semiconductor light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61101085A true JPS61101085A (en) | 1986-05-19 |
| JPH06105795B2 JPH06105795B2 (en) | 1994-12-21 |
Family
ID=16794829
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59223230A Expired - Lifetime JPH06105795B2 (en) | 1984-03-22 | 1984-10-24 | Method for manufacturing group III-V semiconductor light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06105795B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797371A (en) * | 1987-02-26 | 1989-01-10 | Kabushiki Kaisha Toshiba | Method for forming an impurity region in semiconductor devices by out-diffusion |
| JPS6414975A (en) * | 1987-07-08 | 1989-01-19 | Nec Corp | Semiconductor photodetector |
| JPH036946A (en) * | 1989-06-02 | 1991-01-14 | Toho Gas Co Ltd | Intelligent head end for broad band multi-channel lan |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101278A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Manufacture for semiconductor device |
| JPS54102876A (en) * | 1978-01-30 | 1979-08-13 | Mitsubishi Electric Corp | Manufacture for planer type semiconductor device |
| JPS5830164A (en) * | 1981-08-17 | 1983-02-22 | Nippon Telegr & Teleph Corp <Ntt> | Avalanche photodiode and manufacture thereof |
| JPS58157177A (en) * | 1982-03-15 | 1983-09-19 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1984
- 1984-10-24 JP JP59223230A patent/JPH06105795B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54101278A (en) * | 1978-01-26 | 1979-08-09 | Nec Corp | Manufacture for semiconductor device |
| JPS54102876A (en) * | 1978-01-30 | 1979-08-13 | Mitsubishi Electric Corp | Manufacture for planer type semiconductor device |
| JPS5830164A (en) * | 1981-08-17 | 1983-02-22 | Nippon Telegr & Teleph Corp <Ntt> | Avalanche photodiode and manufacture thereof |
| JPS58157177A (en) * | 1982-03-15 | 1983-09-19 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4797371A (en) * | 1987-02-26 | 1989-01-10 | Kabushiki Kaisha Toshiba | Method for forming an impurity region in semiconductor devices by out-diffusion |
| JPS6414975A (en) * | 1987-07-08 | 1989-01-19 | Nec Corp | Semiconductor photodetector |
| JPH036946A (en) * | 1989-06-02 | 1991-01-14 | Toho Gas Co Ltd | Intelligent head end for broad band multi-channel lan |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06105795B2 (en) | 1994-12-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4651187A (en) | Avalanche photodiode | |
| JPH0824199B2 (en) | Manufacturing method of semiconductor light receiving element | |
| JPS5854685A (en) | Avalanche photodiode and manufacture thereof | |
| JPS6058686A (en) | Photodetector and method of producing same | |
| JPS63955B2 (en) | ||
| JPS61101085A (en) | Manufacture of group iii-v semiconductor light-receiving element | |
| JPS60198786A (en) | Semiconductor photo receiving element | |
| JPS61191082A (en) | Semiconductor light receiving element | |
| JPH0382085A (en) | Semiconductor photodetector and manufacture thereof | |
| JPS61101084A (en) | Manufacture of compound semiconductor light-receiving element | |
| JP3055030B2 (en) | Manufacturing method of avalanche photodiode | |
| JP2711055B2 (en) | Semiconductor photodetector and method of manufacturing the same | |
| KR970006610B1 (en) | Buried mesa avalanche photodiode and method of manufacturing the same | |
| JP2766761B2 (en) | Semiconductor photodetector and method of manufacturing the same | |
| JPS63198382A (en) | Semiconductor photodetector and its manufacture | |
| JP2002141547A (en) | Semiconductor photodetector | |
| JPS61267376A (en) | Semiconductor device | |
| JPH02296379A (en) | Avalanche photodiode | |
| JPH02246172A (en) | Manufacture of photodetector | |
| JP2001007378A (en) | Semiconductor light receiving device, and manufacture thereof | |
| JPS61204988A (en) | Semiconductor light receiving element | |
| JPS60173880A (en) | Semiconductor photodetector and manufacture thereof | |
| JPS59177977A (en) | Semiconductor photo detector | |
| JPH0362977A (en) | Long wavelength avalanche photodiode | |
| JP2995751B2 (en) | Semiconductor light receiving element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |