JPS60173880A - Semiconductor photodetector and manufacture thereof - Google Patents
Semiconductor photodetector and manufacture thereofInfo
- Publication number
- JPS60173880A JPS60173880A JP59029728A JP2972884A JPS60173880A JP S60173880 A JPS60173880 A JP S60173880A JP 59029728 A JP59029728 A JP 59029728A JP 2972884 A JP2972884 A JP 2972884A JP S60173880 A JPS60173880 A JP S60173880A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- junction
- light
- avalanche
- inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000000034 method Methods 0.000 claims abstract description 7
- 230000031700 light absorption Effects 0.000 claims description 7
- 239000004744 fabric Substances 0.000 claims 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 6
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000035945 sensitivity Effects 0.000 abstract description 5
- 238000009826 distribution Methods 0.000 abstract description 4
- 229910001425 magnesium ion Inorganic materials 0.000 abstract description 2
- 238000010521 absorption reaction Methods 0.000 abstract 2
- 230000003287 optical effect Effects 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 206010034960 Photophobia Diseases 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910001427 strontium ion Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
- H01L31/1075—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure
Abstract
Description
【発明の詳細な説明】
（１） 技術分野
本発明は半導体受光素子およびその製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field The present invention relates to a semiconductor photodetector and a method for manufacturing the same.
（２）従来技術とその問題点
半導体受光素子の分野においては、低暗電流化、高受信
感度を実現するために禁制帯幅の狭い半導体層で光を吸
収させ、光吸収によって生じたキャリアの一方だけを禁
制帯幅の大きい半導体層へ注入してアバランシ増倍を生
じさせる構造が用いられている。その−例として、現在
光ファイバー通信用に開発の進められているＩｎＰ／Ｉ
ｎＧａＡｓへテロ構造を用いた半導体受光素子の断面図
を第１図に示す。ｎ“−ＩｎＰ基板基板上にｎ −Ｉ
ｎ Ｐバラフッ層２、ｎ −−Ｉ ｎ Ｑ、、４．ｒ’
＋ Ｇ ａ ｉｌ’；１−Ｊｉ Ａｓ ／ＩＪ ３、ｎ
”−Ｉ ｎ Ｐ Ｊ％ ４ ｋ ｌＦ次影形成た後、
熱拡散もしくはイオン注入によりｐ型導電領域５を設け
てｐｎ接合を形成している。６は表面保護を兼ねた反射
防止膜で、７，８は各々ｐ ＩＩｔｌ電極、ｎ側電極で
ある。かかる構造においてはｔ極７−８間に逆バイアス
電圧全印加し、窒乏層をＩｎＧａＡｓ Ｊ脅３まで伸ば
すことによって禁制帯幅の狭いＩｎＧａＡｓ Ｊ脅３で
光を吸収させ、光吸収によって発生した正孔キャリアを
禁制帯幅の大きいＩｎＰ基板１内に設けたｐｎ接合−ま
で輸送してアバランシ増倍を生じさせている。すなわち
禁制帯幅の大きいＩｎＰ基板１で電圧降伏が支配される
ために、低暗電流が実現でき、従って低雑音でかつ島受
信感度がＭ侍できる。(2) Prior art and its problems In the field of semiconductor photodetectors, in order to achieve low dark current and high receiving sensitivity, light is absorbed by a semiconductor layer with a narrow forbidden band, and carriers generated by light absorption are A structure is used in which only one side is injected into a semiconductor layer with a large forbidden band width to cause avalanche multiplication. As an example, InP/I, which is currently being developed for optical fiber communications,
FIG. 1 shows a cross-sectional view of a semiconductor light receiving element using an nGaAs heterostructure. n”-InP substrate n −I on the substrate
n P barrier layer 2, n --I n Q, 4. r'
+ Ga il'; 1-Ji As /IJ 3, n
”-I n P J % 4 k IF After the second shadow formation,
A p-type conductive region 5 is provided by thermal diffusion or ion implantation to form a pn junction. 6 is an antireflection film that also serves as surface protection, and 7 and 8 are a pIItl electrode and an n-side electrode, respectively. In such a structure, by applying a full reverse bias voltage between the t-poles 7 and 8 and extending the nitrogen depletion layer to the InGaAs layer 3, light is absorbed by the InGaAs layer 3, which has a narrow forbidden band width, and the light is generated by light absorption. Hole carriers are transported to a pn junction provided in the InP substrate 1 having a large forbidden band width, thereby causing avalanche multiplication. That is, since the voltage breakdown is dominated by the InP substrate 1 having a large forbidden band width, a low dark current can be realized, and therefore low noise and an island reception sensitivity of M can be achieved.
しかしながら、第１図に示した構造においては、ｐｎ接
合周辺領域９、あるいは表面に露出するｐｎ接合周辺領
域１０において電界集中による電圧降伏が生じるために
、均−増倍層Ｊｌｉ を示す良好な受光感度が得られ難
いという欠点を有しているＧこれを克服するために、第
２図に示すように、Ｉｎ１）アバランシ層４ ｆ ｎ−
ＩｎＰ％％４’とｎ−Ｉ ｎ Ｐ Ｊ脅４０の２層に分
割しかつ、受光周辺部に傾斜型接合をイコするガードリ
ング１１を設ける構造が用いられている。かかる第２図
の構造においては、受光領域のｎ−ＩｎＰｎ種層におい
て優先的に電圧降下を生じさせ、ガードリング領域の降
伏電圧よ−りも小さい降伏電圧を期待するものである。However, in the structure shown in FIG. 1, voltage breakdown occurs due to electric field concentration in the pn junction peripheral region 9 or the pn junction peripheral region 10 exposed on the surface, so that good light reception exhibiting the uniform multiplier layer Jli is caused. In order to overcome this drawback that it is difficult to obtain sensitivity, as shown in FIG.
A structure is used in which the device is divided into two layers, InP%%4' and n-InPJ layer 40, and a guard ring 11 is provided in the light receiving peripheral area to provide an inclined junction. In the structure shown in FIG. 2, a voltage drop is preferentially caused in the n-InPn seed layer in the light-receiving region, and a breakdown voltage smaller than that in the guard ring region is expected.
しかし、受光領域の降伏電圧とガードリング領域の降伏
電圧との差は１０〜２０Ｖ程度であシ、ｐｎ接合周辺部
の増倍全光分に抑制するには至っていない。更に、過剰
雑音指数は１０倍の増倍率において８〜９ｄ１３であり
、充分低いとは答えない。However, the difference between the breakdown voltage of the light-receiving region and the breakdown voltage of the guard ring region is only about 10 to 20 V, and it is not possible to suppress the total amount of light multiplied around the pn junction. Furthermore, the excess noise figure is 8 to 9d13 at a multiplication factor of 10, which is not considered sufficiently low.
（３）発明の目的
従って本発明の目的は、従来のかかる欠点を除き均一な
受光領域の感度分布全示しかつより低雑音の半導体受光
素子およびその製造方法を提供することである。(3) Aim of the Invention Accordingly, an object of the present invention is to provide a semiconductor light-receiving element that eliminates the above-mentioned drawbacks of the conventional semiconductor light-receiving element, exhibits a uniform sensitivity distribution in the light-receiving area, and has lower noise, and a method for manufacturing the same.
（４）発明の構成
本発明は、前述のｐｎ接合の受光領域でかつ光吸収層と
アバランシ増倍層との界面と、前記ｐｎ接合との中間に
光吸収層かつアバランシ増倍層と同じ導電型を有する高
濃度層が選択的に設けられていることを特徴とする半導
体受光素子であり、さらに該高濃度層の最高濃度位置が
前記ｐｎ接合位置から少なくとも０．５μｍ以上離れて
いることを特徴とする半導体受光素子である。さらに、
前記アバランシ増倍層を少なくとも２回以上に分けて形
成する工程を有し、かつ第１回目に形成する第１のアバ
ランシ増倍層の厚さが少なくとも高濃度層を形成する注
入イオンの投射飛程よりも厚くなるように第１のアバラ
ンシ増倍層を形成することを特徴とする上記半導体受光
素子の製造方法である。(4) Structure of the Invention The present invention provides a light absorption layer and an avalanche multiplication layer having the same conductivity as the avalanche multiplication layer in the light receiving region of the pn junction and between the interface between the light absorption layer and the avalanche multiplication layer and the pn junction. A semiconductor light-receiving element characterized in that a high concentration layer having a mold is selectively provided, and the highest concentration position of the high concentration layer is at least 0.5 μm or more away from the pn junction position. This is a characteristic semiconductor light receiving element. moreover,
The step of forming the avalanche multiplication layer in at least two steps or more, and the projection flight of implanted ions such that the thickness of the first avalanche multiplication layer formed in the first step is at least that of a high concentration layer. The method for manufacturing the semiconductor light-receiving device is characterized in that the first avalanche multiplication layer is formed so as to be thicker than the thickness of the first avalanche multiplication layer.
（５）実施例
以下、本発明をＩｎＰ／ＩｎＧａＡｓヘテロ構造受光素
子の実施例について説明するが、他の半導体材料につい
ても全く同様の効果であることは容易に理解される。第
３図は本発明による実施例である０図中の１〜８の名称
は、第１図の従来構造の場合と同一である。】２は本発
明による選択的に受光領域に形成された高濃度層である
。該高濃度層は表面から数μｍ深い領域に位置するため
に、投射飛程が１μｍ以下であるイオン注入法で表面か
らイオンを打ち込んで形成することは困難であシ、従っ
て本発明の製造方法によって形成した。 ｎ＋−ＩｎＰ
基板１の上に、ｎ−ＩｎＰバッファ層２、ｎ−ＩｎＧａ
ＡｓＮ３、第１のアバランシ増倍層であるｎ−ＩｎＰ
４ａを順次成長した後、選択的に受光領域にＳｉイオン
を注入した。ｎ−ＩｎＧａＡｓ層３は３×１ｏ１５ＣＩ
ｎ−３キャリア濃度で４ｐｍ、 ｎ”−ＩｎＰ／酋４
ａは３Ｘ１０１５α キャリア濃度で０．５μｍの厚さ
に形成した。 Ｓ ｒイオンは］ ５０ ｋＶ 加速テ
１．５ Ｘ １ ｏ１２．−２注入した。(5) Example The present invention will be described below with reference to an example of an InP/InGaAs heterostructure light-receiving element, but it is easily understood that the same effect can be obtained with other semiconductor materials. FIG. 3 shows an embodiment according to the present invention. The names 1 to 8 in FIG. 0 are the same as in the conventional structure shown in FIG. 2 is a high concentration layer selectively formed in the light receiving area according to the present invention. Since the high concentration layer is located in a region several μm deep from the surface, it is difficult to form it by implanting ions from the surface using an ion implantation method with a projection range of 1 μm or less. Therefore, the manufacturing method of the present invention Formed by. n+-InP
On the substrate 1, an n-InP buffer layer 2, an n-InGa
AsN3, n-InP which is the first avalanche multiplication layer
After sequentially growing 4a, Si ions were selectively implanted into the light receiving region. n-InGaAs layer 3 is 3×1o15CI
n-3 carrier concentration of 4 pm, n”-InP/4
A was formed to have a carrier concentration of 3×10 15 α and a thickness of 0.5 μm. Sr ions are] 50 kV acceleration te 1.5 X 1 o 12. -2 injected.
このときのＳｉイオンの投射飛程は０．１３μｍであり
、ｎ−ＩｎＰｎ種層はそれ以上の厚さく０．５μｍ）に
設定している。しかる後、第２回目のｎ−ＩｎＰｎ種層
を３Ｘ１０ ｃｍ キャリア濃度で２．５μｍ成長し、
さらにＭｇイオン’ｅ１５０ｋＶ加速でＩ Ｘ １０
”ｃｍ−２注入してｐｎ接合を形成した。このときのｐ
ｎ接合位置は高濃度層１２の最高濃度位置から約１μｍ
離してい、る。次いで、Ｂｅイオン’１ｚ１００ｋＶ加
速で５×＋０１３Ｃｎ１−２注入してガードリング１２
を形成した。The projection range of the Si ions at this time is 0.13 μm, and the thickness of the n-InPn seed layer is set to be greater than that (0.5 μm). After that, a second n-InPn seed layer was grown to 2.5 μm with a carrier concentration of 3×10 cm.
Furthermore, Mg ion 'e150kV acceleration
"cm-2 was implanted to form a pn junction. At this time, p
The n-junction position is approximately 1 μm from the highest concentration position of the high concentration layer 12.
I'm away from you. Next, 5×+013Cn1-2 was implanted with Be ion '1z accelerated at 100kV to form the guard ring 12.
was formed.
（６）発明の作用効果
このようにして作製された本発明による受光素子は、受
光領域の降伏電圧が約９５Ｖであり、ガードリングの降
伏電圧が約１５０Ｖであった。 すなわち従来の降伏電
圧差１０〜２０Ｖよりも大きい降伏電圧差が得られ、均
一な増倍光感度分布を示した。さらに、本発明による素
子の過剰雑音指数は約７．３ｄＢであり、従来の８〜９
ｄＢよりも低いことが明らかであった。この理由は、高
濃度層をｐｎ接合から離して形成することによってｐｎ
接合部の最高電界強度を従来よシも低くすることができ
は、受光領域のｐｎ接合からＩｎｋ−ＩｎＧａＡｓ界面
までの距離を２μｍにして、Ｓ１注入した高濃度層の付
層がＩｎＧａＡｓ層中にあるときは、空乏層幅が低下し
て充分な量子効率を得ることができない。また、高濃度
層がｐｎ接合に近づくと雑音指数が従来よシも高くなる
０すなわち、高濃度層がｐｎ接合から０．５μｍ以上離
れてＩｎＰ層中にあるとき従来よシも低雑音になること
が本発明者によって確認された。高濃度層をｐｎ接合位
階から０．５μｍ以上離せば、従来よりも低雑音になる
ととは注入量、キャリア濃度等の条件を変化させた場合
についても適用できた０以上、本発明の半導体受光素子
によれに：、低雑音でかつ、均一な増倍光感度分布を得
ることができるという利点ヲ有する。(6) Effects of the Invention In the light-receiving element of the present invention manufactured in this way, the breakdown voltage of the light-receiving region was about 95V, and the breakdown voltage of the guard ring was about 150V. That is, a breakdown voltage difference larger than the conventional breakdown voltage difference of 10 to 20 V was obtained, and a uniform multiplication photosensitivity distribution was exhibited. Furthermore, the excess noise figure of the device according to the present invention is about 7.3 dB, compared to 8 to 9 dB of the conventional device.
It was clear that it was lower than dB. The reason for this is that by forming the high concentration layer away from the pn junction,
The maximum electric field strength at the junction can be made lower than before, by setting the distance from the pn junction in the light-receiving region to the Ink-InGaAs interface to 2 μm, so that the high concentration layer injected with S1 is added to the InGaAs layer. In some cases, the depletion layer width decreases and sufficient quantum efficiency cannot be obtained. In addition, when the high concentration layer approaches the pn junction, the noise figure becomes higher than before. In other words, when the high concentration layer is located in the InP layer at a distance of 0.5 μm or more from the pn junction, the noise becomes lower than before. This was confirmed by the inventor. If the high concentration layer is separated by 0.5 μm or more from the pn junction level, the noise will be lower than that of the conventional one. Depending on the device, it has the advantage of being able to obtain low noise and a uniform multiplication light sensitivity distribution.
第１図、第２図は従来の半導体素子の積層構造層の位置
を変えたときの降伏電圧、空乏層幅、過剰雑音指数を示
す図である。第１図から第３図において、ｌは半導体基
板、２は１と同種の半導体バッフγ層、３は禁制帯幅の
小さい光吸収層、４は禁制帯幅の大きいアバランシ層、
４’、４’ｔ４ ａ。
４ｂは４と同一の半導体層、５は４層内に形成したｐｎ
接合、６は表面保護膜、７はｐ側側Ｌ８はｎ Ｉｌｌ！
ｌ電極、９はｐｎ接合周辺領域ｌＯは表面に露出するｐ
ｎ接合周辺部、１１はカードリング、１２は高濃度不純
物イオン注入層である〇
代理人弁理士 内原 ７へ
オ １ 口
７１−２ 図
′１７３ 図FIGS. 1 and 2 are diagrams showing the breakdown voltage, depletion layer width, and excess noise figure when the positions of the laminated structure layers of a conventional semiconductor device are changed. 1 to 3, l is a semiconductor substrate, 2 is a semiconductor buffer γ layer of the same type as 1, 3 is a light absorption layer with a small forbidden band width, 4 is an avalanche layer with a large forbidden band width,
4', 4't4 a. 4b is the same semiconductor layer as 4, and 5 is a pn formed within the 4th layer.
Junction, 6 is surface protective film, 7 is p side L8 is n Ill!
9 is a pn junction peripheral region IO is a p electrode exposed on the surface.
The peripheral part of the n-junction, 11 is a card ring, and 12 is a high-concentration impurity ion implantation layer. 〇Representative Patent Attorney Uchihara 7 Heo 1 Kuchi 71-2 Figure '173 Figure
Claims (1)
を有するアバランシ増倍層を有し、該アバランシ増倍層
中に選択的にｐｎ接合を形成した半導体受光素子におい
て、前記ｐｎ接合の受光領域でかつ、光吸収層とアバラ
ンシ増倍層との界面と前記ｐｎ接合との中間に光吸収層
かつアバランシ増倍層と同じ導電ｆｆｉ’ｒ有する高濃
度層が前記ｐｎ接合位置から少なくとも０５μｎ〕以上
離れて選択的に設けられていることを特徴とする半導体
受光素子。 ” Ｅｇ＋なる禁制帯幅を有する光吸収層を形成する工
程と、この光吸収層上にＥ （Ｅ＞Ｅ ）ｇ２ ｇ２
ｇ＋ なる禁制帯幅を有するアバランシ増倍層を形成する工程
と、アバ２ンシ増倍層中にｐｎ接合を形成する工程とを
少なくとも具備する半導体受光素子の製造方法において
、前記アバランシ増倍層を、少なくとも２回以上に分け
て形成する工程と、第１回目のアバランシ増倍層形成後
に、この第１回目に形成されたアバランシ増倍層にアバ
ランシ増倍層と同じ導布、型の高濃度層を選択的に形成
する工程とを有することを特徴とする半導体受光素子の
製造方法。[Scope of Claims] 1 A light absorbing layer having a forbidden band width of at least E and an avalanche multiplication layer having a forbidden band width of (where 8g2 >Dg); In a semiconductor light-receiving element in which a p-n junction is selectively formed, a light-absorbing layer and an avalanche multiplier layer are provided in the light-receiving region of the p-n junction and between the interface between the light-absorbing layer and the avalanche multiplier layer and the p-n junction. 1. A semiconductor light-receiving device characterized in that a high concentration layer having the same conductivity ffi'r is selectively provided at a distance of at least 05 μn from the pn junction position. ” A step of forming a light absorption layer having a forbidden band width of Eg+, and a step of forming a light absorption layer having a forbidden band width of E
A method for manufacturing a semiconductor light-receiving device, which comprises at least the steps of forming an avalanche multiplication layer having a forbidden band width of g+, and forming a pn junction in the avalanche multiplication layer. , a step of forming the avalanche multiplier layer in at least two or more steps, and after forming the avalanche multiplier layer in the first step, the avalanche multiplier layer formed in the first step is coated with a high concentration of the same conductive fabric and mold as the avalanche multiplier layer. 1. A method for manufacturing a semiconductor light-receiving element, comprising a step of selectively forming layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029728A JPS60173880A (en) | 1984-02-20 | 1984-02-20 | Semiconductor photodetector and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59029728A JPS60173880A (en) | 1984-02-20 | 1984-02-20 | Semiconductor photodetector and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60173880A true JPS60173880A (en) | 1985-09-07 |
Family
ID=12284159
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59029728A Pending JPS60173880A (en) | 1984-02-20 | 1984-02-20 | Semiconductor photodetector and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60173880A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6285477A (en) * | 1985-10-09 | 1987-04-18 | Hitachi Ltd | Photosemiconductor device |
| FR2618257A1 (en) * | 1987-07-17 | 1989-01-20 | Rca Inc | PHOTODIODE AT AVALANCHE. |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57198667A (en) * | 1981-06-01 | 1982-12-06 | Fujitsu Ltd | Light receiving element |
| JPS58206178A (en) * | 1982-05-27 | 1983-12-01 | Fujitsu Ltd | Manufacture of semiconductor light-receiving device |
-
1984
- 1984-02-20 JP JP59029728A patent/JPS60173880A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57198667A (en) * | 1981-06-01 | 1982-12-06 | Fujitsu Ltd | Light receiving element |
| JPS58206178A (en) * | 1982-05-27 | 1983-12-01 | Fujitsu Ltd | Manufacture of semiconductor light-receiving device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6285477A (en) * | 1985-10-09 | 1987-04-18 | Hitachi Ltd | Photosemiconductor device |
| FR2618257A1 (en) * | 1987-07-17 | 1989-01-20 | Rca Inc | PHOTODIODE AT AVALANCHE. |
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