JPS63281480A - Semiconductor photodetector and manufacture thereof - Google Patents

Semiconductor photodetector and manufacture thereof

Info

Publication number
JPS63281480A
JPS63281480A JP62114590A JP11459087A JPS63281480A JP S63281480 A JPS63281480 A JP S63281480A JP 62114590 A JP62114590 A JP 62114590A JP 11459087 A JP11459087 A JP 11459087A JP S63281480 A JPS63281480 A JP S63281480A
Authority
JP
Japan
Prior art keywords
layer
junction
inp
light
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62114590A
Other languages
Japanese (ja)
Inventor
Ichiro Fujiwara
一郎 藤原
Hiroshi Matsuda
広志 松田
Kazuyuki Nagatsuma
一之 長妻
Kazuhiro Ito
和弘 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62114590A priority Critical patent/JPS63281480A/en
Publication of JPS63281480A publication Critical patent/JPS63281480A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce excess noise and dark current, by arranging one or more intermediate layer between a carrier multiplying layer and a window layer, the impurity concentration of said intermediate layer being larger than that of the multiplying layer and the window layer. CONSTITUTION:On N<+> InP substrate 1, the following are grown in order; N<-> InP layer 2, N<-> InGaAs layer 3, N-InP layer 4, N<-> InP layer 5, N-InP layer 6 and N<-> InP layer 7. By applying an SiNx film formed by plasma CVD to a mask, P-type impurity is selectively introduced, and a main junction 8 and a guard ring junction 9 are formed. The positions of the main junction and the guard ring junction are in an N<-> InP layer 7 and N-InP layer 6, respectivety. For a passivation film, a three-layer film 10, i.e., SiNx/PSG/SiO2 is formed. For an antireflection film, SiNx 11 is stuck on a light receiving surface. For a p-type ohmic electrode 12, Au/Pt/Ti is used, and for an N-type ohmic electrode 13, Au/Pd/AuGeNi is used.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアバランシェホトダイオード(以下APDとい
う。)に係わり、特に長波長光通信システムに好適な適
切な動作電圧を有する、低雑音APDに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an avalanche photodiode (hereinafter referred to as APD), and particularly to a low-noise APD having an appropriate operating voltage suitable for long wavelength optical communication systems.

〔従来の技術〕[Conventional technology]

一般に化合物半導体材料を用いた長波長APDでは禁止
帯幅が小さい半導体層で光を吸収し、禁止帯幅が大きい
半導体層で光励起キャリアを増倍するS A M (S
eparated Absorption andMu
] tiplication)構造が採用されている。
In general, in long-wavelength APDs using compound semiconductor materials, light is absorbed in a semiconductor layer with a narrow band gap, and photoexcited carriers are multiplied in a semiconductor layer with a large band gap.
eparated Absorption andMu
] tiplication) structure is adopted.

また、低雑音APDを実現するためには電子と正孔のイ
オン化係数比を大きくする必要がある。イオン化係数比
はp”n接合の最大電界強度に依存し、最大電界強度が
低いほど、イオン化係数比は大きくなる。
Furthermore, in order to realize a low-noise APD, it is necessary to increase the ionization coefficient ratio of electrons and holes. The ionization coefficient ratio depends on the maximum electric field strength of the p''n junction, and the lower the maximum electric field strength, the larger the ionization coefficient ratio.

したがって、低雑音APDを実現するためには、最大電
界強度を低くするような電界分布が必要となる。その−
例として特公昭61−46078号公報に記載されてい
るLo−Hi−Lo型の不純物濃度を持つAPDがある
(第2図)。ここで23は禁止帯幅の小さい光吸収層、
25は禁止帯幅の大きい増倍層であり比較的不純物濃度
が高い中間層24で電界を制御して、主接合に対接する
光吸収層23と中間層24の界面の電界強度を低くし、
禁止帯幅の小さい光吸収層23でバンド間トンネル電流
が発生することを防いでいる。また、増倍層の不純物濃
度が低いため、降伏時の最大電界強度は低くなっている
。ところが、上記L o −H1−Lo不純物濃度分布
を持つAPDでは以下の問題点がある。
Therefore, in order to realize a low-noise APD, an electric field distribution that reduces the maximum electric field strength is required. That-
As an example, there is an APD having a Lo-Hi-Lo type impurity concentration described in Japanese Patent Publication No. 61-46078 (FIG. 2). Here, 23 is a light absorption layer with a small forbidden band width;
Reference numeral 25 denotes a multiplication layer with a large forbidden band width, and controls the electric field in an intermediate layer 24 having a relatively high impurity concentration to lower the electric field intensity at the interface between the light absorption layer 23 and the intermediate layer 24 facing the main junction.
Interband tunneling current is prevented from occurring in the light absorption layer 23, which has a small bandgap width. Furthermore, since the impurity concentration in the multiplication layer is low, the maximum electric field strength at breakdown is low. However, the APD having the above Lo-H1-Lo impurity concentration distribution has the following problems.

イオン化係数比が大きくなるような電界強度を実現する
にはLo層の不純物濃度が、少なくともlXl0”■−
8のオーダは必要となる。ところが、ジャーナル・オブ
・アプライド・フィジックス・レター、第43巻、第6
号(1983年)第594〜596頁(J、 of A
ppl、 Phys、 Lett、、43 、6(19
83)pp、594〜596) において論じられてい
るように、不純物濃度がlXl015■−8の程度にな
ると拡散速度が異常に速い拡散が起り、接合の制御が困
難になるという問題点が生じた。
In order to achieve an electric field strength that increases the ionization coefficient ratio, the impurity concentration of the Lo layer must be at least lXl0”■−
An order of 8 is required. However, Journal of Applied Physics Letters, Volume 43, No. 6
No. (1983), pp. 594-596 (J, of A
ppl, Phys, Lett, 43, 6 (19
83) pp. 594-596), when the impurity concentration reached lXl015■-8, diffusion occurred at an abnormally high diffusion rate, making it difficult to control the junction. .

拡散の制御性が悪くなると、主接合フロントと半導体層
25の距離がばらつくため、空乏層が光吸収層へ到達す
る電圧(パンチスルー電圧)及び、降伏電圧が大きく変
動する。降伏電圧の変動はAPDの動作電圧の変動をも
たらす。
When the controllability of diffusion deteriorates, the distance between the main junction front and the semiconductor layer 25 varies, so the voltage at which the depletion layer reaches the light absorption layer (punch-through voltage) and the breakdown voltage vary greatly. Variations in breakdown voltage result in variations in the APD's operating voltage.

p”n接合と中間層24との距離が大き過ぎる場合、降
伏電圧が100Vを越え、光通信システムに対する適応
性が悪くなる。また、反対にp・n接合と中間層24と
の距離が小さ過ぎる場合、光吸収層23と中間層24の
界面の電界強度が増大し、禁止帯幅の小さい光吸収層2
3でトンネル電流が発生して、暗電流特性を劣化させる
If the distance between the p"n junction and the intermediate layer 24 is too large, the breakdown voltage will exceed 100V, resulting in poor adaptability to optical communication systems. On the other hand, if the distance between the p/n junction and the intermediate layer 24 is too small, If the band gap is too large, the electric field strength at the interface between the light absorption layer 23 and the intermediate layer 24 increases, and the light absorption layer 2 with a small forbidden band width increases.
3, a tunnel current is generated and deteriorates the dark current characteristics.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術は低不純物濃度の接合形成の制御について
配慮されておらず、適切な動作バイアス電圧の変動およ
び暗電流特性など素子性能低下をきたす問題があった。
The above-mentioned conventional technology does not take into account the control of the formation of a junction with a low impurity concentration, and has the problem of deteriorating device performance such as appropriate fluctuations in operating bias voltage and dark current characteristics.

本発明の目的は、不純物濃度、主接合の位置を配慮する
ことによって、適切な動作電圧で、低時電流、低雑音の
APDおよびその製法を提供することにある。゛ 〔問題点を解決するための手段〕 上記目的は、APDを構成する不純物濃度分布を工夫し
、それによって接合位置を制御するこ1とによって達成
される。
An object of the present invention is to provide an APD with an appropriate operating voltage, low current, and low noise by considering the impurity concentration and the position of the main junction, and a method for manufacturing the same. [Means for solving the problem] The above object is achieved by devising the impurity concentration distribution constituting the APD and controlling the junction position accordingly.

すなわち、選択的に不純物を導入して、比較的不純物濃
度が高い半導体層6内に接合を形成する。
That is, impurities are selectively introduced to form a junction in the semiconductor layer 6 having a relatively high impurity concentration.

該半導体層6は不純物濃度が低い半導体層5に接してい
る。
The semiconductor layer 6 is in contact with the semiconductor layer 5 having a low impurity concentration.

本不純物濃度構造において半導体層7の表面から他方の
導電形の不純物を導入すると、接合は、拡散係数の大き
い該半導体層7を越え、拡散速度の遅い不純物濃度の大
きい半導体層6内に形成される。
In this impurity concentration structure, when an impurity of the other conductivity type is introduced from the surface of the semiconductor layer 7, a junction is formed beyond the semiconductor layer 7, which has a large diffusion coefficient, and into the semiconductor layer 6, which has a large impurity concentration and has a slow diffusion rate. Ru.

〔作用〕[Effect]

第1図において、比較的不純物濃度が高い半導体層6は
、p’n接合の位置を半導体層6内に位置させるように
動作する。入射光は不純物濃度の低い半導体層3によっ
て吸収され、生じた光励起キャリアは、不純物濃度が低
い5で主として増倍される。また、比較的不純物濃度の
高い半導体層5によって、APD全体の電界分布を制御
している。
In FIG. 1, the semiconductor layer 6 having a relatively high impurity concentration operates so that the p'n junction is located within the semiconductor layer 6. The incident light is absorbed by the semiconductor layer 3 having a low impurity concentration, and the generated photoexcited carriers are mainly multiplied by the semiconductor layer 3 having a low impurity concentration. Further, the electric field distribution of the entire APD is controlled by the semiconductor layer 5 having a relatively high impurity concentration.

これら技術的手段により、接合の位置は安定に制御でき
るようになるため、再現性よく特性の優れたAPDを得
ることができる。
By using these technical means, the position of the bond can be stably controlled, so that an APD with excellent characteristics can be obtained with good reproducibility.

〔実施例〕〔Example〕

以下、本発明の実施例を図を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

実施例1 本実施例ではInP系材系材用いた場合について第1図
を用いて説明する。
Example 1 In this example, a case where an InP-based material is used will be explained using FIG. 1.

第1図はプレーナ型InGaAs/ InPAPDの断
面構造図である。
FIG. 1 is a cross-sectional structural diagram of a planar type InGaAs/InPAPD.

まず、製造方法を述べる。First, the manufacturing method will be described.

n+−InP基板1」二に、気相成長法(例えばMBE
法、MOCVD法、ハイドライドまたはハライドVPE
法)を用いて順次、n−−InP層2 (No = I
 X 10”an−8,厚さ0.57zm)  。
n+-InP substrate 1'' Second, vapor phase growth method (for example, MBE
method, MOCVD method, hydride or halide VPE
n--InP layer 2 (No = I
x 10”an-8, thickness 0.57zm).

n−−InGaAs層3(Nn = I X 10’δ
1m −’ 、厚さ3μm)、n−102層4 (No
= 1−5 X 1016an−8゜厚さ1−1.5 
μm)、 n−−I n P層5(No=I X 10
15an−8,厚さ0.2 −1 pm) 、  n 
−InP層6 (No= 1〜5 X 1018an−
8,厚さ0.2−0,4μm)、n−−I n P層7
 (No= I X 10 ”Qn −8,厚さ2.5
〜3.5μm)を成長させる。
n--InGaAs layer 3 (Nn = I x 10'δ
1 m −', thickness 3 μm), n-102 layer 4 (No.
= 1-5 x 1016an-8゜thickness 1-1.5
μm), n--I n P layer 5 (No=I x 10
15an-8, thickness 0.2-1 pm), n
-InP layer 6 (No = 1 to 5 x 1018an-
8, thickness 0.2-0.4 μm), n--I n P layer 7
(No=I X 10"Qn -8, thickness 2.5
~3.5 μm).

プラズマCVDによって形成したSiNx膜をマスクに
、選択的にp型不純物を導入し、主接合8ガードリング
接合9を形成する。p型不純物領域の形成においては、
ZnまたはCdの熱拡散、あるいはBeやMgなどのイ
オン打込み法が取られる。主接合及びガードリング接合
の位置は、それぞれn−−InP層7及びn −I n
 P層6内に形成する。次に、パッシベーション膜とし
て、S i N x / P S G / S i O
2,三層膜10を形成し、受光面上には反射防止膜とし
てS i N x 11を被着した。
Using the SiNx film formed by plasma CVD as a mask, p-type impurities are selectively introduced to form main junctions 8 and guard ring junctions 9. In forming the p-type impurity region,
Thermal diffusion of Zn or Cd, or ion implantation of Be, Mg, etc., is used. The positions of the main junction and guard ring junction are n--InP layer 7 and n-InP layer 7, respectively.
It is formed in the P layer 6. Next, as a passivation film, S i N x / P S G / S i O
Two- and three-layer films 10 were formed, and S i N x 11 was deposited on the light-receiving surface as an antireflection film.

p型オーミック電極12にはA u / P t / 
T i 。
The p-type ohmic electrode 12 has A u / P t /
Ti.

n型オーミック電極13にはA u / P d / 
AuGeNiをそれぞれ用いた。
The n-type ohmic electrode 13 has A u / P d /
AuGeNi was used in each case.

次にこの素子の動作について述べる。Next, the operation of this element will be described.

本素子に入射した光は逆バイアス電圧によって空乏層化
されている半導体層3内でほとんど吸収され光励起キャ
リアを発生する。生成した光励起キャリア(この場合は
ホール)はドリフト電界により、キャリア増倍層5へ注
入される。該増倍層5には高電界が印加されているため
、二次イオン化により注入されたキャリアを効率よく増
倍する。
Most of the light incident on this device is absorbed within the semiconductor layer 3, which is depleted by the reverse bias voltage, and photoexcited carriers are generated. The generated photoexcited carriers (holes in this case) are injected into the carrier multiplication layer 5 by the drift electric field. Since a high electric field is applied to the multiplication layer 5, carriers injected by secondary ionization are efficiently multiplied.

増倍されたキャリアは主接合に集められ、光電流として
外部回路に取り出される。
The multiplied carriers are collected at the main junction and taken out as a photocurrent to an external circuit.

本実施例では、p’n接合の位置が±0.1μm以内に
正確に制御できるため、適切な動作電圧をもちかつ、低
暗電流のAPDを実現できる。また、増倍領域の不純物
濃度が低いため、アバランシェ降伏時の最大電界強度が
低くなり、イオン化係数比を大きくできる。その結果、
増倍に伴う過剰雑音が小さくなり、低雑音APDを実現
できる。
In this embodiment, since the position of the p'n junction can be accurately controlled within ±0.1 μm, an APD with an appropriate operating voltage and low dark current can be realized. Furthermore, since the impurity concentration in the multiplication region is low, the maximum electric field strength at the time of avalanche breakdown is low, and the ionization coefficient ratio can be increased. the result,
Excessive noise accompanying multiplication is reduced, and a low-noise APD can be achieved.

実施例2 第2図に別の実施例を説明する。第1図と異なるのは半
導体層3と4の間に禁止帯幅(λg=1.3μm)のI
nGaAsP層が挿入しであることである。
Embodiment 2 Another embodiment will be described in FIG. The difference from FIG. 1 is that there is a forbidden band width (λg=1.3 μm) between semiconductor layers 3 and 4.
The nGaAsP layer is inserted.

その製造方法については、実施例1と基本的には同様で
あり、n+ −InP基板上に気相成長法によりn−−
InP42.n−−InGaAs43゜n−−InGa
AsP44.n−I nP45.n−−InP46゜n
−InP47.n−−InP48を成長させた後、周知
のプロセス技術を用いて、主接合49゜ガードリング5
0.パッシベーション膜512反射防止膜52.p型オ
ーミック電極53.n型オーミック電極54を形成する
The manufacturing method is basically the same as that in Example 1, and n--
InP42. n--InGaAs43゜n--InGa
AsP44. n-I nP45. n--InP46゜n
-InP47. After growing n--InP48, the main junction 49° guard ring 5 is formed using well-known process technology.
0. Passivation film 512 Anti-reflection film 52. p-type ohmic electrode 53. An n-type ohmic electrode 54 is formed.

実施例2では、InGaAs43とInP45のへテロ
界面での価電子帯でのエネルギー不連続(約0.6V)
を緩和するために、禁止帯幅が43と45の中間の値(
λ、=4.3μm) をもつInGaAsP44を挿入
しである。44の挿入により、ヘテロ界面のエネルギー
不連続を約0.3■に低減できるため、ヘテロ界面の電
界強度を十分高くすることなく、ホールのパイルアップ
現象を抑止し、高速応答を実現することができる。
In Example 2, energy discontinuity (approximately 0.6 V) in the valence band at the hetero interface of InGaAs43 and InP45
In order to alleviate this, the forbidden band width is set to a value between 43 and 45 (
λ, = 4.3 μm) was inserted. By inserting 44, the energy discontinuity at the heterointerface can be reduced to approximately 0.3■, so it is possible to suppress the hole pile-up phenomenon and achieve high-speed response without making the electric field strength at the heterointerface sufficiently high. can.

したがって、実施例2においては、適切なバイアス電圧
をもち、低暗電流、高速、高感度のAPDを制御性よく
実現することができる。
Therefore, in the second embodiment, an APD with an appropriate bias voltage, low dark current, high speed, and high sensitivity can be realized with good controllability.

以上InGaAs/ I n P系について述べてきた
が、InPをInAffiAsに置きかえたInA1A
s系 InA1As系においても、本発明は有効である
The InGaAs/I n P system has been described above, but InA1A in which InP is replaced with InAffiAs
The present invention is also effective for the s-based InA1As system.

また、本発明の本質は、InP系の材料以外、例えばG
 a S b系など他の化合物半導体を用いた場合、他
にm−v族化合物と、Ge、Siの組合せたものにおい
ても変るものではない。
Moreover, the essence of the present invention is that materials other than InP-based materials, such as G
When other compound semiconductors such as aSb-based semiconductors are used, the same applies to combinations of m-v group compounds, Ge, and Si.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、比較的不純物濃度の高い禁止帯幅の大
きい半導体層内に制御性よ<p−n接合を形成でき、か
つ増倍層の不純物濃度を低くできるため、以下のような
効果がある。
According to the present invention, it is possible to form a p-n junction with good controllability in a semiconductor layer with a relatively high impurity concentration and a large band gap, and the impurity concentration of the multiplication layer can be reduced, so that the following effects can be achieved. There is.

(1)キャリア増倍層でのイオン化係数比を大きくする
ことができるため、過剰雑音を小さくできる。
(1) Since the ionization coefficient ratio in the carrier multiplication layer can be increased, excess noise can be reduced.

(2)禁止帯幅の小さい光吸収層での電界強度を適正な
値に制御することができるため、バンド間トンネル電流
の発生を抑止でき、降伏電圧近傍の暗電流を小さくでき
る。
(2) Since the electric field strength in the light absorption layer with a small forbidden band width can be controlled to an appropriate value, generation of interband tunneling current can be suppressed, and dark current near the breakdown voltage can be reduced.

(3)パンチスルー電圧、降伏電圧等を正確に制御でき
るようになるため、再現性が向上し、工場生産での歩留
りの向上が期待できる。
(3) Punch-through voltage, breakdown voltage, etc. can be accurately controlled, which improves reproducibility and can be expected to improve yield in factory production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例1に示す素子の断面構造図、第
2図は、従来のAPDの断面構造図、および第3図は、
本発明の実施例2に示す素子の断面構造図である。 l−−・n+−InP基板、2−n−−InP層、3−
n−InGaAs光吸収層、4− n −I n P電
界緩和層、5−n−−I nP増倍層、6− n −I
 n P中間層、7・・・n−−InP窓層、8・・・
p−InP(主接合)、9・・・p−−InP(ガード
リング)、10・・・パッシベーション膜、11.・・
・反射防止膜、12・・・P型オーミック電極、13・
・・n型オーミック電極、21−n+ −I n P基
板、22−n−−InP層、23− n −−InGa
As光吸収層、24・・・n −I n P電界緩和層
、25・・・n−−InP増倍層、窓層、26−p−I
nP (主接合)、27・・・p−−InP(ガードリ
ング)、28・・・パッシベーション膜、29・・・反
射防止膜、30・・・p型オーミック電極、31・・・
n型オーミック電極、41−n+ −I n P基板、
42−n−−I n P層、43−n−−I nGaA
s光吸収層、44− n −−InGaAsPバッファ
層(1g = 1.3 pm)  、 45−−− n
 −I n P電界緩和層、46−n−−I n P増
倍層、47− n −I n P中間層、48−n−−
InP窓層、49−p−InP(主接合)、50・・・
p−−InP(ガードリング)、51・・・パッシベー
ション膜、52・・・反射防止膜、53・・・p型オー
ミック電極、54・・・n型オーミック電極。
FIG. 1 is a cross-sectional structural diagram of a device shown in Example 1 of the present invention, FIG. 2 is a cross-sectional structural diagram of a conventional APD, and FIG.
FIG. 3 is a cross-sectional structural diagram of an element shown in Example 2 of the present invention. l--/n+-InP substrate, 2-n--InP layer, 3-
n-InGaAs light absorption layer, 4-n-I nP electric field relaxation layer, 5-n--I nP multiplication layer, 6-n-I
nP intermediate layer, 7...n--InP window layer, 8...
p-InP (main junction), 9... p--InP (guard ring), 10... passivation film, 11.・・・
・Anti-reflection film, 12... P-type ohmic electrode, 13.
...n-type ohmic electrode, 21-n+ -InP substrate, 22-n--InP layer, 23-n--InGa
As light absorption layer, 24...n-I nP electric field relaxation layer, 25...n--InP multiplication layer, window layer, 26-p-I
nP (main junction), 27... p--InP (guard ring), 28... passivation film, 29... antireflection film, 30... p-type ohmic electrode, 31...
n-type ohmic electrode, 41-n+ -I n P substrate,
42-n--I nP layer, 43-n--I nGaA
s light absorption layer, 44-n --InGaAsP buffer layer (1g = 1.3 pm), 45--n
-I nP electric field relaxation layer, 46-n--I nP multiplication layer, 47- n -I nP intermediate layer, 48-n--
InP window layer, 49-p-InP (main junction), 50...
p--InP (guard ring), 51... passivation film, 52... antireflection film, 53... p-type ohmic electrode, 54... n-type ohmic electrode.

Claims (1)

【特許請求の範囲】 1、一方の導電形を持つ基板上に少なくとも光を吸収す
る光吸収層及び光を吸収して生じたキャリアを増倍する
増倍層、p・n接合(主接合)を有する窓層を含む複数
の半導体層を積層して構成される半導体受光素子におい
て、キャリア増倍層と窓層の間に不純物濃度が当該増倍
層および当該窓層のそれより大きい中間層を1以上有す
ることを特徴とする半導体受光素子。 2、前記中間層内に前記p・n接合(主接合)を形成し
たことを特徴とする特許請求の範囲第1項記載の半導体
受光素子。 3、前記中間層内に前記p・n接合(主接合)を形成し
、ガードリング接合を前記窓層内に有することを特徴と
する特許請求の範囲第1項記載の半導体受光素子。 4、前記中間層の、不純物濃度が1×10^1^8cm
^−^3〜1×10^1^7cm^−^3で、厚さが0
.1〜0.4μmである特許請求の範囲第1項記載の半
導体受光素子。 5、基板上に、受光機能を有する主接合を含む、半導体
を形成する諸工程でなる半導体受光素子の製造方法にお
いて、1方の導電形を有し、不純物濃度が小さい、キャ
リアを増倍する半導体層(増倍層)及び光を透過する半
導体層(密層)を形成する工程の間に中間層を形成する
工程を有することを特徴とする半導体受光素子の製造方
法。 6、前記主接合を前記中間層内に、エッジ降伏を抑止す
るガードリング接合を前記窓層内に形成することを特徴
とする特許請求の範囲第5項記載の半導体受光素子の製
造方法。
[Claims] 1. A light absorption layer that absorbs at least light on a substrate having one conductivity type, a multiplication layer that multiplies carriers generated by absorbing light, and a p/n junction (main junction). In a semiconductor light-receiving device configured by laminating a plurality of semiconductor layers including a window layer having A semiconductor light-receiving element characterized by having one or more. 2. The semiconductor light-receiving device according to claim 1, wherein the p/n junction (main junction) is formed within the intermediate layer. 3. The semiconductor light-receiving device according to claim 1, wherein the p/n junction (main junction) is formed in the intermediate layer, and a guard ring junction is provided in the window layer. 4. The impurity concentration of the intermediate layer is 1×10^1^8 cm
^-^3~1x10^1^7cm^-^3, thickness is 0
.. The semiconductor light receiving element according to claim 1, which has a thickness of 1 to 0.4 μm. 5. In a method for manufacturing a semiconductor light-receiving element, which includes various steps of forming a semiconductor on a substrate, including a main junction having a light-receiving function, the semiconductor light-receiving element has one conductivity type, has a low impurity concentration, and multiplies carriers. A method for manufacturing a semiconductor light-receiving element, comprising the step of forming an intermediate layer between the steps of forming a semiconductor layer (multiplier layer) and a light-transmitting semiconductor layer (dense layer). 6. The method of manufacturing a semiconductor light-receiving device according to claim 5, characterized in that the main junction is formed in the intermediate layer, and the guard ring junction for suppressing edge breakdown is formed in the window layer.
JP62114590A 1987-05-13 1987-05-13 Semiconductor photodetector and manufacture thereof Pending JPS63281480A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62114590A JPS63281480A (en) 1987-05-13 1987-05-13 Semiconductor photodetector and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62114590A JPS63281480A (en) 1987-05-13 1987-05-13 Semiconductor photodetector and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS63281480A true JPS63281480A (en) 1988-11-17

Family

ID=14641666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62114590A Pending JPS63281480A (en) 1987-05-13 1987-05-13 Semiconductor photodetector and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS63281480A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH036871A (en) * 1989-06-02 1991-01-14 Mitsubishi Electric Corp Photodetecting element
US4992386A (en) * 1988-12-14 1991-02-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor light detector
US5281844A (en) * 1991-04-18 1994-01-25 Mitsubishi Denki Kabushiki Kaisha Avalanche photodiode
EP0600746A1 (en) * 1992-12-04 1994-06-08 Nec Corporation Avalanche photo-diode

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4992386A (en) * 1988-12-14 1991-02-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor light detector
JPH036871A (en) * 1989-06-02 1991-01-14 Mitsubishi Electric Corp Photodetecting element
US5281844A (en) * 1991-04-18 1994-01-25 Mitsubishi Denki Kabushiki Kaisha Avalanche photodiode
US5346837A (en) * 1991-04-18 1994-09-13 Mitsubishi Denki Kabushiki Kaisha Method of making avalanche photodiode
EP0600746A1 (en) * 1992-12-04 1994-06-08 Nec Corporation Avalanche photo-diode

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