JPH036871A - Photodetecting element - Google Patents
Photodetecting elementInfo
- Publication number
- JPH036871A JPH036871A JP1141791A JP14179189A JPH036871A JP H036871 A JPH036871 A JP H036871A JP 1141791 A JP1141791 A JP 1141791A JP 14179189 A JP14179189 A JP 14179189A JP H036871 A JPH036871 A JP H036871A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type alinas
- electric field
- multiplication
- multiplying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 230000031700 light absorption Effects 0.000 claims abstract description 17
- 230000001133 acceleration Effects 0.000 claims abstract description 11
- 239000000203 mixture Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 17
- 238000009825 accumulation Methods 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 125000005842 heteroatom Chemical group 0.000 description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、光検出素子に係り、特になだれ増倍フォト
ダイオードの高速動作および動作電圧に低減に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photodetection element, and particularly to high-speed operation and reduction in operating voltage of an avalanche multiplication photodiode.
第3図は、例えばAppl Phys Lett Vo
l、45.1984p968−970に示されたものと
同様な従来の光検出素子を示す断面図であり、この図に
おいて、1はp”−InP基板、2はp−1nGaAs
光吸収層、4はp−−All I nAs層、5はp”
−AILInAs層、7はn”−A、j2InAs層
、8はp側電極、9はn側電極、10はp−−An I
nAs増倍層であって、その層厚は1μmである。FIG. 3 shows, for example, Appl Phys Lett Vo
1, 45.1984 p968-970, in which 1 is a p''-InP substrate and 2 is a p-1nGaAs substrate.
Light absorption layer, 4 is p--All InAs layer, 5 is p''
-AILInAs layer, 7 is n''-A, j2InAs layer, 8 is p-side electrode, 9 is n-side electrode, 10 is p--An I
The nAs multiplication layer has a layer thickness of 1 μm.
次に動作について説明する。Next, the operation will be explained.
図の上側から入射した光は光吸収層2で吸収されて電子
−正孔対を生成するが、p−−AJZInAs増倍層1
0からp” −All I nAs層°5およびp−−
All I nAs層4を通して光吸収層2まで伸びて
いるn−p接合の空乏領域の電界により、電子はn”
−AJ2 I nAs層7に向かって加速され、光吸収
による電流として検出することができる。ここで、n−
p接合は逆方向バイアスされており、各接合での電界は
トンネル電流が支配的にならない位に小さく、かつ各接
合で電子の蓄積が生じない程度に大きくし、n−p接合
での電界がなだれ破壊を生じる程度に大きくすれば、空
乏領域で加速された電子はなだれ破壊によりあらたに電
子−正孔対を生成するため、光生成電流は増倍され、感
度を大きくすることができる。この構造ではp−−A、
Q I nAs増倍層10の層厚が1μmと大きいため
に、なだれ増倍の立上り時間が大きく、さらにAl2I
nAs層群、p−−AuInAs層4.p”−AftI
nAs層5.n9Aj2 I nAs層7.P−−Al
2 I nAs増倍層10とp−1nGaAs光吸収層
2とのへテロ界面での光生成キャリアの蓄積が生じて高
速動作が困難である。Light incident from the upper side of the figure is absorbed by the light absorption layer 2 and generates electron-hole pairs, but the p--AJZInAs multiplication layer 1
0 to p''-All I nAs layer °5 and p--
Due to the electric field in the depletion region of the n-p junction extending through the All I nAs layer 4 to the light absorption layer 2, electrons are
-AJ2 In is accelerated toward the nAs layer 7 and can be detected as a current due to light absorption. Here, n-
The p-junction is reverse-biased, and the electric field at each junction is small enough that tunnel current does not become dominant and large enough that electrons do not accumulate at each junction, so that the electric field at the n-p junction is If it is made large enough to cause avalanche destruction, the electrons accelerated in the depletion region will generate new electron-hole pairs due to the avalanche destruction, so the photogenerated current will be multiplied and the sensitivity can be increased. In this structure, p--A,
Since the layer thickness of the QI nAs multiplication layer 10 is as large as 1 μm, the rise time of avalanche multiplication is long, and the Al2I
nAs layer group, p--AuInAs layer 4. p”-AftI
nAs layer5. n9Aj2 I nAs layer7. P--Al
Accumulation of photogenerated carriers occurs at the hetero interface between the 2 InAs multiplication layer 10 and the p-1nGaAs light absorption layer 2, making high-speed operation difficult.
(発明が解決しようとする課題)
上記のような従来の光検出素子は、ヘテロ界面で光生成
キャリアが蓄積するため高速動作に問題があった。また
、p−−All I nAs増倍層10の層厚が大きい
ため、動作電圧も大きくなっていた。(Problems to be Solved by the Invention) Conventional photodetecting elements as described above have a problem in high-speed operation because photogenerated carriers accumulate at the hetero interface. Furthermore, since the layer thickness of the p--All I nAs multiplication layer 10 was large, the operating voltage was also large.
この発明は、上記のような問題点を解消するためになさ
れたもので、高速動作を実現するとともに、なだれ増倍
動作する電圧も十分低い光検出素子を得ることを目的と
する。The present invention has been made to solve the above-mentioned problems, and aims to provide a photodetecting element that can operate at high speed and at a sufficiently low voltage for avalanche multiplication.
〔課題を解決するための手段)
この発明に係る光検出素子は、p−−Al2 I nA
s増倍層の層厚を0.17〜0.25μmとし、そのキ
ャリア濃度を2xlO”cm−3以下とするとともに、
光吸収層とp−−Aft I nAs層間にこれらの中
間の組成のキャリア加速層を形成したものである。[Means for Solving the Problems] A photodetecting element according to the present invention includes p--Al2I nA
The layer thickness of the s multiplication layer is set to 0.17 to 0.25 μm, and the carrier concentration is set to 2×lO”cm−3 or less,
A carrier acceleration layer having a composition intermediate between these layers is formed between the light absorption layer and the p--Aft InAs layer.
(作用)
この発明においては、キャリア濃度の差によってなだれ
増倍が生じる電圧が単一のキャリア濃度の増倍層の場合
よりも低下するほか、狭い増倍領域とすることによって
、なだれ増倍立上り時間が減少する。また、中間の組成
のキャリア加速層を導入したことによりヘテロ界面での
キャリアの蓄積が防止される。(Function) In this invention, the voltage at which avalanche multiplication occurs due to the difference in carrier concentration is lower than that in the case of a multiplication layer with a single carrier concentration. Time decreases. Further, by introducing a carrier acceleration layer having an intermediate composition, accumulation of carriers at the hetero interface is prevented.
〔実施例]
第1図はこの発明の光検出素子の一実施例を示す断面図
であり、この図において、1はp+InP基板、2はp
−InGaAs光吸収層、3はp−Al1 I nGa
Asキャリア加速層、4はp−−All I nAs層
、5はp” −All I nAs層、6はp−−Af
t I nAs増倍層、7はn+A1InAs層、8は
p側電極、9はn側電極である。ここで、p−−Aff
iInAs増倍層6は、層厚を0,17〜0.25μm
7キヤリア濃度を2×1015cm−3以下としている
。[Example] FIG. 1 is a sectional view showing an example of the photodetecting element of the present invention. In this figure, 1 is a p + InP substrate, 2 is a p
-InGaAs light absorption layer, 3 is p-Al1InGa
As carrier acceleration layer, 4 p--All I nAs layer, 5 p"-All I nAs layer, 6 p--Af
t I nAs multiplication layer, 7 is an n+A1InAs layer, 8 is a p-side electrode, and 9 is an n-side electrode. Here, p--Aff
The iInAs multiplication layer 6 has a layer thickness of 0.17 to 0.25 μm.
7 carrier density is set to 2×10 15 cm −3 or less.
なお、p−−Aft I nAs増倍層6の層厚キャリ
ア濃度は次のようにし2て設計する。Note that the layer thickness and carrier concentration of the p--Aft InAs multiplication layer 6 are designed as follows.
なだれ増倍フォトダイオードにおいて、この発明のよう
な電子注入型では、増倍率Mは次式で示される(今井他
偏、化学半導体デバイス(II)工業調査会(1985
)参照)。In the avalanche multiplication photodiode, in the electron injection type as in the present invention, the multiplication factor M is expressed by the following formula (Imai et al., Chemical Semiconductor Device (II) Industrial Research Group (1985)
)reference).
の発明は、2層を多層構造とじ03層と隣接する層を低
キヤリア濃度化している構造であり、p−n接合の高電
界部がこの低キヤリア濃度化した層(P−−Au I
nAs増倍層6に相当)だけとなるようにすることがで
きる。また、この高電界部の電界値は一定にすることが
でき、第 (1)式は次のようになる(α、βがXによ
らず一定である)。The invention has a structure in which the two layers are combined into a multilayer structure, and the layer adjacent to the 03 layer has a low carrier concentration, and the high electric field part of the p-n junction is made of this low carrier concentration layer (P--Au I
(corresponding to the nAs multiplication layer 6). Further, the electric field value in this high electric field portion can be kept constant, and Equation (1) becomes as follows (α and β are constant regardless of X).
ここで、WMは高電界部の幅(n+層と隣接した低キヤ
リア濃度化した層、p−−All I nAs増倍層6
の幅)である。Here, WM is the width of the high electric field part (the layer with low carrier concentration adjacent to the n+ layer, the p--All I nAs multiplication layer 6
width).
なだれ増倍は第 (2)式において分母−〇のとき生じ
るので、
・・・・・・ (1)
ここで、α(X)は電子のイオン化係数、β(y)は正
孔のイオン化係数であり、空乏層がx=0からX=Wま
で伸びているとして積分している。こがなだれ増倍条件
となる。第 (3)式にα、βとして報告されている値
(渡辺他、第36回春季応物予fa4a−ZB−7,p
947 (1989)参照)。Avalanche multiplication occurs when the denominator is -0 in equation (2), so... (1) Here, α(X) is the ionization coefficient of electrons, and β(y) is the ionization coefficient of holes. The depletion layer is integrated assuming that it extends from x=0 to X=W. This is the avalanche multiplication condition. The values reported as α and β in equation (3) (Watanabe et al., 36th Spring Science Preliminary Fa4a-ZB-7, p
947 (1989)).
a= 8.6・10’ exp (−3,5・1
06/E) [cm−’]−(4a)β= 2.3
・10’ exp (−4,5・106/E)
[cm−’]−(4b)ただし、E:v/cm
を用いて、WoとEの関係を求めた結果を第2図に示す
。ここで、電界値としてp−n接合の高電界部でトンネ
ル電流が大きくならないようにするため、E≦7.2X
10’ v/Cmに限定される。このため、WMは−
0,17μm以上に限定される。a= 8.6・10' exp (-3,5・1
06/E) [cm-']-(4a)β= 2.3
・10' exp (-4,5・106/E)
[cm-']-(4b) However, FIG. 2 shows the results of determining the relationship between Wo and E using E:v/cm. Here, in order to prevent the tunnel current from becoming large in the high electric field part of the p-n junction as the electric field value, E≦7.2X
Limited to 10'v/Cm. Therefore, WM is −
It is limited to 0.17 μm or more.
WMは小さい方が高速応答性、動作電圧の低減に対して
有利なため、実効的なWM(P−−All I nAs
増倍層6の層厚)は0.17〜0.25μmとする。ま
た、キャリア濃度は幅WMにわたって電界値を一定とす
るために2.10”以下に下げている。Since a smaller WM is advantageous for faster response and lower operating voltage, effective WM (P--All I nAs
The layer thickness of the multiplication layer 6 is set to 0.17 to 0.25 μm. Further, the carrier concentration is lowered to 2.10'' or less in order to keep the electric field value constant over the width WM.
次に動作について説明する。Next, the operation will be explained.
図の上側から入射した光は光吸収層2で吸収されて電子
−正孔対を生成し、p−−Afl I nAs増倍層6
からp” Al2 I nAs層5.p−−AuInA
s層4.キャリア加速層3を通して光吸収層2まで伸び
ているn−p接合の空乏領域の電界により、電子はn”
−AJlI nAs層7に向かって加速され、光吸収に
よる電流として検出することができる。ここで、各接合
での電界がトンネル電流が、大きくならない程度に小さ
く、かつ各接合で電子の蓄積が生じない程度に大きくし
、n −p接合での電界はなだれ破壊を生じる程度に大
きくすれば、なだれ破壊によりあらたに電子−正孔対を
生成して光電流を増倍する。The light incident from the upper side of the figure is absorbed by the light absorption layer 2 to generate electron-hole pairs, and the p--Afl I nAs multiplication layer 6
p'' Al2I nAs layer 5.p--AuInA
s layer 4. Due to the electric field in the depletion region of the n-p junction that extends through the carrier acceleration layer 3 to the light absorption layer 2, electrons are
-AJlI is accelerated toward the nAs layer 7 and can be detected as a current due to light absorption. Here, the electric field at each junction is made small enough so that the tunnel current does not increase and large enough so that electrons do not accumulate at each junction, and the electric field at the n-p junction is made large enough to cause avalanche breakdown. For example, new electron-hole pairs are generated by avalanche destruction, thereby multiplying the photocurrent.
すなわち、この構造では、n” −A11. I nA
s層7とキャリア加速層3との間のp−Al1 I n
As層をキャリア濃度分布を有する多層構造としてp−
AflInAs層全体にかかる電圧を減少しているほか
、p−−AβInAs増倍層6の層厚を最適に設計する
ことにより、なだれ増倍動作を可能としている。この結
果、〜50V程度での動作が可能であり、なだれ増倍領
域が小さくなるため、なだれ増倍の立上り時間が小さく
なって高速動作が可能である。また、Al2 I nA
s層群(p−A11I nAs層4.p”−AnI n
As層5、p−−AnInAs増倍層5.n” −AI
lI nAs層7)とp−InGaAsnGaAs光吸
収層導入したキャリア加速層3により、ヘテロ界面での
光生成キャリアの蓄積を防止でき、−層の高速動作が可
能になっている。That is, in this structure, n” −A11. I nA
p-Al1 I n between the s layer 7 and the carrier acceleration layer 3
The As layer has a multilayer structure with a carrier concentration distribution, and p-
In addition to reducing the voltage applied to the entire AflInAs layer, avalanche multiplication operation is made possible by optimally designing the layer thickness of the p--AβInAs multiplication layer 6. As a result, operation at about 50 V is possible, and since the avalanche multiplication region becomes small, the rise time of avalanche multiplication becomes short and high-speed operation is possible. Also, Al2I nA
s layer group (p-A11I nAs layer 4.p''-AnI n
As layer 5, p--AnInAs multiplication layer 5. n”-AI
The carrier acceleration layer 3 into which the lI nAs layer 7) and the p-InGaAsnGaAs light absorption layer are introduced prevents the accumulation of photogenerated carriers at the hetero interface, and enables high-speed operation of the - layer.
なお、上記実施例ではp−n接合がメサ構造のものにつ
いて示したが、プレーナ構造のものでも同様である。In the above embodiments, the pn junction has a mesa structure, but the same applies to a planar structure.
また、上記実施例では光吸収層2とAl2InAs層群
との間にAll I nGaAsからなるキャリア加速
層3を有する構造ものもを示したが、InGaAsP層
を用いたものでもよい。Further, in the above embodiment, a structure having a carrier acceleration layer 3 made of AllInGaAs between the light absorption layer 2 and the Al2InAs layer group was shown, but a structure using an InGaAsP layer may also be used.
〔発明の効果)
この発明は以上説明したとおり、p−−AJZInAs
増倍層の層厚を0.17〜0.25μmとし、そのキャ
リア濃度を2xlO”cm−3以下とするとともに、光
吸収層とp−−Al2I nAs層間にこれらの中間の
組成のキャリア加速層を形成したので、なだれ増倍が生
じる電圧が単一のキャリア濃度の増倍層の場合よりも低
下し、なだれ増倍立上り時間が減少するほか、ヘテロ界
面でのキャリアの蓄積が防止され、高速動作が可能にな
るほか、低い電圧での動作も可能になるという効果があ
る。[Effect of the invention] As explained above, this invention
The layer thickness of the multiplication layer is 0.17 to 0.25 μm, the carrier concentration is 2xlO"cm-3 or less, and a carrier acceleration layer with a composition intermediate between these layers is provided between the light absorption layer and the p--Al2I nAs layer. As a result, the voltage at which avalanche multiplication occurs is lower than in the case of a multiplication layer with a single carrier concentration, which reduces the avalanche multiplication rise time, and prevents carrier accumulation at the heterointerface, resulting in high-speed In addition to enabling operation, it also has the effect of enabling operation at low voltage.
′i41図はこの発明の光検出素子の一実施例を示す断
面図、第2図はなだれ増倍を実現する高電界部の幅WM
と電界Eの関係を示す図、第3図は従来の光検出素子を
示す断面図である。
図において、1はp” −InP基板、2はp−I n
GaAs光吸収層、3はp−Al1. I nGaAs
キャリア加速層、4はp−−Al2 I nAs層、5
はp”−AIlI nAs層、6はI)−−AJZIn
As増倍層、7はn” −An I nAs層、8はp
側電極、9はn側電極である。
なお、各図中の同一符号は同一または相当部分を示す。Figure 'i41 is a cross-sectional view showing one embodiment of the photodetector element of the present invention, and Figure 2 is the width WM of the high electric field part that realizes avalanche multiplication.
FIG. 3 is a cross-sectional view showing a conventional photodetecting element. In the figure, 1 is a p''-InP substrate, 2 is a p-InP substrate, and 2 is a p-InP substrate.
GaAs light absorption layer, 3 is p-Al1. InGaAs
Carrier acceleration layer, 4 p--Al2InAs layer, 5
is p''-AIlI nAs layer, 6 is I)--AJZIn
As multiplication layer, 7 is n”-An I nAs layer, 8 is p
The side electrode 9 is an n-side electrode. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
−AlInAs層、p^+−AlInAs層、p^−−
AlInAs増倍層、n^+−AlInAs層を有する
フォトダイオードにおいて、前記p^−−AlInAs
増倍層の層厚を0.17〜0.25μmとし、そのキャ
リア濃度を2×10^1^5cm^−^3以下とすると
ともに、前記光吸収層と前記p^−−AlInAs層間
にこれらの中間の組成のキャリア加速層を形成したこと
を特徴とする光検出素子。p^+-A light absorption layer that absorbs light on the InP substrate, p^-
-AlInAs layer, p^+ -AlInAs layer, p^--
In the photodiode having an AlInAs multiplication layer and an n^+-AlInAs layer, the p^--AlInAs
The layer thickness of the multiplication layer is 0.17 to 0.25 μm, the carrier concentration is 2×10^1^5 cm^-^3 or less, and these layers are provided between the light absorption layer and the p^--AlInAs layer. A photodetecting element characterized by forming a carrier acceleration layer having a composition between .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141791A JPH036871A (en) | 1989-06-02 | 1989-06-02 | Photodetecting element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1141791A JPH036871A (en) | 1989-06-02 | 1989-06-02 | Photodetecting element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH036871A true JPH036871A (en) | 1991-01-14 |
Family
ID=15300235
Family Applications (1)
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JP1141791A Pending JPH036871A (en) | 1989-06-02 | 1989-06-02 | Photodetecting element |
Country Status (1)
Country | Link |
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JP (1) | JPH036871A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103081129A (en) * | 2010-09-02 | 2013-05-01 | Ntt电子股份有限公司 | Avalanche photodiode |
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JPS59151475A (en) * | 1983-02-17 | 1984-08-29 | Kokusai Denshin Denwa Co Ltd <Kdd> | Hetero-structure avalanche-photodiode with buffer layer |
JPS59161082A (en) * | 1983-03-03 | 1984-09-11 | Fujitsu Ltd | Semiconductor light-receptor |
JPS6226871A (en) * | 1985-07-27 | 1987-02-04 | Mitsubishi Electric Corp | Semiconductor element |
JPS63281480A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Semiconductor photodetector and manufacture thereof |
-
1989
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---|---|---|---|---|
JPS59151475A (en) * | 1983-02-17 | 1984-08-29 | Kokusai Denshin Denwa Co Ltd <Kdd> | Hetero-structure avalanche-photodiode with buffer layer |
JPS59161082A (en) * | 1983-03-03 | 1984-09-11 | Fujitsu Ltd | Semiconductor light-receptor |
JPS6226871A (en) * | 1985-07-27 | 1987-02-04 | Mitsubishi Electric Corp | Semiconductor element |
JPS63281480A (en) * | 1987-05-13 | 1988-11-17 | Hitachi Ltd | Semiconductor photodetector and manufacture thereof |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103081129A (en) * | 2010-09-02 | 2013-05-01 | Ntt电子股份有限公司 | Avalanche photodiode |
CN103081129B (en) * | 2010-09-02 | 2015-07-22 | Ntt电子股份有限公司 | Avalanche photodiode |
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