JPH02228080A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPH02228080A
JPH02228080A JP1048334A JP4833489A JPH02228080A JP H02228080 A JPH02228080 A JP H02228080A JP 1048334 A JP1048334 A JP 1048334A JP 4833489 A JP4833489 A JP 4833489A JP H02228080 A JPH02228080 A JP H02228080A
Authority
JP
Japan
Prior art keywords
layer
window
conductivity type
window layer
light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1048334A
Other languages
Japanese (ja)
Inventor
Shigeyuki Misu
三須 重幸
Nozomi Matsuo
松尾 望
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP1048334A priority Critical patent/JPH02228080A/en
Publication of JPH02228080A publication Critical patent/JPH02228080A/en
Pending legal-status Critical Current

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  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To restrain the generation of current at a low level by doping the interfaces facing an optical absorption layer of a buffer layer and a window layer with impurities. CONSTITUTION:The interfaces facing an optical absorption layer 4 of a buffer layer 2a and a window layer 5a are doped with impurities such as Se, S, and Si. Namely, the carriers compensate for defects by doping the interfaces with impurities. As a result, a depletion layer ranges from the window layer 5a to the buffer layer 2a by applying a bias voltage, and the generation of current caused by defects or traps can be prevented even over the range including the both side interfaces of the optical absorption layer 4.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は構造改良された半導体受光素子に関す〔従来の
技術〕 I nGaAsを光吸収層とする半導体受光素子は、波
長1.7μ近(まで高い受光感度があるため、1−帯波
長光通信に広く用いられている。その構造は、例えば第
2図に示すように、n”−1nP基板(1)上に、n−
−1nPバッファ層(2)、n−I nGaAs光吸収
層(4)およびn−−1nP窓層(5)が順次積層され
、次に、n−−1nP窓層(5)表面から選択的にZn
を拡散して、p” −Zn導電層(6)が形成されてい
る。n−〜InP窓層(5)の表面には、SiNx表面
保護膜(7)がp” −Zn導電層(6)の周端部と非
拡散部に形成されている。(8)は受光領域のp” −
Zn導電層(6)の端部とSiNx表面保護膜(7)上
に形成されたp電極、(9)はno−InP基板(])
裏面に形成されたn電極である。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor light-receiving device with an improved structure [Prior Art] A semiconductor light-receiving device having a light absorption layer of InGaAs has a wavelength of around 1.7μ ( It is widely used in 1-band wavelength optical communications because of its high light-receiving sensitivity up to
-1nP buffer layer (2), n-I nGaAs light absorption layer (4) and n-1nP window layer (5) are sequentially laminated, and then selectively from the surface of n-1nP window layer (5). Zn
A p''-Zn conductive layer (6) is formed by diffusing the p''-Zn conductive layer (6). On the surface of the n-~InP window layer (5), a SiNx surface protection film (7) is formed by diffusing the p''-Zn conductive layer (6). ) and the non-diffusion part. (8) is p” − of the light receiving area
P-electrode formed on the edge of the Zn conductive layer (6) and the SiNx surface protective film (7), (9) is the no-InP substrate (])
This is an n-electrode formed on the back surface.

上記構造では、E nGaAs P系の光吸収層上に光
吸収層よりも禁止帯中が広く、光を透過する窓層が設け
られ、pn接合部が窓層に形成されている。従って、低
バイアスで光吸収層を完全に空乏化するために、窓層の
キャリア濃度も光吸収層なみに高純度化している。各層
は高純度のエピタキシャル層であること、rnGaAs
層上に直接InP層を成長できること、および、拡散に
よりpn接合を形成するために必要な膜厚の均一性に優
れている事などから、気相成長法により上記構造の半導
体受光素子が製作されている6表面保護膜は、窓層表面
のpn接合部の保護、表面酸化による暗電流増加を防ぐ
ため、酸化膜のかわりにSiNxを用いている。
In the above structure, a window layer that has a wider forbidden band than the light absorption layer and transmits light is provided on the E nGaAs P-based light absorption layer, and a pn junction is formed in the window layer. Therefore, in order to completely deplete the light absorption layer with a low bias, the carrier concentration of the window layer is also made as highly purified as that of the light absorption layer. Each layer is a high purity epitaxial layer, rnGaAs
The semiconductor light-receiving device with the above structure has been fabricated using the vapor phase growth method because the InP layer can be grown directly on the InP layer and the uniformity of the film thickness required to form a pn junction by diffusion is excellent. The surface protective film 6 uses SiNx instead of the oxide film in order to protect the pn junction on the surface of the window layer and prevent an increase in dark current due to surface oxidation.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、上記構造の半導体受光素°子には次のよ
うな問題点がある。すなわち、 イ)ダブルへテロ構造界面の欠陥は、発光素子のように
高いキャリア濃度(I XIO”cm−’以上)では補
償されているが、上記半導体受光素子のように高純度エ
ピタキシャル層を成長させる場合には、素子特性に大き
な影響を及ぼす、特に気相成長法では、界面に変成層が
できやすいため、それがトラップとなって暗電流を増大
させる。
However, the semiconductor light receiving element having the above structure has the following problems. That is, a) Defects at the double heterostructure interface are compensated for at high carrier concentrations (more than I In particular, in vapor phase growth, metamorphic layers are likely to form at interfaces, which act as traps and increase dark current.

口)高純度エピタキシャル層上に表面保護膜として誘電
体膜を積層すると、誘電体膜自体の持つ電荷(SiNx
ならば負)により、誘電体膜直下に空乏層が生じてチャ
ンネル化したり、あるいは、誘電体膜と半導体界面に界
面準位が生じたりして、表面リーク電流が大きくなる。
) When a dielectric film is laminated as a surface protection film on a high-purity epitaxial layer, the charge of the dielectric film itself (SiNx
(if negative), a depletion layer is generated directly under the dielectric film and becomes a channel, or an interface state is generated at the interface between the dielectric film and the semiconductor, resulting in an increase in surface leakage current.

本発明は以上のような点にかんがみてなされたもので、
その目的とするところは、暗電流の小さい半導体受光素
子を提供することにある。
The present invention has been made in view of the above points.
The purpose is to provide a semiconductor light-receiving element with low dark current.

〔課題を解決するための手段と作用〕[Means and actions to solve the problem]

上記目的を達成するための本発明は次の通りである。す
なわち、本発明は第1導電型の半導体基板上に、第1導
電型のバッファ層、光吸収層および窓層が順次積層され
、該窓層の表面より層内部に向けて第2導電型領域が選
択的に形成され、窓層表面の第1導電型碩域と第2導電
型領域の境界領域上に第1導電型領域と第2導°電型領
域にまたがって表面保護膜が形成されている半導体受光
素子において、パンフ1層および窓層の光吸収層に面す
る界面にはSe、S、Stなどの不純物がドーピングさ
れていることを第1発明とし、窓層の光入射側の表面に
は不純物がドーピングされていることを第2発明とする
ものである。
The present invention for achieving the above object is as follows. That is, in the present invention, a buffer layer, a light absorption layer, and a window layer of a first conductivity type are sequentially laminated on a semiconductor substrate of a first conductivity type, and a region of a second conductivity type is formed from the surface of the window layer toward the inside of the layer. is selectively formed, and a surface protective film is formed on the boundary region of the first conductivity type region and the second conductivity type region on the surface of the window layer, spanning the first conductivity type region and the second conductivity type region. In the semiconductor light receiving device, the first invention provides that impurities such as Se, S, and St are doped at the interfaces of the first pamphlet layer and the window layer facing the light absorption layer; The second invention is that the surface is doped with impurities.

気相成長法によりn−−1nPバッファ層(2)上にn
−−1nCaAs光吸収層を成長させる場合、加熱によ
りn−−1nPバッファ層のPが抜けてバッファ層の光
吸収層側界面に欠陥による変成層が生じる。同様にn−
−InGaAs光吸収層(4)上に11−−111 p
g層(5ンを成長させると、n−InGaAs光吸収層
(4)のAsが抜けて、光吸収層の窓層(5)側界面に
欠陥が生じる6本発明では、光吸収層(4)に面するバ
ッファ層(2)および窓層(5)の界面に不純物をドー
ピングして上記欠陥をキャリアで補償している。その結
果、バイアス電圧の印加により、空乏層が窓層(5)か
らバッファFJ (2)到り、光吸収層(4)の両側界
面を含む範囲にわたっても、欠陥やトラップによる発生
電流を防ぐことができる。また、窓層(5)の光入射側
の表面に不純物をドーピングすると、誘電体からなる表
面保護膜(7)の電荷により窓層(5)表面にチャンネ
ルが形成されることを防ぐことができ、表面リークを流
を抑えることができる。上記のバッファ層(2)および
窓N(5)の界面に形成される不純物をドーピングした
層は、キャリア濃度が5.OXl0ISe11−’ 〜
1.OXIO”CI−’の範囲であり、厚さが0.1〜
0.3μであることが望ましい、その理由は、キャリア
濃度が1.0X10”CI−’以上、あるいは厚さが0
.3−以上になると、トンネル現象による暗電流が増加
する。また、キャリア濃度が5X10”am−’以下、
あるいは厚さが0.1−以下になると、トラップ欠陥を
補償できないからである。
n on the n--1nP buffer layer (2) by vapor phase epitaxy.
When growing a --1nCaAs light absorption layer, heating causes P in the n−1nP buffer layer to escape, creating a metamorphosed layer due to defects at the interface of the buffer layer on the light absorption layer side. Similarly n-
-11--111 p on the InGaAs light absorption layer (4)
When the n-InGaAs light-absorbing layer (4) is grown, As in the n-InGaAs light-absorbing layer (4) is grown, causing defects at the interface of the light-absorbing layer on the window layer (5) side. ) The interface between the buffer layer (2) and the window layer (5) facing the buffer layer (2) and the window layer (5) is doped with impurities to compensate for the above defects with carriers.As a result, by applying a bias voltage, the depletion layer closes to the window layer (5). From the buffer FJ (2) to the buffer FJ (2), it is possible to prevent current generation due to defects and traps even over a range including both interfaces of the light absorption layer (4). Doping with impurities can prevent the formation of channels on the surface of the window layer (5) due to the charges of the surface protection film (7) made of a dielectric material, and can suppress surface leakage. The impurity-doped layer formed at the interface between layer (2) and window N(5) has a carrier concentration of 5.OXl0ISe11-' ~
1. OXIO"CI-' range, thickness 0.1~
It is desirable that the thickness is 0.3 μ because the carrier concentration is 1.0×10” CI-’ or more or the thickness is 0
.. When it is 3- or more, dark current due to tunneling phenomenon increases. In addition, the carrier concentration is 5×10”am-’ or less,
Alternatively, if the thickness is less than 0.1, trap defects cannot be compensated for.

〔実施例〕〔Example〕

以下、図面に示した実施例に基づいて本発明を説明する
The present invention will be described below based on embodiments shown in the drawings.

第1図は本発明にかかる半導体受光素子の一実施例の要
部断面図であり、n”−1nP基板(1)上に気相成長
法によりn−−1nPバッファ層(2a)、n−1nP
ド一ピング層(2b)、n−−1nGaAS光吸収N(
4)、n−1nPド一ピング層(5b)、n−InP窓
層(5a)、n−1nPド一ピング層(5c)を順次成
長させる。バッファ1it(2a)および窓層(5a)
は不純物濃度が1.0X10”cm−”、厚さ2.0−
1n−1nPド一ピング層(2b)、(5b)、(5C
)は不純物濃度が7.0X10”CI−”、厚さ0.2
n、光吸収層(4)は不純物濃度が5.0X10”el
l−’、厚さが265−である、窓層(5a)の表面に
はZn、Cd、Mgの熱拡散、あるいは、Be、Mgの
イオン打込みによりp型の導電層(6)を選択的に形成
し、窓層(5a)内にpn接合部を形成し、ドーピング
層(5C)上には、SiNxからなる誘電体の表面保!
!膜(7)を形成する。(8)はT i / P t 
/ A uのn電極、(9)はAuGeNi/Auのn
t極、00)は受光径100−φの受光部を被うAR膜
である。本実施例の半導体受光素子に5■のバイアス電
圧を印加すると、空乏層端はバッファ層(2a)に達し
、光吸収層(4)は完全に空乏化した。その状態で光を
入射すると、受光面の反射および光吸収層(4)とドー
ピング層(2b)、(5b)との界面による反射および
キャリアの再結合による低下はあるものの、90%以上
の量子効率が得られた。また、5■のバイアス電圧下に
おいて、暗電流は1nA以下、周波数応答はIGHz以
上という結果をえた。因に、本実施例におけるドーピン
グ層のない場合には、量子効率は70%であり、暗電流
は10nA以上に、周波数応答は500MHzであった
FIG. 1 is a sectional view of a main part of an embodiment of a semiconductor light-receiving device according to the present invention, in which an n--1nP buffer layer (2a) and an n- 1nP
Doping layer (2b), n--1nGaAS optical absorption N(
4) Sequentially grow an n-1nP doped layer (5b), an n-InP window layer (5a), and an n-1nP doped layer (5c). Buffer 1it (2a) and window layer (5a)
The impurity concentration is 1.0X10"cm-" and the thickness is 2.0-
1n-1nP doping layer (2b), (5b), (5C
) has an impurity concentration of 7.0X10"CI-" and a thickness of 0.2
n, the light absorption layer (4) has an impurity concentration of 5.0×10”el
A p-type conductive layer (6) is selectively formed on the surface of the window layer (5a) with a thickness of 265 mm by thermal diffusion of Zn, Cd, and Mg, or by ion implantation of Be and Mg. A pn junction is formed in the window layer (5a), and a dielectric layer made of SiNx is formed on the doping layer (5C).
! A film (7) is formed. (8) is T i / P t
/ Au n electrode, (9) is AuGeNi/Au n electrode
The t-pole (00) is an AR film covering a light-receiving portion with a light-receiving diameter of 100-φ. When a bias voltage of 5cm was applied to the semiconductor photodetector of this example, the edge of the depletion layer reached the buffer layer (2a), and the light absorption layer (4) was completely depleted. When light is incident in this state, more than 90% of quantum Efficiency was achieved. In addition, under a bias voltage of 5■, the dark current was less than 1 nA, and the frequency response was more than IGHz. Incidentally, in the case without the doped layer in this example, the quantum efficiency was 70%, the dark current was 10 nA or more, and the frequency response was 500 MHz.

なお、窓層およびバッファ層は光吸収層に格子整合し、
かつ禁制帯巾が光吸収層より広い材料ならばよく、上記
実施例におけるI nGaAs光吸収層に対しては、I
nP以外にI nGaAs Pを用いてもよい、また、
本発明は、I nGaAs P系以外のGaSb系など
の化合物半導体にも適用することができる。さらに、上
記実施例はプレーナー型PINフォトダイオードについ
てであったが、本発明はメサ型でも実施可能であり、ま
た、アバランシェフォトダイオードでも実施可能である
。光吸収層はバルク半導体に限定されることなく、量子
井戸構造でも実施可能であることはいうまでもない。
Note that the window layer and buffer layer are lattice matched to the light absorption layer,
It is sufficient if the material has a wider forbidden band width than the light absorption layer, and for the InGaAs light absorption layer in the above embodiment, I
InGaAsP may be used other than nP, and
The present invention can also be applied to compound semiconductors other than InGaAsP-based, such as GaSb-based. Furthermore, although the above embodiments are about planar type PIN photodiodes, the present invention can also be implemented with mesa type photodiodes, and can also be implemented with avalanche photodiodes. It goes without saying that the light absorption layer is not limited to a bulk semiconductor, and can also have a quantum well structure.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、バッファ層および
窓層の光吸収層に面する界面、および窓層の光入射側の
表面には不純物がドーピングされているため、発生′r
!12itおよび表面リーク電流を低く抑えることがで
き、暗電流の小さな良好な半導体受光素子を得ることが
できるという優れた効果がある。
As explained above, according to the present invention, impurities are doped at the interfaces of the buffer layer and the window layer facing the light absorption layer, and at the surface of the window layer on the light incident side.
! 12it and surface leakage current can be suppressed to a low level, and a good semiconductor light-receiving element with small dark current can be obtained, which is an excellent effect.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明にかかる半導体受光素子の一実施例の要
部断面図、第2図は一従来例の要部断面図である。 1・・・基板、 2,2a・・・バッファ層、 2b、
 5b5c・・・ドーピング層、  4・・・光吸収層
、  5.5a・・・窓層、 6・・・導電層、 7・
・・表面保護膜、  8・・・n電極、 9・・・n電
極、 10・・・AR膜。 第2図
FIG. 1 is a sectional view of a main part of an embodiment of a semiconductor light receiving element according to the present invention, and FIG. 2 is a sectional view of a main part of a conventional example. 1...Substrate, 2,2a...Buffer layer, 2b,
5b5c... Doping layer, 4... Light absorption layer, 5.5a... Window layer, 6... Conductive layer, 7.
...Surface protective film, 8...n electrode, 9...n electrode, 10...AR film. Figure 2

Claims (2)

【特許請求の範囲】[Claims] (1)第1導電型の半導体基板上に、第1導電型のバッ
ファ層、光吸収層および窓層が順次積層され、該窓層の
表面より層内部に向けて第2導電型領域が選択的に形成
され、窓層表面の第1導電型領域と第2導電型領域の境
界領域上に第1導電型領域と第2導電型領域にまたがっ
て表面保護膜が形成されている半導体受光素子において
、バッファ層および窓層の光吸収層に面する界面には、
不純物がドーピングされていることを特徴とする半導体
受光素子。
(1) A first conductivity type buffer layer, a light absorption layer, and a window layer are sequentially laminated on a first conductivity type semiconductor substrate, and a second conductivity type region is selected from the surface of the window layer toward the inside of the layer. A semiconductor light-receiving element in which a surface protection film is formed on the boundary region between the first conductivity type region and the second conductivity type region on the surface of the window layer and spanning the first conductivity type region and the second conductivity type region. In the interface of the buffer layer and the window layer facing the light absorption layer,
A semiconductor light-receiving element characterized by being doped with impurities.
(2)窓層の光入射側の表面には、不純物がドーピング
されていることを特徴とする請求項1記載の半導体受光
素子。
(2) The semiconductor light-receiving device according to claim 1, wherein the surface of the window layer on the light incident side is doped with an impurity.
JP1048334A 1989-02-28 1989-02-28 Semiconductor photodetector Pending JPH02228080A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1048334A JPH02228080A (en) 1989-02-28 1989-02-28 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1048334A JPH02228080A (en) 1989-02-28 1989-02-28 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPH02228080A true JPH02228080A (en) 1990-09-11

Family

ID=12800514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1048334A Pending JPH02228080A (en) 1989-02-28 1989-02-28 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPH02228080A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368750B2 (en) 2002-09-20 2008-05-06 Fujitsu Quantum Devices Limited Semiconductor light-receiving device
WO2016139970A1 (en) * 2015-03-05 2016-09-09 住友電気工業株式会社 Semiconductor laminate and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391685A (en) * 1976-12-31 1978-08-11 Philips Nv Semiconductor
JPS59161082A (en) * 1983-03-03 1984-09-11 Fujitsu Ltd Semiconductor light-receptor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5391685A (en) * 1976-12-31 1978-08-11 Philips Nv Semiconductor
JPS59161082A (en) * 1983-03-03 1984-09-11 Fujitsu Ltd Semiconductor light-receptor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7368750B2 (en) 2002-09-20 2008-05-06 Fujitsu Quantum Devices Limited Semiconductor light-receiving device
WO2016139970A1 (en) * 2015-03-05 2016-09-09 住友電気工業株式会社 Semiconductor laminate and semiconductor device

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