JPH0215680A - Semiconductor photodetecting device - Google Patents

Semiconductor photodetecting device

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Publication number
JPH0215680A
JPH0215680A JP63165006A JP16500688A JPH0215680A JP H0215680 A JPH0215680 A JP H0215680A JP 63165006 A JP63165006 A JP 63165006A JP 16500688 A JP16500688 A JP 16500688A JP H0215680 A JPH0215680 A JP H0215680A
Authority
JP
Japan
Prior art keywords
layer
type
mesa
type inp
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63165006A
Other languages
Japanese (ja)
Other versions
JP2633912B2 (en
Inventor
Hiroshi Matsuda
広志 松田
Kazuhiro Ito
和弘 伊藤
Tadashi Fukuzawa
董 福沢
Ichiro Fujiwara
一郎 藤原
Kazuyuki Nagatsuma
一之 長妻
Takao Miyazaki
隆雄 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP63165006A priority Critical patent/JP2633912B2/en
Publication of JPH0215680A publication Critical patent/JPH0215680A/en
Application granted granted Critical
Publication of JP2633912B2 publication Critical patent/JP2633912B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To decrease a mesa-type photodetecting element in a dark current and to improve it in reliability by a method wherein the side face of a mesa is made semi-insulated by the introduction of an inert impurity. CONSTITUTION:The following are successively grown on an n-type InP substrate 31 through an MOCVD method: an n-type InP buffer layer 32; an n-type InGaAs light absorbing layer 33; an n-type InGaAsP barrier alleviating layer 34; an n-type InP electrical field alleviating layer 35; and an n-type InP layer. After that, the uppermost InP layer is made to serve as an n-type InP multiplying layer 36 and a p-type InP layer 37 though the diffusion of Zn 2mum in depth to form a p-n junction 38. After a protecting film 39 has been formed on a side face of a mesa, oxygen is introduced through an ion implantation for the formation of a semi-insulating region 40. Next, the substrate 31 is annealed at a temperature of 700 deg.C, and then a p-electrode 41 and an n-electrode 42 are built to form an APD.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体受光装置に係り、特にメサ型構造のアバ
ランシェ・ホトダイオード(以下APDと略記する)お
よびpinホトダイオードの構造とその製造方法に係る
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor light receiving device, and particularly to the structure of an avalanche photodiode (hereinafter abbreviated as APD) having a mesa structure and a pin photodiode, and a manufacturing method thereof.

〔従来の技術〕[Conventional technology]

以下、InP系の受光素子を例にして説明する。 In the following, an InP-based light receiving element will be explained as an example.

APDにおいては、主接合端部のカバーが重要な課題で
ある。プレーナ型APDでは、ガードリング接合を形成
して、主接合湾曲部をカバーしている。しかし、ガード
リング接合の深さ制御は非常に難しい。すなわち、ガー
ドリング接合深さと主接合深さの相対位置および光吸収
層との距離の微妙な差異がAPD特性の上では大きな差
となるためであり、エピタキシャル層の厚みバラツキを
考慮すると、制御は非常に困難である。この点、メサ型
構造のAPD主接合湾曲部がないため、ガードリング接
合は不要となる利点を持つ。
In APD, covering the main joint end is an important issue. In a planar APD, a guard ring junction is formed to cover the main junction curved portion. However, controlling the depth of the guard ring junction is extremely difficult. In other words, subtle differences in the relative position of the guard ring junction depth and the main junction depth and the distance to the light absorption layer make a big difference in APD characteristics, and considering the thickness variation of the epitaxial layer, control is difficult. Very difficult. In this respect, since there is no curved part of the APD main junction of the mesa type structure, there is an advantage that no guard ring junction is required.

例えば、エレクトロニクスレターズ (ELECTRONIC3LETTER5)第29,9
月、1983年第19巻第20号第818〜820頁の
従来構造を第2図に示す。同図において、11はp型I
nP基板、12はp型InP層、13はn型InP層、
14はn型I n G a A s P層、15はn型
I n G a A s層(光吸収層)、16はp電極
For example, Electronics Letters (ELECTRONIC3LETTER5) No. 29, 9
The conventional structure is shown in FIG. 2. In the same figure, 11 is p-type I
nP substrate, 12 is a p-type InP layer, 13 is an n-type InP layer,
14 is an n-type InGaAs P layer, 15 is an n-type InGaAs layer (light absorption layer), and 16 is a p electrode.

17はn電極であり、18はpn接合である。しかし、
メサ型構造は同図からもわかるように。
17 is an n electrode, and 18 is a pn junction. but,
As you can see from the figure, the mesa-shaped structure.

pn接合18および光吸収層15の端部がメサ側面に露
出してしまい、その保護が難しく5表面リーク電流の低
減および信頼性の面で劣るという欠点を持つ。
The ends of the pn junction 18 and the light absorption layer 15 are exposed on the side surface of the mesa, making it difficult to protect them, resulting in a disadvantage in terms of reduction in surface leakage current and reliability.

また、メサ型構造はpinホトダイオード(以下pin
PDと略記)でも検討されている0例えば第3図に示す
従来例はエレクトロニクスレターズ(HLECTRON
IC5LETTf!R3)第9,5月、1985年第2
1巻、第10号、第441〜442頁の構造である。同
図において、21はn型InP基板、22はn型InP
層、23はn型I n G a A s層(光吸収層)
、24はp型I n G a A s層、25はp型I
nP層、26はp電極であり、27はpn接合である0
本例でもpn接合27および光吸収層23の端部はメサ
側面に露出しており、第2図の従来例と同様の欠点を有
している。
In addition, the mesa-type structure is a pin photodiode (hereinafter referred to as a pin photodiode).
For example, the conventional example shown in Figure 3 is Electronics Letters (HLECTRON).
IC5LETTf! R3) 9th, May, 2nd 1985
This is the structure of Volume 1, No. 10, pages 441-442. In the same figure, 21 is an n-type InP substrate, 22 is an n-type InP substrate, and 22 is an n-type InP substrate.
layer, 23 is an n-type InGaAs layer (light absorption layer)
, 24 is a p-type I n Ga As layer, 25 is a p-type I
nP layer, 26 is p electrode, 27 is pn junction 0
In this example as well, the ends of the pn junction 27 and the light absorption layer 23 are exposed on the side surface of the mesa, which has the same drawback as the conventional example shown in FIG.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

メサ型構造受光素子における上記従来技術は、メサ側面
に露出したpn接合端および光吸収層端の保護に関して
配慮がされておらず、表面リーク電流の低減および信頼
性の点で問題が残されていた。
The above-mentioned conventional technology for the mesa structure photodetector does not take into consideration the protection of the pn junction end and the light absorption layer end exposed on the side surface of the mesa, and problems remain in terms of surface leakage current reduction and reliability. Ta.

本発明の目的はメサ型構造における上記欠点を解消する
ことにある。
An object of the present invention is to eliminate the above-mentioned drawbacks of mesa-type structures.

尚、メサ側面にSiN膜を被着した例(例えば。Incidentally, an example in which a SiN film is deposited on the side surface of the mesa (for example).

昭和58年度電子通信学会半導体・材料部門全国大会予
稿314)もあるが、信頼性の点で不十分と考えられる
There is also a Proceedings of the 1981 IEICE Semiconductor and Materials Division National Conference 314), but it is considered insufficient in terms of reliability.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するための手段をAPDを例に第1図を
用いて説明する。第1図において、1はn型InP基板
、2はn型InGaAs光吸収層。
Means for achieving the above object will be explained using FIG. 1 using an APD as an example. In FIG. 1, 1 is an n-type InP substrate, and 2 is an n-type InGaAs light absorption layer.

3はn型InP増倍層、4はp型InP層で、5はpn
接合である。6は不活性不純物導入によって、上記1〜
5を半絶縁物化した領域、7は絶縁膜、8はp電極、9
はn電極である1本発明の目的は、メサ側面の保護を、
不活性不純物を導入して半絶縁物化した半導体領域6で
行なうことによって達成される。
3 is an n-type InP multiplication layer, 4 is a p-type InP layer, and 5 is a pn
It is a joining. 6 is achieved by introducing inert impurities into the above 1 to 6.
5 is a semi-insulating region, 7 is an insulating film, 8 is a p-electrode, 9
is an n-electrode.1 The purpose of the present invention is to protect the side surfaces of the mesa.
This is achieved by introducing inactive impurities into the semiconductor region 6 which has been made into a semi-insulator.

〔作用〕[Effect]

メサ側面を、不活性不純物を導入して半絶縁物化するこ
とにより、pn接合5および光吸収層2の端面が半導体
結晶端に露出しなくなることにより、表面リーク電流が
おさえられ、かつ信頼性が良いAPDを作製することが
できる。
By introducing inert impurities into the mesa side surfaces to make them semi-insulating, the end faces of the pn junction 5 and the light absorption layer 2 are no longer exposed to the semiconductor crystal ends, suppressing surface leakage current and improving reliability. A good APD can be produced.

本発明の作用は、上記のごとく、連続した結晶内部にp
n接合端と光吸収層端を閉じこめることにあり、メサ側
面に絶縁膜を被着する方法、メサ部を半絶縁性半導体結
晶で埋め込む方法等とは本質的に異なる。すなわち、メ
サ側面に絶縁膜を被着あるいは埋め込む方式においては
、メサ側面と被着物あるいは埋め込み層との界面は活き
ており、本発明以外の方法ではこの界面の汚染またた活
性不純物の導入が生じやすいためである。
The effect of the present invention is that, as described above, p
The purpose of this method is to confine the n-junction end and the light absorption layer end, and is essentially different from methods such as depositing an insulating film on the mesa side surfaces or burying the mesa portion with semi-insulating semiconductor crystal. In other words, in the method of depositing or embedding an insulating film on the mesa side surface, the interface between the mesa side surface and the deposit or buried layer is active, and methods other than the present invention cause contamination of this interface or introduction of active impurities. This is because it is easy.

〔実施例〕〔Example〕

実施例1 第4図を用いて説明する。n型InP基板31(Sドー
プt n = I X 101g(1m−8)上に、n
型InPバッファー層32(アンドープ、0.5pm)
、n型InGaAs光吸収層33(アンドープ、2μm
)、n型InGaAsP障壁緩和層34(アンドープ、
Q、2μm)m n型InP電界緩和層35(Siドー
プ、n=2X10”m″″81.2μm)、n型InP
層(アンドープ、2.6μm)をMOCVD法を用いて
連続成長した。アンドープ層のキャリア濃度は1〜5X
101Bam−8であった。この後、深さ2μmのZn
拡散によって、最上層のInP層をn型1nP増倍層3
6(アンドープ、0.6μm )とp型InP層37(
Zn拡散、2μm)とにし、pn接合38を形成した。
Example 1 This will be explained using FIG. 4. On an n-type InP substrate 31 (S-doped t n = I
Type InP buffer layer 32 (undoped, 0.5pm)
, n-type InGaAs light absorption layer 33 (undoped, 2 μm
), n-type InGaAsP barrier relaxation layer 34 (undoped,
Q, 2 μm) m n-type InP electric field relaxation layer 35 (Si doped, n=2X10"m""81.2 μm), n-type InP
A layer (undoped, 2.6 μm) was continuously grown using MOCVD. The carrier concentration of the undoped layer is 1 to 5X
It was 101Bam-8. After this, Zn at a depth of 2 μm
By diffusion, the topmost InP layer becomes an n-type 1nP multiplication layer 3.
6 (undoped, 0.6 μm) and p-type InP layer 37 (
A pn junction 38 was formed by Zn diffusion (2 μm).

メサ側面に保護膜39を形成した後、酸素をイオン打込
によって導入して半絶縁物領域40を形成した。700
℃、1分のアニールを行なった後、p電極41.n電極
42を形成してAPDとした。本素子の特性を測定した
ところ、逆方向降伏電圧VBは約80V、逆バイアス電
圧10Vにおける暗電流は1nA以下、0.9Vaにお
ける暗電流は約20nA、最大増倍率約40と良好な特
性を得た。また信頼性においても、0.9Vaでの逆バ
イアス通電テストにおいて、1000時間経過後も劣化
が見られなかった。
After forming a protective film 39 on the side surface of the mesa, oxygen was introduced by ion implantation to form a semi-insulating region 40. 700
℃ for 1 minute, the p electrode 41. An n-electrode 42 was formed to form an APD. When we measured the characteristics of this device, we found that the reverse breakdown voltage VB was approximately 80V, the dark current at a reverse bias voltage of 10V was less than 1nA, the dark current at 0.9Va was approximately 20nA, and the maximum multiplication factor was approximately 40. Ta. In terms of reliability, no deterioration was observed even after 1000 hours in a reverse bias current test at 0.9 Va.

実施例2 第5図を用いて説明する1本実施例はp電極41をパタ
ーン電極とし、n電極42を全面電極として表面光入射
型にした点を除き、実施例1と同じである。特性面でも
、実施例1とほぼ同等の性能が得られた。
Embodiment 2 This embodiment, which will be explained with reference to FIG. 5, is the same as Embodiment 1 except that the p-electrode 41 is used as a pattern electrode, and the n-electrode 42 is used as a surface-light-incident electrode. In terms of characteristics, almost the same performance as in Example 1 was obtained.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、メサ側面を不活性不純物の導入によっ
て半絶縁物化することにより、従来メサ型受光素子で問
題とされていた、暗電流の低減および信頼性の向上が得
られる。したがって、良好な特性の受光素子を再現性良
く得られることから、産業上多大な効果がある。
According to the present invention, by making the mesa side surface semi-insulating by introducing inert impurities, it is possible to reduce dark current and improve reliability, which have been problems in conventional mesa-type light receiving elements. Therefore, a light-receiving element with good characteristics can be obtained with good reproducibility, which has great industrial effects.

本発明はAPDを例にとって説明してきたが、例えばp
inホトダイオード等、pn接合を有するメサ型の受光
装置において共通して効果が発揮されることは明らかで
ある。また、材料においても、InP系を例に実施例を
説明したが1例えばGaAs系等においても材料に特定
されることな〈実施例と同様の効果が得られることも明
らかである。
Although the present invention has been explained using APD as an example, for example, p
It is clear that this effect is commonly exhibited in mesa-type light receiving devices having a pn junction, such as in-photodiodes. Further, regarding the material, although the embodiment has been described using an InP-based material as an example, it is clear that the same effects as in the embodiment can be obtained with, for example, a GaAs-based material, etc., regardless of the material.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の基本概念を示すAPDの縦断面図、第
2図は従来のAPDを示す縦断面図、第3図は従来のp
inPDを示す縦断面図、第4図はおよび第5図は本発
明の実施例を示す縦断面図である。尚、図面を兄やすく
するため、ハツチングは不活性不純物を注入して半絶縁
物化した領域のみとした。 1.31−n型InP基板、2,33−n型I nGa
As光吸収層、3.35−n型InP増倍層、4.37
−P型InP層、5.38−pn接合、6,42・・・
半絶縁物化した領域、7.39・・・絶縁膜。 壽1呂 茅ス図 茅夕図
Fig. 1 is a longitudinal sectional view of an APD showing the basic concept of the present invention, Fig. 2 is a longitudinal sectional view of a conventional APD, and Fig. 3 is a longitudinal sectional view of a conventional APD.
FIGS. 4 and 5 are vertical cross-sectional views showing an inPD, and FIG. 5 is a vertical cross-sectional view showing an embodiment of the present invention. In order to make the drawings more concise, the hatching is limited to regions that have been made semi-insulating by implanting inert impurities. 1.31-n-type InP substrate, 2,33-n-type InGa
As light absorption layer, 3.35-n-type InP multiplication layer, 4.37
-P-type InP layer, 5.38-pn junction, 6,42...
Semi-insulating region, 7.39...insulating film. 1st birthday

Claims (1)

【特許請求の範囲】 1、pn接合を有するメサ型半導体受光素子を含む半導
体受光装置において、メサ側面の少なくともpn接合端
を含む一部または全部の領域を、不活性不純物導入によ
つて絶縁物化または半絶縁物化したことを特徴とする半
導体受光装置。 2、プロトンまたは酸素のイオン打込を用いて請求項第
1項記載の半導体受光装置の不活性不純物導入層を形成
することを特徴とする半導体受光装置の製造方法。 3、メサ側面に絶縁物保護膜を形成した後、その絶縁物
保護膜を通してメサ側面に不活性不純物を導入すること
を特徴とする請求項第2項記載の半導体受光装置の製造
方法。
[Claims] 1. In a semiconductor light receiving device including a mesa type semiconductor light receiving element having a pn junction, a part or all of the region including at least the end of the pn junction on the side surface of the mesa is made into an insulator by introducing an inert impurity. Or a semiconductor light receiving device characterized by being made of a semi-insulating material. 2. A method for manufacturing a semiconductor light receiving device, comprising forming the inert impurity-introduced layer of the semiconductor light receiving device according to claim 1 using ion implantation of protons or oxygen. 3. The method of manufacturing a semiconductor light receiving device according to claim 2, wherein after forming an insulating protection film on the side surface of the mesa, an inert impurity is introduced into the side surface of the mesa through the insulating protection film.
JP63165006A 1988-07-04 1988-07-04 Semiconductor light receiving device Expired - Lifetime JP2633912B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63165006A JP2633912B2 (en) 1988-07-04 1988-07-04 Semiconductor light receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63165006A JP2633912B2 (en) 1988-07-04 1988-07-04 Semiconductor light receiving device

Publications (2)

Publication Number Publication Date
JPH0215680A true JPH0215680A (en) 1990-01-19
JP2633912B2 JP2633912B2 (en) 1997-07-23

Family

ID=15804051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63165006A Expired - Lifetime JP2633912B2 (en) 1988-07-04 1988-07-04 Semiconductor light receiving device

Country Status (1)

Country Link
JP (1) JP2633912B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232442A (en) * 1993-02-04 1994-08-19 Nec Corp Semiconductor photodetector
JPH09213988A (en) * 1995-02-02 1997-08-15 Sumitomo Electric Ind Ltd P-i-n type photodetector, photoelectric conversion circuit and photoelectric conversion module
RU2627146C1 (en) * 2016-10-04 2017-08-03 Акционерное общество "НПО "Орион" Mesastructural photodiode based on heteroepitaxial structure of ingaas / alinas / inp

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232442A (en) * 1993-02-04 1994-08-19 Nec Corp Semiconductor photodetector
JPH09213988A (en) * 1995-02-02 1997-08-15 Sumitomo Electric Ind Ltd P-i-n type photodetector, photoelectric conversion circuit and photoelectric conversion module
RU2627146C1 (en) * 2016-10-04 2017-08-03 Акционерное общество "НПО "Орион" Mesastructural photodiode based on heteroepitaxial structure of ingaas / alinas / inp

Also Published As

Publication number Publication date
JP2633912B2 (en) 1997-07-23

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