JP2711055B2 - Semiconductor photodetector and method of manufacturing the same - Google Patents

Semiconductor photodetector and method of manufacturing the same

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Publication number
JP2711055B2
JP2711055B2 JP4289950A JP28995092A JP2711055B2 JP 2711055 B2 JP2711055 B2 JP 2711055B2 JP 4289950 A JP4289950 A JP 4289950A JP 28995092 A JP28995092 A JP 28995092A JP 2711055 B2 JP2711055 B2 JP 2711055B2
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JP
Japan
Prior art keywords
ridge
semiconductor
conductive layer
type
layer
Prior art date
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JP4289950A
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Japanese (ja)
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JPH06140658A (en
Inventor
和利 加藤
進 秦
信一 松本
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Nippon Telegraph and Telephone Corp
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Nippon Telegraph and Telephone Corp
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Priority to JP4289950A priority Critical patent/JP2711055B2/en
Publication of JPH06140658A publication Critical patent/JPH06140658A/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、静電容量と寄生抵抗と
を同時に低減できる構造の、高速応答可能な半導体光検
出器およびその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor photodetector having a structure capable of simultaneously reducing capacitance and parasitic resistance and capable of high-speed response, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来の一般的な半導体光検出器は、信号
光波長が1.55μmの場合を例にとると、図4に示す
ように低キャリア濃度の光吸収層303(図4の場合は
ノンドープInGaAs)の上下に、p型導電層30
4、n型導電層302をそれぞれ配置して形成している
(榊原勝利他、「直列抵抗を低減した高速GaInAs
/InP PINフォトダイオード」1991年春季応
用物理学会学術講演会予稿集、953頁、28p−F−
1)。なお、307はn電極、308はp電極である。
上記半導体光検出器においては、p型導電層304とn
型導電層302との間に逆バイアス電圧を印加して、ノ
ンドープの光吸収層303内に空乏層を形成し、上記空
乏層にかかる高電界を利用して、半導体光検出器上面ま
たは裏面より光吸収層に入射した信号光を光電変換する
ものである。
2. Description of the Related Art A conventional general semiconductor photodetector has a low carrier concentration light absorbing layer 303 (FIG. 4) as shown in FIG. Are p-type conductive layers 30 above and below non-doped InGaAs).
4. An n-type conductive layer 302 is formed by arranging each of the layers (Satoshi Sakakibara et al., "High-speed GaInAs with reduced series resistance"
/ InP PIN photodiode ”Proceedings of the 1991 Spring Conference of the Japan Society of Applied Physics, 953 pages, 28p-F-
1). 307 is an n-electrode and 308 is a p-electrode.
In the semiconductor photodetector, the p-type conductive layer 304 and the n-type
A reverse bias voltage is applied between the semiconductor layer 302 and the conductive layer 302 to form a depletion layer in the non-doped light absorbing layer 303. This is for photoelectrically converting the signal light incident on the light absorbing layer.

【0003】ところで、上記半導体光検出器の応答速度
は、CR時定数と光励起キャリアの走行時間とで決定さ
れる。上記光励起キャリアの走行時間を小さくするため
には光吸収層を薄くする必要があるが、上記光吸収層を
薄くすることによる静電容量Cの増加を抑えるため、光
吸収層の面積を小さくしなければならない。
Incidentally, the response speed of the semiconductor photodetector is determined by the CR time constant and the traveling time of the photoexcited carriers. In order to reduce the travel time of the photoexcited carriers, it is necessary to reduce the thickness of the light absorbing layer. However, in order to suppress an increase in capacitance C due to the thinning of the light absorbing layer, the area of the light absorbing layer is reduced. There must be.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記p
型導電層上面の一部にはp型オーミック電極を形成する
必要があるため、従来のように光吸収層の上部だけにp
型導電層を設けた半導体光検出器では、上記光吸収層の
面積を小さくした場合にp型オーミック電極の面積も必
然的に小さくなり、その結果、オーミック抵抗が増加し
てCR時定数が増大し、結局は高速応答ができないとい
う問題があった。
However, the above-mentioned p
Since it is necessary to form a p-type ohmic electrode on a part of the upper surface of the type conductive layer, the p-type ohmic electrode is
In a semiconductor photodetector provided with a type conductive layer, when the area of the light absorbing layer is reduced, the area of the p-type ohmic electrode is inevitably reduced. As a result, the ohmic resistance increases and the CR time constant increases. However, there was a problem that high-speed response could not be achieved after all.

【0005】本発明は、上記従来技術における静電容量
と寄生抵抗との関係を解消し、高速応答が可能な半導体
光検出器を得ることを目的とする。
An object of the present invention is to eliminate the relationship between the capacitance and the parasitic resistance in the prior art and to obtain a semiconductor photodetector capable of high-speed response.

【0006】[0006]

【課題を解決するための手段】上記目的は、半導体基板
上に設けたpn接合を有する半導体光検出器において、
上記pn接合部は側面を誘電体膜で覆ったリッジ状に形
成し、上記リッジ側面の周囲に空洞を形成するようにし
て、上記リッジを半導体層で埋め込んだことにより達成
される。
SUMMARY OF THE INVENTION The object of the present invention is to provide a semiconductor photodetector having a pn junction provided on a semiconductor substrate.
The pn junction is formed by forming a ridge with a side surface covered with a dielectric film, forming a cavity around the ridge side surface, and embedding the ridge with a semiconductor layer.

【0007】[0007]

【作用】本発明では、リッジ状のpn接合部の側面およ
び半導体基板上面の一部に形成した誘電体膜マスクを用
いて、pn接合部を半導体層で埋め込むことにより、上
記pn接合部の周囲に空洞を形成している。本発明では
pn接合部をリッジ状に形成するため、光吸収層の面積
とは独立に上部導電層の面積を設定することができ、光
吸収層の面積を小さく保ちながら、広い面積のp型オー
ミック電極を形成することができる。また、上記空洞に
よってn型下部導電層とp型上部導電層とが離されるた
め、下部導電層と上部導電層との間に生じる寄生容量を
低減することができるので、高速応答が可能な半導体光
検出器を得ることができる。
According to the present invention, the pn junction is buried with a semiconductor layer by using a dielectric film mask formed on the side surface of the ridge-shaped pn junction and a part of the upper surface of the semiconductor substrate, thereby forming the periphery of the pn junction. A cavity is formed. In the present invention, since the pn junction is formed in a ridge shape, the area of the upper conductive layer can be set independently of the area of the light absorption layer. An ohmic electrode can be formed. In addition, since the n-type lower conductive layer and the p-type upper conductive layer are separated from each other by the cavity, a parasitic capacitance generated between the lower conductive layer and the upper conductive layer can be reduced, so that a semiconductor capable of high-speed response can be obtained. A light detector can be obtained.

【0008】[0008]

【実施例】つぎに本発明の実施例を図面とともに説明す
る。図1は本発明による半導体光検出器の第1実施例を
示す構造図、図2(a)〜(d)は上記実施例の製造工
程を示す図、図3は本発明の第2実施例を示す半導体光
検出器の製造工程を示す図である。図1において、10
1は半絶縁性InP基板、102はn型InP下部導電
層、103はノンドープInGaAs光吸収層、104
はp型InP上部導電層、105は誘電体マスク、10
6は空洞、107はn型オーミック電極、108はp型
オーミック電極である。この半導体光検出器はノンドー
プInGaAs光吸収層103を光電変換層とする導波
路型pinホトダイオードの構成になっている。
Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a structural diagram showing a first embodiment of a semiconductor photodetector according to the present invention, FIGS. 2 (a) to 2 (d) are diagrams showing manufacturing steps of the above embodiment, and FIG. 3 is a second embodiment of the present invention. FIG. 6 is a diagram showing a manufacturing process of the semiconductor photodetector showing the above. In FIG. 1, 10
1 is a semi-insulating InP substrate, 102 is an n-type InP lower conductive layer, 103 is a non-doped InGaAs light absorbing layer, 104
Is a p-type InP upper conductive layer, 105 is a dielectric mask, 10
6 is a cavity, 107 is an n-type ohmic electrode, and 108 is a p-type ohmic electrode. This semiconductor photodetector has a configuration of a waveguide type pin photodiode using the non-doped InGaAs light absorption layer 103 as a photoelectric conversion layer.

【0009】上記半導体光検出器の製造は図2(a)〜
(d)に示すつぎの工程により行う。まず図2(a)に
示すように、半絶縁性InP基板101上に厚さ0.2
μmのn型InP下部導電層102と、厚さ0.5μm
のノンドープInGaAs光吸収層103をこの順にエ
ピタキシャル成長する。その後InP基板101が露出
するまで、上記n型InP下部導電層102とノンドー
プInGaAs光吸収層103をリッジ状にエッチング
する。ついで図2(b)に示すように、上記リッジ状に
形成された半導体層及び半絶縁性InP基板101の表
面全面に誘電体膜SiO2105を堆積し、リッジ側面
およびリッジ下部近傍のInP基板101表面だけを残
して、上記誘電体膜SiO2105を図2(c)に示す
ようにエッチングにより除去する。つぎに図2(d)に
示すように、厚さ2μmのp型InP上部導電層104
を選択成長する。この際、上記リッジ側面およびリッジ
下部近傍の誘電体膜SiO2105に覆われた部分に
は、上記上部導電層104が成長しないため、この部分
に空洞106が形成される。その後、上記リッジの一部
をノンドープInGaAs光吸収層103が露出するま
でエッチングし、露出した光吸収層103上にn型オー
ミック電極107を形成し、さらに上記p型InP上部
導電層104上にp型オーミック電極108を形成する
ことにより、図1に示すような半導体光検出器が得られ
る。
The manufacture of the semiconductor photodetector is shown in FIGS.
This is performed by the following steps shown in FIG. First, as shown in FIG. 2A, a film having a thickness of 0.2 mm is formed on a semi-insulating InP substrate 101.
μm n-type InP lower conductive layer 102 and a thickness of 0.5 μm
The non-doped InGaAs light absorption layer 103 is epitaxially grown in this order. Thereafter, the n-type InP lower conductive layer 102 and the non-doped InGaAs light absorbing layer 103 are etched in a ridge shape until the InP substrate 101 is exposed. Then, as shown in FIG. 2B, a dielectric film SiO 2 105 is deposited on the entire surface of the semiconductor layer formed in the ridge shape and the semi-insulating InP substrate 101, and the InP substrate near the ridge side surface and the lower portion of the ridge is formed. The dielectric film SiO 2 105 is removed by etching, as shown in FIG. Next, as shown in FIG. 2D, a p-type InP upper conductive layer 104 having a thickness of 2 μm is formed.
Select to grow. At this time, since the upper conductive layer 104 does not grow in the portion covered with the dielectric film SiO 2 105 near the ridge side surface and the lower portion of the ridge, a cavity 106 is formed in this portion. Thereafter, a part of the ridge is etched until the non-doped InGaAs light absorbing layer 103 is exposed, an n-type ohmic electrode 107 is formed on the exposed light absorbing layer 103, and a p-type ohmic electrode 107 is formed on the p-type InP upper conductive layer 104. By forming the type ohmic electrode 108, a semiconductor photodetector as shown in FIG. 1 is obtained.

【0010】上記p型InP上部導電層104の選択成
長により形成されるエピタキシャル層においては、上面
からの成長だけでなく側面からの成長も促進されるた
め、成長初期にはSiO2膜105によって分離されて
いた上部導電層104は、成長終了時になると図2
(d)に示すように互いにつながり合い、その結果、上
記p型InP上部導電層104は極めて広い面積を有す
ることになる。したがって、光吸収層103の面積を小
さく保ちながら、広い面積のp型オーミック電極108
を形成することが可能になる。また、上記空洞106に
よってn型InP下部導電層102とp型InP上部導
電層104との間が離隔されるため、上記両者間に生じ
る寄生容量を大幅に低減することができる。
[0010] separated by the above in the p-type InP upper conductive layer 104 epitaxial layer formed by selective growth, since the growth from the side as well as growth from the upper surface is promoted, the initial growth SiO 2 film 105 When the growth is completed, the upper conductive layer 104 which has been
As shown in (d), the p-type InP upper conductive layer 104 has an extremely large area. Therefore, while keeping the area of the light absorption layer 103 small, the p-type ohmic electrode 108 having a large area
Can be formed. Further, since the cavity 106 separates the n-type InP lower conductive layer 102 from the p-type InP upper conductive layer 104, the parasitic capacitance generated between the two can be significantly reduced.

【0011】本発明による製造方法を用いて製作した半
導体光検出器においては、幅1μmの光吸収層に対して
幅10μmのp型オーミック電極を形成した結果、寄生
抵抗は5Ωと従来の約10分の1に減少し、また寄生容
量を素子容量に比べて無視できる程度に小さくすること
ができ、応答速度は60GHZと従来の約4倍の性能を
実現することが可能になった。
In a semiconductor photodetector manufactured by using the manufacturing method according to the present invention, a p-type ohmic electrode having a width of 10 μm is formed on a light absorption layer having a width of 1 μm. The parasitic capacitance can be reduced by a factor of one, and the parasitic capacitance can be reduced to a negligible level as compared with the element capacitance. The response speed can be 60 GHZ, which is about four times the performance of the conventional device.

【0012】本発明の第2実施例である半導体光検出器
を、その製造工程を示す図3により説明する。図3にお
いて、201は半絶縁性InP基板、202はn型In
P下部導電層、203はノンドープInGaAs光吸収
層、204はp型InP上部導電層、205は誘電体マ
スク、206は空洞である。上記半導体光検出器はノン
ドープInGaAs光吸収層203を光電変換層とする
導波路型pinホトダイオードの構成になっている。
A semiconductor photodetector according to a second embodiment of the present invention will be described with reference to FIGS. In FIG. 3, 201 is a semi-insulating InP substrate, and 202 is an n-type InP.
A P lower conductive layer, 203 is a non-doped InGaAs light absorbing layer, 204 is a p-type InP upper conductive layer, 205 is a dielectric mask, and 206 is a cavity. The semiconductor photodetector has a configuration of a waveguide type pin photodiode using the non-doped InGaAs light absorption layer 203 as a photoelectric conversion layer.

【0013】上記半導体光検出器の製造方法を図3
(a)〜(d)に示す工程にしたがって説明する。ま
ず、半絶縁性InP基板201上に厚さ0.2μmのn
型InP下部導電層202および厚さ0.5μmのノン
ドープInGaAs光吸収層203を、この順にエピタ
キシャル成長し、図3(a)に示すように上記下部導電
層202と光吸収層203とを、半絶縁性基板201が
露出するまで逆メサ形リッジ状にエッチングする。つぎ
に図3(b)に示すように、上記リッジ状に形成された
半導体層および半絶縁性InP基板201上の全面に誘
電体膜SiO2205を堆積する。その後、上記半導体
基板上方よりイオンビームを照射して、上記誘電体膜S
iO2205を図3(c)に示すようにリッジの側面お
よび下部近傍を除いてエッチングにより除去する。ここ
で、上記リッジは逆メサ形状をしているため、リッジ側
面およびリッジ下部近傍はリッジの影になりイオンビー
ムが到達しない。そのため、上記リッジ側面およびリッ
ジ下部近傍のSiO2膜205はエッチングされないで
残ることになる。つぎに、図3(d)に示すように、厚
さ2μmのp型InP上部導電層204を選択成長する
が、上記リッジ側面およびリッジ下部近傍のSiO2
部分においては上記InP上部導電層204が成長しな
いため、この部分に空洞206が形成されることにな
る。第1実施例と同様に、上記リッジの一部をノンドー
プInGaAs光吸収層203が露出するまでエッチン
グし、上記吸収層203の表面にn型オーミック電極を
形成するとともに、上記p型InP上部導電層204上
にp型オーミック電極を形成して半導体光検出器を得
る。
FIG. 3 shows a method of manufacturing the semiconductor photodetector.
Description will be made in accordance with the steps shown in (a) to (d). First, a 0.2 μm thick n
A type InP lower conductive layer 202 and a non-doped InGaAs light absorbing layer 203 having a thickness of 0.5 μm are epitaxially grown in this order, and the lower conductive layer 202 and the light absorbing layer 203 are semi-insulated as shown in FIG. Etching is performed in an inverted mesa ridge shape until the conductive substrate 201 is exposed. Next, as shown in FIG. 3B, a dielectric film SiO 2 205 is deposited on the entire surface of the semiconductor layer formed in the ridge shape and the semi-insulating InP substrate 201. Thereafter, an ion beam is irradiated from above the semiconductor substrate to form the dielectric film S
As shown in FIG. 3C, the iO 2 205 is removed by etching except for the side surface and the lower portion of the ridge. Here, since the ridge has an inverted mesa shape, the side surface of the ridge and the vicinity of the lower portion of the ridge become shadows of the ridge, and the ion beam does not reach the ridge. Therefore, the SiO 2 film 205 near the ridge side surface and the lower portion of the ridge remains without being etched. Next, as shown in FIG. 3D, a p-type InP upper conductive layer 204 having a thickness of 2 μm is selectively grown, and the InP upper conductive layer 204 is formed on the side surface of the ridge and the SiO 2 film portion near the lower portion of the ridge. Does not grow, a cavity 206 is formed in this portion. As in the first embodiment, a part of the ridge is etched until the non-doped InGaAs light absorbing layer 203 is exposed, an n-type ohmic electrode is formed on the surface of the absorbing layer 203, and the p-type InP upper conductive layer is formed. A p-type ohmic electrode is formed on 204 to obtain a semiconductor photodetector.

【0014】上記半導体基板の上方からイオンビームを
照射してSiO2膜をエッチングにより除去する工程に
おいては、リッジが逆メサ形に形成されているためエッ
チングマスクを用いることなく、リッジ側面およびリッ
ジ下部近傍のSiO2膜205を残すことができるた
め、上記第1実施例に比べて製造の簡素化を行うことが
できるが、同様な効果が得られることはいうまでもな
い。
In the step of irradiating an ion beam from above the semiconductor substrate to remove the SiO 2 film by etching, since the ridge is formed in an inverted mesa shape, an etching mask is not used, and the ridge side surface and the ridge lower portion are used. Since the SiO 2 film 205 in the vicinity can be left, the manufacturing can be simplified as compared with the first embodiment, but it goes without saying that the same effect can be obtained.

【0015】上記各実施例は導波路型光検出器を実現し
た例を示したが、本発明を面入射型光検出器に適用する
ことにより、高速応答が可能な面入射型光検出器を実現
することができる。上記実施例では半導体材料としてI
nP基板と格子整合する材料を用いた例を示したが、こ
れらの一部または全部をInPと格子整合しない材料と
しても同様の効果が期待できる。また、信号光波長が
1.55μmの場合についての例を示したが、材料を適
当に選ぶことにより波長1.55μm以外の信号光に対
して、本実施例と同様の効果がある半導体光検出器が実
現できる。さらに、本構造を半導体レーザあるいは半導
体光変調器などの他の光素子に適用することも可能であ
る。
In each of the above embodiments, an example in which a waveguide type photodetector is realized has been described. By applying the present invention to a surface incident type photodetector, a surface incident type photodetector capable of high-speed response can be obtained. Can be realized. In the above embodiment, the semiconductor material is I
Although an example is shown in which a material that lattice-matches with the nP substrate is used, a similar effect can be expected even if some or all of these materials do not lattice-match with InP. Also, an example in which the signal light wavelength is 1.55 μm has been described. However, by appropriately selecting a material, a semiconductor light detection device having the same effect as that of the present embodiment can be applied to signal light having a wavelength other than 1.55 μm. Vessel can be realized. Further, the present structure can be applied to another optical element such as a semiconductor laser or a semiconductor optical modulator.

【0016】[0016]

【発明の効果】上記のように本発明による半導体光検出
器およびその製造方法は、半導体基板上に設けたpn接
合を有する半導体光検出器において、上記pn接合部は
側面を誘電体膜で覆ったリッジ状に形成し、上記リッジ
側面の周囲に空洞を形成するようにして、上記リッジを
半導体層で埋め込んだことにより、静電容量と寄生抵抗
との互いに相反する関係を解消してこれらを同時に低減
し、かつ、寄生容量が小さく高速応答が可能な半導体光
検出器を実現し、その製造方法を得ることができる。
As described above, according to the semiconductor photodetector and the method of manufacturing the same according to the present invention, in a semiconductor photodetector having a pn junction provided on a semiconductor substrate, the pn junction has a side surface covered with a dielectric film. The ridge is formed in such a manner that a cavity is formed around the side surface of the ridge, and the ridge is buried with a semiconductor layer. At the same time, it is possible to realize a semiconductor photodetector which is reduced and has a small parasitic capacitance and is capable of high-speed response, and a manufacturing method thereof can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体光検出器の第1実施例を示
す構造図である。
FIG. 1 is a structural diagram showing a first embodiment of a semiconductor photodetector according to the present invention.

【図2】(a)〜(d)は上記実施例の製造工程をそれ
ぞれ示す図である。
FIGS. 2 (a) to 2 (d) are diagrams respectively showing the manufacturing steps of the above embodiment.

【図3】本発明の第2実施例である半導体検出器で、
(a)〜(d)はそれぞれ製造工程を示す図である。
FIG. 3 shows a semiconductor detector according to a second embodiment of the present invention;
(A)-(d) is a figure which shows a manufacturing process, respectively.

【図4】従来の半導体光検出器を示す模式図である。FIG. 4 is a schematic diagram showing a conventional semiconductor photodetector.

【符号の説明】[Explanation of symbols]

101、201 半導体基板 102、202 n型下部導電層 103、203 光吸収層 104、204 p型上部導電層 105、205 誘電体膜 106、206 空洞 101, 201 Semiconductor substrate 102, 202 N-type lower conductive layer 103, 203 Light absorbing layer 104, 204 P-type upper conductive layer 105, 205 Dielectric film 106, 206 Cavity

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭47−23182(JP,A) 特開 昭50−140285(JP,A) 特開 平2−166774(JP,A) ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-47-23182 (JP, A) JP-A-50-140285 (JP, A) JP-A-2-166774 (JP, A)

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板上に設けたpn接合を有する半
導体光検出器において、上記pn接合部は側面を誘電体
膜で覆ったリッジ状に形成し、上記リッジ側面の周囲に
空洞を形成するようにして、上記リッジを半導体層で埋
め込んだことを特徴とする半導体光検出器。
In a semiconductor photodetector having a pn junction provided on a semiconductor substrate, the pn junction is formed in a ridge shape with a side surface covered with a dielectric film, and a cavity is formed around the ridge side surface. A semiconductor photodetector having the ridge embedded in a semiconductor layer as described above.
【請求項2】半導体基板上に設けたpn接合を有する半
導体光検出器の製造方法において、上記半導体基板上に
pn接合を有する半導体光検出器層を形成したのち、上
記半導体光検出器層をリッジ状に形成する工程と、上記
リッジの側面および下部近傍の基板上面に誘電体膜を堆
積する工程と、上記リッジを半導体層の成長により埋め
込む工程とを有することを特徴とする半導体光検出器の
製造方法。
2. A method for manufacturing a semiconductor photodetector having a pn junction provided on a semiconductor substrate, comprising: forming a semiconductor photodetector layer having a pn junction on the semiconductor substrate; Forming a ridge, depositing a dielectric film on the upper surface of the substrate near the side surface and lower portion of the ridge, and embedding the ridge by growing a semiconductor layer. Manufacturing method.
JP4289950A 1992-10-28 1992-10-28 Semiconductor photodetector and method of manufacturing the same Expired - Fee Related JP2711055B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4289950A JP2711055B2 (en) 1992-10-28 1992-10-28 Semiconductor photodetector and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4289950A JP2711055B2 (en) 1992-10-28 1992-10-28 Semiconductor photodetector and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH06140658A JPH06140658A (en) 1994-05-20
JP2711055B2 true JP2711055B2 (en) 1998-02-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP4289950A Expired - Fee Related JP2711055B2 (en) 1992-10-28 1992-10-28 Semiconductor photodetector and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2711055B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3447806B1 (en) * 2016-04-19 2021-03-03 Nippon Telegraph And Telephone Corporation Optical waveguide integrated light receiving element and method for manufacturing same

Also Published As

Publication number Publication date
JPH06140658A (en) 1994-05-20

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