JPS5391662A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5391662A
JPS5391662A JP593977A JP593977A JPS5391662A JP S5391662 A JPS5391662 A JP S5391662A JP 593977 A JP593977 A JP 593977A JP 593977 A JP593977 A JP 593977A JP S5391662 A JPS5391662 A JP S5391662A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
dullness
inaccuracy
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP593977A
Other languages
Japanese (ja)
Other versions
JPS6126214B2 (en
Inventor
Akihiro Tomosawa
Masayasu Tsunematsu
Jun Ueda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP593977A priority Critical patent/JPS5391662A/en
Publication of JPS5391662A publication Critical patent/JPS5391662A/en
Publication of JPS6126214B2 publication Critical patent/JPS6126214B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To avoid the inaccuracy and lowering in yield rate, by preventing the occurrence of dullness and pin holes through avoiding the etching for a long time, when the substrate contact is taken out from the surface of the semiconductor substrate.
JP593977A 1977-01-24 1977-01-24 Manufacture for semiconductor device Granted JPS5391662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP593977A JPS5391662A (en) 1977-01-24 1977-01-24 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP593977A JPS5391662A (en) 1977-01-24 1977-01-24 Manufacture for semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP18498583A Division JPS59112619A (en) 1983-10-05 1983-10-05 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5391662A true JPS5391662A (en) 1978-08-11
JPS6126214B2 JPS6126214B2 (en) 1986-06-19

Family

ID=11624860

Family Applications (1)

Application Number Title Priority Date Filing Date
JP593977A Granted JPS5391662A (en) 1977-01-24 1977-01-24 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5391662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599722A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Preparation of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599722A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Preparation of semiconductor device

Also Published As

Publication number Publication date
JPS6126214B2 (en) 1986-06-19

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