JPS59112619A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the abrupt formation of contacting holes in a substrate by removing an insulating film in a hole with a resist film having holes wider than a field insulating film to be etched as a mask. CONSTITUTION:A field oxidized film 2 is formed on the surface of a P type semiconductor substrate 1, partly removed, a gate insulating film, a polysilicon layer 3 and a source-drain layer are formed, and a PSG film 4 is formed on the entire surface. Subsequently, part of the film 2 an N<+> type diffused layer and the layer 3 are exposed by contacting photoresist 6. Then, the remaining field oxidized film is etched by a substrate contacting photoresist 7 to expose the substrate. Thereafter, the resist 7 is removed, aluminum is deposited, and electrodes and wirings 8 to be respectively connected to the substrate 1 and the layer 3 are formed. According to this manufacturing method, the contacting holes of the substrate are not abruptly formed, thereby facilitating the formation of the electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for making a substrate contact from a surface portion of a semiconductor substrate (a surface portion of a semiconductor substrate on which an active region such as a transistor is formed) in a semiconductor device, and mainly relates to a method for making a substrate contact from a surface portion of a semiconductor substrate (a surface portion of a semiconductor substrate on which an active region such as a transistor is formed). 5FET
Or called MOSFET. ) consisting of a semiconductor integrated circuit (
IC) Yet target.

Recently, mounting using a tape carrier method has been considered, which is extremely effective in reducing device costs through automation of bonding technology and assembly technology.

Regarding the implementation of this mount, for example, E1 electronic
cs+February 1971, pages 44 to 48 r ICon film 5trip 1en
d them serve t.

automatic handling by rna
It was introduced in the nufacturer anduser tool.

By the way, when mounting MISIC using the tape carrier method, external leads (lead frames) are placed on the back side of the semiconductor substrate.
Since the semiconductor board is not attached, the semiconductor substrate is electrically floating. As a result, the substrate potential becomes unstable, the operating margin becomes extremely poor, and the performance decline becomes unavoidable. Therefore, in the case of the tape carrier method, it is necessary to take out the substrate contact electrode directly from the surface of the substrate.

By the way, in order to take out a substrate contact from the surface on the side where the active region (source/drain region) is formed in a MOSIC, the thick field oxide film must be photo-etched to expose the substrate, and aluminum must be vapor-deposited there to serve as the electrode. Bananaashi.

That is, as shown in Figure 2, a resist film with a predetermined pattern was formed on the field oxide film, and the underlying oxide film was etched away using this as a mask to form an opening for substrate contact. . However, according to such a method, (a) the oxide film around the opening suddenly becomes more concentrated;

A connection failure occurs in the aluminum wiring at that portion. (
Hereinafter, this will be referred to as an AA stage disconnection defect. ) (b) Several methods are known for smoothing the edges as described above, but each method requires the addition of a subordinate step.

When contact holes (openings) are formed, pinholes in the photoresist occur in the field oxide film, reducing the reliability of the semiconductor.

Various problems such as this occur.

Therefore, one object of the present invention is to provide a highly reliable semiconductor manufacturing technology.

One object of the present invention is to provide a substrate contact forming technique with simple steps.

One object of the present invention is to provide an integrated circuit technology that is compatible with MO8FET technology.

A brief overview of typical inventions disclosed in this application is as follows. That is,
Using a resist film having an opening wider than the field oxide film portion to be removed by etching as a mask, the field oxide film within the opening is removed to form a substrate contact opening.

The present invention will be described in detail below with reference to FIG.

That is, (a) a thick field oxide film 2 is formed on the surface of the P-type semiconductor substrate 1, a part of which is removed by etching, and a gate insulating film is formed (not shown).

After forming the polysilicon layer 3 and the source/drain layers, PSG (Phosphorus) is applied to the entire surface.
A Silicate Glass) film 4 is formed. In this PSG film, a 5in2 film containing no impurities is exposed (
・Since it is impossible to protect the semiconductor surface from contamination by ions such as Na, glass containing phosphorus is used (see FIG. 1 (al)).

(b) A part of the field oxide film, the n+ diffusion layer and the polysilicon layer are exposed using a contact photon 6 (see FIG. 1(b)).

(c) Using substrate contact photoresist 7, the remaining field oxide film is etched to expose the substrate (first
(See figure (C)).

(d) After that, the photoresist 7 is removed and aluminum is deposited to form electrodes or wirings 8 connected to the substrate and the polysilicon layer, respectively (see FIG. 1(d)).

Let me explain in more detail.

fal Prepare one P-type silicon semiconductor substrate (sea urchin...) and form field oxide silicon (SiO2) by surface oxidation.
) After forming the film 12 to a thickness of approximately 1.0 to 1.4 μm, etching is performed using a selectively formed photoresist film (not shown) as a mask. The portion of the semiconductor substrate that should be H is exposed.

(bl) Next, the gate oxide film 13 by thermal oxidation is
A polycrystalline silicon layer 3 is formed thereon to a thickness of approximately 0.30 to 0.60 μm.

(c) The polysilicon layer 3 is selectively removed using a mixed etching solution consisting of hydrofluoric acid, nitric acid, and glacial acetic acid, leaving behind the polysilicon layer for the gate electrode and the polysilicon layer for the wiring. Using the polysilicon layer as a mask, the gate oxide film is self-line etched to expose a portion of the substrate.

(d) Perform phosphorus diffusion on the exposed substrate and polysilicon layer to form source, drain, gate, and polysilicon interconnects! 4! form a layer. After that, a 15vc phosphorus silicate glass layer with a Linnaeus purity concentration of 3.5 mol% or more is applied to the entire surface.
+oooX degree CV D (ChemicalVap
or Deposition) method. Then, the silicate glass layer is densified by performing high temperature treatment at a heat treatment temperature of 1000 tl or more for several minutes to several tens of minutes.

(e) Contact photoresist 6? Using this photoresist 6 as a mask, the phosphosilicate glass (PSG) film on the source 7 drain region of the active area, the contact area, and the polysilicon wiring cr in the high field area is exposed to hydrofluoric acid and centre,
It is selectively removed using a mixed etching solution consisting of ammonium chloride.

(f) The contact resist 6 is removed once, and a new substrate contact photoresist 7 is selectively formed. Using this photoresist 7 as a mask, the field oxide film 2 in the substrate contact region I is selectively removed using an etching solution made of hydrofluoric acid.

(g) After that, the photoresist 7 is removed, the aluminum 8 is evaporated, and a photoresist process is performed using a wiring pattern photomask, and the source of the active area is
Aluminum electrodes S and D are ohmically connected to the drain and gate polysilicon layers and the wiring polysilicon layer on the field portion, respectively.

At the same time as forming G1, a wiring G2 connected to the substrate contact portion is formed.

Since the substrate contact area (■) is processed in parallel with the formation of the active area (■), the substrate bias electrode can be formed on the surface of the substrate without increasing the number of steps by simply adding a substrate contact photoetching step to the normal process. It can be provided in

Therefore, even if the MISIC according to the present invention is mounted using a tape carrier method, the substrate is not in a floating state (potentially), but can be grounded or a predetermined bias voltage can be applied, and the operating margin will not deteriorate. Along with this, a high performance and highly reliable M I S I C can be obtained at extremely low cost by mounting using a tape carrier method.

The present invention is not limited to the above-mentioned embodiments, but has various embodiments in addition to the above embodiments.

In the embodiment described above, after contact photoetching, a substrate contact photoresist 19 is applied thereon without removing the contact photoresist 6, and then photoetched. This method is effective in preventing pinholes because the resist is doubled. However, this method cannot be used for devices in which the glass flow step is performed after contact photoetching.

The scope of application of this invention is as follows.

(1) In the embodiment, a p-type semiconductor substrate was used (*Although the description has been made from an n-channel MISICK, it can also be applied to a p-channel MISIC.

(2) The process is equally applicable to planar technology and LOCO8 technology.

(The gate part of the 31MISFET should be a polysilicon gate (a molybdenum gate is also acceptable).

(4) Photoresists for polysilicon and photoresists for contacts.The window opening size and shape of photoresists for substrate contacts are not limited.

As explained above, according to the present invention, the substrate contact hole does not have a steep t(t), and the electrode can be easily formed, so that a highly reliable semiconductor manufacturing technology can be achieved.

Further, there is almost no need for subordinate processes, and a substrate contact technology with simple steps can be provided.

[Brief explanation of the drawing]

FIG. 1 (a), (b), (c), (di is a cross-sectional view of a device showing the process of an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an outline of a conventional substrate contact hole forming method. [Explanation of symbols]

Claims (1)

[Claims] 1. (a) Step of forming a field insulating film having a predetermined pattern on a semiconductor substrate (b) Selectively forming the field between a plurality of openings or between different parts of the same opening A method for manufacturing a semiconductor device comprising: (c) removing the insulating film to expose the semiconductor substrate; and forming a substrate contact electrode on the exposed portion.