JPH0758058A - Wiring structure and manufacture therof - Google Patents

Abstract

PURPOSE:To secure the adhesion of a silicide layer in a polycide structure and simplify the manufacturing process so as to reduce the manufacturing cost in case when making connections between different conductivity type diffusion layers through wirings of the polycide structure. CONSTITUTION:An interlaminar insulating film 15 is formed on a semiconductor board 11 where a first conductivity type (N-type) diffusion layer 12 and a second conductive (P-type) diffusion layer 13 are formed on the upper layer of a semiconductor board 11 and a polysilicon wiring 16 is installed to the layer insulating film 15 between the upper parts of the N-type and P-type diffusion layers 12 and 13. A first connection hole 17 and a second connection hole 18 are formed on the layer insulating film 15 on the N-type and P-type diffusion layers 12 and 13. A silicide wiring 19 which is connected to the N-type and P-type diffusion layers 12 and 13 by way of the first and second connection holes 17 and 18, is further formed on the polysilicon wiring 16, thereby forming a wiring 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure for connecting different conductive type diffusion layers of a semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a Full-CMOS type circuit, it is necessary to connect an N type diffusion layer and a P type diffusion layer by wiring. As a conventional example thereof, a structure in which an N-type diffusion layer and a P-type diffusion layer formed on an upper layer of a semiconductor substrate are connected by wiring will be described with reference to a schematic configuration sectional view of FIG.

As shown in FIG. 3, an N type diffusion layer 52 and a P type diffusion layer 53 are formed on the upper layer of the semiconductor substrate 51. The N-type and P-type diffusion layers 52 and 53 are separated by an element isolation region 54 formed in the upper layer of the semiconductor substrate 51. Furthermore, an interlayer insulating film 55 is formed on the upper surface of the semiconductor substrate 51, and the N-type and P-type diffusion layers 5 are formed.
First and first connection holes 56, 57 are formed in the interlayer insulating film 55 on the layers 2, 53. Then, the N-type and P-type diffusion layers 52 and 5 are formed through the first and second connection holes 56 and 57.
The wiring 58 connected to 3 is formed.

The wiring 58 is made of aluminum or aluminum alloy.

Alternatively, the wiring 58 is made of a refractory metal silicide such as tungsten silicide, molybdenum silicide or titanium silicide.

Next, another example of the wiring structure will be described with reference to the schematic sectional view of FIG. As shown in FIG. 4, an N-type diffusion layer 72 and a P-type diffusion layer 73 are formed on the semiconductor substrate 71.
And are formed. The N-type and P-type diffusion layers 72 and 73
Is the element isolation region 7 formed in the upper layer of the semiconductor substrate 71.
Separated by four. Further, the semiconductor substrate 71
An interlayer insulating film 75 is formed on the upper surface of
First and first connection holes 76 and 77 are formed in the interlayer insulating film 75 on the p-type and p-type diffusion layers 72 and 73.

A wiring 78 is formed to connect to the N-type and P-type diffusion layers 72 and 73 through the first and second connection holes 76 and 77. The wiring 78 has a lower layer made of a polysilicon layer 79 and an upper layer made of a refractory metal silicide layer 80. An N-type impurity (not shown) is introduced into the polysilicon layer 79 on the N-type diffusion layer 72 side, and a P-type impurity (not shown) is introduced into the polysilicon layer 79 on the P-type diffusion layer 73 side. Have been introduced.

[0008]

Of the above wiring structures,
When the wiring formed of aluminum or aluminum alloy is applied to, for example, a Full-CMOS type SRAM, a multilayer structure of aluminum-based metal wiring must be adopted in order to reduce the size of the memory cell. However, the multi-layer structure of aluminum-based metal wiring complicates the process, and thus the yield is reduced.

When the wiring is formed of silicide, the adhesion between the interlayer insulating film which is the base of the silicide and the silicide layer is poor, and the silicide layer is easily peeled off.

Further, when the wiring is formed of a polycide layer composed of a polysilicon layer and a silicide layer, N
N-type impurities are introduced into the polysilicon layer connected to the type diffusion layer, P-type impurities are introduced into the polysilicon layer connected to the P-type diffusion layer, and the contact resistance with each diffusion layer is increased. Need to be reduced. Therefore, N type, P
It is necessary to form an ion implantation mask for introducing the type impurities into the polysilicon layer. As a result,
Since two mask processes are required, the manufacturing cost becomes high.

It is an object of the present invention to provide a wiring structure which secures the adhesion of a silicide layer and keeps the manufacturing cost low, and a manufacturing method thereof.

[0012]

SUMMARY OF THE INVENTION The present invention is a wiring structure and a method of manufacturing the same for achieving the above object. That is, as the wiring structure, the first conductive type diffusion layer and the second conductive type diffusion layer are formed on the upper layer of the semiconductor substrate, and the interlayer insulating film is formed on the semiconductor substrate. Polysilicon wiring is provided on the interlayer insulating film between the first and second conductivity type diffusion layers. Then, first and second connection holes are formed correspondingly to the interlayer insulating film and the polysilicon wiring on the first and second conductivity type diffusion layers. Further, through the first and second connection holes,
The silicide wiring is formed on the polysilicon wiring in a state of being connected to the second conductivity type diffusion layer.

As the method of manufacturing the wiring structure, in the first step, an interlayer insulating film is formed on the semiconductor substrate having the first and second conductivity type diffusion layers formed on the upper layer of the semiconductor substrate, and the upper surface thereof is further formed. Form a polysilicon layer. Next, in a second step, first and second connection holes are formed in the interlayer insulating film and the polysilicon layer on the first and second conductivity type diffusion layers. Then, in a third step, a silicide layer is formed on the polysilicon layer in a state of being connected to the first and second conductivity type diffusion layers via the first and second connection holes. Then, in a fourth step, a wiring that connects to the first and second conductivity type diffusion layers is formed using the polysilicon layer and the silicide layer.

[0014]

In the above wiring structure, the silicide wiring is connected to the first conductive type diffusion layer and the second conductive type diffusion layer, and the polysilicon wiring is formed between the interlayer insulating film and the silicide wiring. Adhesion of the silicide wiring is secured.

In the wiring structure manufacturing method, after forming the interlayer insulating film and the polysilicon layer, the first and second connection holes are formed in the interlayer insulating film and the polysilicon layer, and then the first and second connecting holes are formed.
By forming the silicide layer connected to the first and second conductivity type diffusion layers through the connection hole, the adhesion of the silicide layer is secured. Further, unlike the conventional polycide structure wiring, a mask process for introducing impurities is not required, so that the manufacturing process is short and the manufacturing cost is low. Further, since the polycide layer including the polysilicon layer and the silicide layer is processed to form the wiring, the workability is high. Since the wiring is not formed of aluminum-based metal, the multi-layer wiring process is simplified. Therefore, the reduction in manufacturing yield can be suppressed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the wiring structure of the present invention will be described with reference to the schematic sectional view of FIG.

As shown in the figure, a first conductivity type (hereinafter referred to as N type) diffusion layer 12 and a second conductivity type (hereinafter referred to as P type) diffusion layer 13 are formed on an upper layer of the semiconductor substrate 11. There is.
The N-type and P-type diffusion layers 12 and 13 are divided by the element isolation region 14 formed in the semiconductor substrate 11 on the side of the sides thereof. The semiconductor substrate 11 is, for example, N
Formed of silicon. A P well region 31 is formed in the semiconductor substrate 11 so as to cover the lower side of the N type diffusion layer 12.

An interlayer insulating film 15 is formed on the semiconductor substrate 11.
Are formed. The interlayer insulating film 15 is made of, for example, silicon oxide. A polysilicon wiring 16 is formed on the interlayer insulating film 15 between the upper portions of the N-type and P-type diffusion layers 12 and 13.
Is provided.

Then, the first and second connection holes 17 and 18 are formed in the interlayer insulating film 15 and the polysilicon wiring 16 on the N-type and P-type diffusion layers 12 and 13, respectively. . Furthermore, N is passed through the first and second connection holes 17 and 18.
A silicide wiring 19 is formed on the polysilicon wiring 16 in a state of being connected to the p-type and p-type diffusion layers 12 and 13. The silicide wiring 19 is made of a refractory metal silicide such as tungsten silicide, molybdenum silicide or titanium silicide.

As described above, the wiring 20 is formed by the polysilicon wiring 16 and the silicide wiring 19.

In the above wiring structure, the silicide wiring 19 is connected to the N-type diffusion layer 12 and the P-type diffusion layer 13, and the polysilicon wiring 16 is formed between the interlayer insulating film 15 and the silicide wiring 19. As a result, the silicide wiring 19
Adhesion is secured.

In the above embodiments, the case where the semiconductor substrate 11 is made of N-type silicon has been described. However, when the semiconductor substrate 11 is made of P-type silicon, the conductivity type of each component is set to the above. The conductivity type may be opposite to the conductivity type described.

Next, a method of manufacturing the wiring structure described with reference to FIG. 1 will be described with reference to the manufacturing process diagram of FIG.

As shown in FIG. 2A, the semiconductor substrate 1
A first conductivity type (N type) diffusion layer 12 and a second conductivity type (P type) diffusion layer 13 are formed on the upper layer of the first layer. Each N type, P
An element isolation region 14 is formed in the semiconductor substrate 11 on the peripheral side of the type diffusion layers 12 and 13. A P well region 31 is formed on the semiconductor substrate 11 so as to cover the lower side of the N type diffusion layer 12. The semiconductor substrate 11 is made of first conductivity type (N type) silicon.

First, in the first step, the interlayer insulating film 15 is formed on the semiconductor substrate 11 by, for example, the CVD method.
The interlayer insulating film 15 is made of, for example, silicon oxide. Further, a polysilicon layer 21 is formed on the upper surface of the interlayer insulating film 15 by the CVD method, for example.

Next, a second step shown in FIG. 2B is performed. In this step, the interlayer insulating film 15 and the polysilicon on the N-type and P-type diffusion layers 12 and 13 are formed by lithography and etching. The layer 21 and the first and second connection holes 1
7 and 18 are formed. Then, the etching mask (not shown) used for the above etching is removed by asher processing, wet etching, or the like.

Subsequently, the third step shown in FIG. 2C is performed. In this step, the N-type and P-type diffusion layers 1 are formed through the first and second connection holes 17 and 18 by the sputtering method, for example.
A silicide layer 22 is formed on the polysilicon layer 21 in a state of being connected to the electrodes 2 and 13.

In the above description, the silicide layer 22 is formed by the sputtering method, but it may be formed by the CVD method, for example. Generally, the silicide layer 22 formed by the sputtering method has a higher crystallinity than that formed by the CVD method.

Thereafter, a fourth step shown in FIG. 2 (4) is performed. In this step, the polysilicon layer (21) and the silicide layer (2
2) is used to form the wiring 20 connected to the N-type and P-type diffusion layers 12 and 13. Therefore, the wiring 20 is composed of the polysilicon wiring 16 made of the polysilicon layer (21) and the silicide wiring 19 made of the silicide layer (22).

In the method of manufacturing the wiring structure described above, after the interlayer insulating film 15 and the polysilicon layer 21 are formed, the first and second connection holes 17 are formed in the interlayer insulating film 15 and the polysilicon layer 21.
18 is formed, and then the silicide layer 22 connected to the N-type and P-type diffusion layers 12 and 13 is formed through the first and second connection holes 17 and 18, so that the adhesion of the silicide layer 22 is secured. To be done. Further, unlike the conventional polycide structure wiring, a mask process for introducing impurities is not required, so that the manufacturing process is short and the manufacturing cost is low. Further, since the polycide layer including the polysilicon layer 21 and the silicide layer 22 is processed to form the wiring 20, the workability is high. Further, since the wiring 20 is not formed of an aluminum-based metal, the subsequent multi-layer wiring process using the aluminum-based metal is simplified. Therefore, the reduction in manufacturing yield can be suppressed.

As a method of forming the silicide layer 22, although not shown, for example, the first and second connection holes 1 are formed.
After forming 7 and 18, a polysilicon film having a film thickness to be silicided is formed on the upper surface of the interlayer insulating film 15 together with the inner walls of the first and second connection holes 17 and 18. Further, a refractory metal film which is silicided is formed on the surface of the polysilicon film. After that, the polysilicon film and the refractory metal film may be silicidized to form the silicide layer 22.

In the manufacturing method of the above embodiment, the semiconductor substrate 1
Although the case where 1 is made of N-type silicon has been described, when the semiconductor substrate 11 is made of P-type silicon, the conductivity type of each component may be a conductivity type having a polarity opposite to the conductivity type described above. .

[0033]

As described above, according to the present invention,
Since the silicide wiring is connected to the first conductive type diffusion layer and the second conductive type diffusion layer and the polysilicon wiring is formed between the interlayer insulating film and the silicide wiring, it is possible to secure the adhesion of the silicide wiring. it can. Therefore, the reliability of the wiring can be improved.

In the wiring structure manufacturing method, after forming the interlayer insulating film and the polysilicon layer, the first and second connection holes are formed in the interlayer insulating film and the polysilicon layer, and then the first and second connecting holes are formed.
Since the silicide layer connected to the first and second conductivity type diffusion layers is formed through the connection hole, the adhesion of the silicide layer can be secured. Therefore, the manufacturing yield can be improved. Further, unlike the conventional polycide structure wiring, a mask process for introducing impurities is not required, so that the manufacturing process is shortened. Therefore, the manufacturing cost can be reduced. Furthermore, since the wiring is formed by processing the polycide layer including the polysilicon layer and the silicide layer, the workability is high. Therefore, it is possible to improve the dimensional accuracy. Since the wiring is not formed of aluminum-based metal, the multi-layer wiring process is simplified.
Therefore, it is possible to suppress a decrease in manufacturing yield.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an example.

FIG. 2 is a manufacturing process diagram of an example.

FIG. 3 is a schematic configuration sectional view of a conventional example.

FIG. 4 is a schematic cross-sectional view of another conventional example.

[Explanation of symbols]

Reference Signs List 11 semiconductor substrate 12 first conductivity type (N-type) diffusion layer 13 second conductivity type (P-type) diffusion layer 15 interlayer insulating film 16 polysilicon wiring 17 first connection hole 18 second connection hole 19 silicide wiring 20 wiring 21 poly Silicon layer 22 Silicide layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication 8826-4M H01L 21/88 Q 8826-4M 21/90 D

Claims (2)

[Claims] 1. A wiring structure for connecting a first conductivity type diffusion layer and a second conductivity type diffusion layer formed on an upper layer of a semiconductor substrate, comprising: an interlayer insulating film formed on the semiconductor substrate; A polysilicon line disposed on the interlayer insulating film between the conductive type diffusion layer and the second conductive type diffusion layer; the interlayer insulating film on the first conductive type diffusion layer; Via a first connection hole formed in the silicon wiring, a second connection hole formed in the interlayer insulating film on the second conductive type diffusion layer and the polysilicon wiring, and the first and second connection holes. And a silicide wiring formed on the polysilicon wiring and connected to the first and second conductivity type diffusion layers. 2. The method of manufacturing a wiring structure according to claim 1, wherein an interlayer insulating film is formed on the semiconductor substrate having a first conductivity type diffusion layer and a second conductivity type diffusion layer formed on an upper layer of the semiconductor substrate. Forming, and further forming a polysilicon layer on the upper surface of the interlayer insulating film; and forming a first connection hole in the interlayer insulating film and the polysilicon layer on the first conductivity type diffusion layer. A second step of forming a second connection hole in the interlayer insulating film and the polysilicon layer on the second conductivity type diffusion layer, and the first and second connection holes via the first and second connection holes. A third step of forming a silicide layer on the polysilicon layer in a state of being connected to the second conductivity type diffusion layer; and using the polysilicon layer and the silicide layer, the first and second conductivity type diffusions. Performing a fourth step of forming wiring connecting to the layer Method for manufacturing a wiring structure according to symptoms.