JPH08236627A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To obtain a method for fabricating a semiconductor device in which conduction is ensured between first and second interconnection layers even if the first interconnection layers is exposed to etching substance for a long time at the time of making an opening. CONSTITUTION: A field insulation layer 12 is formed on a conductor layer 15 through same process as forming a gate electrode 15. A first interlayer insulation layer 18 having a first opening 18a is then formed thereon followed by formation of a first interconnection layer 19 being connected with the conductor layer 15 through the first opening 18. Subsequently, a second interlayer insulation layer 20 having a second opening 20a, corresponding to the first opening 18a, is formed on the first interconnection layer 19. Finally, a second interconnection layer 21a is formed to be connected with the first interconnection layer 19 and/or the conductor layer 15 through the first opening 18a and the second opening 20a.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present application relates to a method of manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art In recent years, silicon integrated circuits having a so-called multilayer wiring structure have been widely used.

FIG. 3 shows an example of a MOS type silicon integrated circuit having a multi-layer wiring structure, showing a constituent portion of a static RAM.

Reference numeral 51 is a silicon substrate, 52 is a field insulating layer having a LOCOS structure, 53 is a gate insulating layer, 54 is a gate electrode, 56 is a source, and 57 is a drain. 58
Is a first interlayer insulating layer, and 60 is a second interlayer insulating layer.
Reference numeral 59 is a polysilicon layer that serves as a first wiring layer, and a high resistance region is formed in a part thereof to form a high resistance load of the static RAM. 61a, 61b and 61c are aluminum layers which will be the second wiring layer. The aluminum layers 61b and 61c are connected to the gate electrode 54 and the source 56, respectively, through openings formed in the first interlayer insulating layer 58 and the second interlayer insulating layer 60. The aluminum layer 61a is connected to the polysilicon layer 59 through the opening formed in the second interlayer insulating layer 60.

[0005]

In the conventional example described above, the opening for connecting the polysilicon layer 59, the opening for connecting the gate electrode 54 and the opening for connecting the source 56 are formed in the same step. To be done. In this case, in order to form the opening for connecting the polysilicon layer 59, only the second interlayer insulating layer 60 needs to be etched, but the opening for connecting the gate electrode 54 and the connection for the source 56 are formed. The first interlayer insulating layer 58 must also be etched in order to form the opening. Therefore, in the opening for connecting the polysilicon layer 59, the polysilicon layer 59 is exposed to the etching substance for a long time even after the etching of the second interlayer insulating layer 60 is completed. Therefore, as shown in FIG. 3, even the polysilicon layer 59, which should not be originally etched, is also etched, resulting in a problem of conduction failure.

An object of the invention according to the present application is to reliably establish conduction between the first wiring layer and the second wiring layer even when the first wiring layer is exposed to an etching substance for a long time when the opening is formed. A method of manufacturing a semiconductor device is provided.

[0007]

A conductor layer is formed under a first wiring layer, and this conductor layer is formed in the same step as a gate electrode forming step. Even if the first wiring layer is exposed to the etching substance for a long time when the opening is formed, it is possible to surely establish electrical continuity between the first wiring layer and the second wiring layer through the conductive layer. Moreover, since the conductor layer is formed in the same step as the step of forming the gate electrode, the manufacturing process can be simplified.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION A conductor layer is formed on a field insulating layer by the same step as the step of forming a gate electrode. Next, a first interlayer insulating layer having a first opening is formed on the conductor layer. Next, a first wiring layer connected to the conductor layer in the first opening is formed on the first interlayer insulating layer. Next, a second interlayer insulating layer having a second opening corresponding to the first opening is formed on the first wiring layer.
Then, through the first opening and the second opening, the first opening
Forming a second wiring layer connected to the wiring layer and / or the conductor layer.

[0009]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIGS. 1A to 1E show an example of a manufacturing process of a MOS type silicon integrated circuit having a multi-layer wiring structure, showing a constituent part of a static RAM.

Reference numeral 11 is a silicon substrate, 12 is a field insulating layer having a LOCOS structure, and 13 is a gate insulating layer (having a film thickness of 30).
Nanometer). 14 is a gate electrode, which is formed by using polysilicon. Reference numeral 15 is a conductor layer, which is formed of polysilicon similarly to the gate electrode 14. Reference numeral 16 is a source and 17 is a drain. 1
Reference numeral 8 is a first interlayer insulating layer (thickness: 300 nanometers), which is made of silicon oxide. 18 a is a first opening, which is formed inside the conductor layer 15. 1
8b is an opening for drain. Reference numeral 19 is a first wiring layer (film thickness 50 nanometers), which is made of polysilicon. The first wiring layer 19 connects the drain 17 to a second wiring layer 21a described later. Further, the high resistance region formed in a part thereof forms a high resistance load of the static RAM. Reference numeral 20 is a second interlayer insulating layer (thickness: 300 nanometers), which is made of silicon oxide. Reference numeral 20a is a second opening, which is formed inside the first opening 18a. 20b is a gate electrode opening, and 20c is a source opening. Two
Reference numerals 1a, 21b, and 21c are second wiring layers, which are made of aluminum.

Next, according to FIGS. 1 (A) to (E),
The manufacturing process will be described.

(A) The gate electrode 1 is formed on the gate insulating layer 13.
4, a conductor layer 15 is formed on the field insulating layer 12 in the same step. That is, the polysilicon forming the gate electrode 14 and the conductor layer 15 is formed on the silicon substrate 11
After being formed by the CVD method on the main surface side of, the gate electrode 14 and the conductor layer 15 are simultaneously formed by patterning this.

(B) After the first interlayer insulating layer 18 is formed by the CVD method, a part of it is dry-etched,
The first opening 18a and the drain opening 18b are formed. At this time, a gate is formed in the drain opening 18b.
The insulating layer 13 is also etched at the same time. For example, CHF3 can be used as the etching gas.

(C) After forming a high-resistance polysilicon layer on the main surface side of the silicon substrate 11, this is patterned to form a first wiring layer 19. After forming the high-resistance polysilicon layer or after patterning it, a part of the high-resistance polysilicon layer is masked to dope impurities to reduce the resistance of the polysilicon layer other than the mask portion. Turn into. The high resistance polysilicon layer of the mask portion becomes a high resistance load of the static RAM.

(D) After forming the second interlayer insulating layer 20 by the CVD method, a part thereof is dry-etched,
A second opening 20a, a gate electrode opening 20b and a source opening 20c are formed. At this time, the first interlayer insulating layer 18 is etched in the gate electrode opening 20b, and the first interlayer insulating layer 18 and the gate insulating layer 13 are simultaneously etched in the source opening 20c. . For example, CHF3 can be used as the etching gas. Subsequently, plasma treatment using CF4 gas is performed to clean the surfaces of the openings 20a, 20b and 20c.

(E) The aluminum layer is applied to the silicon substrate 11
After forming it on the main surface side of the
The wiring layers 21a, 21b and 21c are formed. Second
The wiring layer 21a is connected to the first wiring layer 19 through the first opening 18a and the second opening 20a.

By the way, in the step (D), the first wiring layer 19 formed in the second opening 20a may be entirely etched. At this time, the second wiring layer 21a is directly connected to the conductor layer 15 as shown in FIG. Therefore, the first wiring layer 19 and the second wiring layer 21a are connected to each other via the conductor layer 15, and the conduction failure occurs between the first wiring layer 19 and the second wiring layer 21a. Does not occur. Further, the structure shown in FIG. 2 has the following advantages. First
Depending on the combination of the wiring layer 19 and the second wiring layer 21a, the adhesion between them may be poor or the contact resistance may be high. In such a case, the conductor layer 15 and the If the combination with the second wiring layer 21a has good adhesiveness and low contact resistance, reliability and characteristics can be improved.

[0019]

According to the invention of the present application, the conductive layer is provided on the field insulating layer, the second opening is provided corresponding to the first opening, and the first opening and the second opening are provided. Since the second wiring layer is connected to the first wiring layer and / or the conductor layer, even if the first wiring layer is exposed to the etching substance for a long time during the formation of the second opening, the first wiring layer is exposed. Conduction can be reliably established between the layer and the second wiring layer, and reliability can be improved. Moreover, since the conductor layer is formed in the same step as the step of forming the gate electrode, the manufacturing process can be simplified.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process showing an embodiment of the present invention.

FIG. 2 is a sectional view showing another embodiment of the invention according to the present application.

FIG. 3 is a sectional view showing a conventional example.

[Explanation of symbols]

 11 semiconductor substrate 12 field insulating layer 14 gate electrode 15 conductor layer 18 first interlayer insulating layer 18a first opening 19 first wiring layer 20 second interlayer insulating layer 20a second opening 21a second Wiring layer

Claims (1)

[Claims] 1. A step of forming a conductor layer on a field insulating layer by the same step as the step of forming a gate electrode; and a step of forming a first interlayer insulating layer having a first opening on the conductor layer. A step of forming a first wiring layer connected to the conductor layer in the first opening on the first interlayer insulating layer, and a step of forming the first wiring layer on the first wiring layer. Second corresponding to the opening
Forming a second interlayer insulating layer having a first opening and a second opening through the first opening and the second opening.
A second layer connected to the wiring layer and / or the conductor layer
And a step of forming a wiring layer, the method for manufacturing a semiconductor device.