KR20060007173A - Method of forming a capacitor and a thin film resistor in a semiconductor device - Google Patents

Method of forming a capacitor and a thin film resistor in a semiconductor device Download PDF

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KR20060007173A
KR20060007173A KR1020040055931A KR20040055931A KR20060007173A KR 20060007173 A KR20060007173 A KR 20060007173A KR 1020040055931 A KR1020040055931 A KR 1020040055931A KR 20040055931 A KR20040055931 A KR 20040055931A KR 20060007173 A KR20060007173 A KR 20060007173A
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insulating film
capacitor
thin film
metal layer
metal
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조진연
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0676—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors
    • H01L27/0682—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type comprising combinations of diodes, or capacitors or resistors comprising combinations of capacitors and resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors

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Abstract

본 발명은 반도체 소자의 커패시터와 박막 저항 형성 방법에 관한 것으로, 하부 층간 절연막에는 듀얼 다마신 패턴이 형성되고 듀얼 다마신 패턴에는 비아 플러그와 하부 금속 배선이 형성된 상태에서, 전체 구조 상에 하부 절연막/금속층/상부 절연막으로 이루어진 적층막을 소정의 패턴으로 형성한 후, 하부 금속 배선 상에 형성된 적층막의 하부 절연막과 금속층은 커패시터의 유전체막과 상부 전극으로 각각 사용하고, 하부 층간 절연막 상에 형성된 층 적층막은 박막 저항을 형성하는데 사용함으로써, 커패시터와 박막 저항을 하나의 마스크로 동일한 층에 동시에 형성하여 공정 단계를 감소시키고 단차를 제거하여 공정을 단순화하고 공정의 재현성을 확보할 수 있다.
The present invention relates to a method of forming a capacitor and a thin film resistor of a semiconductor device, wherein a dual damascene pattern is formed on a lower interlayer insulating film, and a via plug and a lower metal wiring are formed on the dual damascene pattern. After the laminated film formed of the metal layer / upper insulating film was formed in a predetermined pattern, the lower insulating film and the metal layer of the laminated film formed on the lower metal wiring were respectively used as the dielectric film and the upper electrode of the capacitor, and the layer laminated film formed on the lower interlayer insulating film Used to form thin film resistors, capacitors and thin film resistors can be simultaneously formed on the same layer with one mask to reduce process steps and eliminate steps to simplify the process and ensure process reproducibility.

커패시터, 박막 저항, 단차, 마스크Capacitors, Thin Film Resistors, Steps, Masks

Description

반도체 소자의 커패시터와 박막 저항 형성 방법{Method of forming a capacitor and a thin film resistor in a semiconductor device} Method of forming a capacitor and a thin film resistor in a semiconductor device             

도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 박막 저항 형성 방법을 설명하기 위한 소자의 단면도들이다.1A to 1E are cross-sectional views of devices for describing a method of forming a thin film resistor of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 커패시터와 박막 저항 형성 방법을 설명하기 위한 소자의 단면도들이다.
2A to 2E are cross-sectional views of devices for describing a capacitor and a thin film resistor forming method of a semiconductor device according to an embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

101, 201 : 반도체 기판 102 : 제1 층간 절연막101, 201: semiconductor substrate 102: first interlayer insulating film

103 : 제1 금속층 104 : 절연막103: first metal layer 104: insulating film

105 : 제2 금속층 106 : 제2 층간 절연막105: second metal layer 106: second interlayer insulating film

107 : 금속 배선 202 : 하부 층간절연막107: metal wiring 202: lower interlayer insulating film

203 : 하부 금속배선 204 : 제1 절연막203: lower metal wiring 204: first insulating film

205 : 금속층 206 : 제2 절연막205 metal layer 206 second insulating film

207 : 제3 절연막 208 : 식각 정지막207: third insulating film 208: etch stop film

209 : 제4 절연막 210 : 비아홀 209: fourth insulating film 210: via hole                 

211 : 트렌치 C200 : 커패시터211: trench C200: capacitor

R200 : 박막 저항
R200: Thin Film Resistance

본 발명은 반도체 소자의 커패시터와 박막 저항 형성 방법에 관한 것으로, 특히 커패시터와 박막 저항을 형성함에 있어 단차를 최소화하고 공정 단계를 감소시킬 수 있는 반도체 소자의 커패시터와 박막 저항 형성 방법에 관한 것이다.
The present invention relates to a method of forming a capacitor and a thin film resistor of a semiconductor device, and more particularly, to a method of forming a capacitor and a thin film resistor of a semiconductor device capable of minimizing steps and reducing process steps in forming a capacitor and a thin film resistor.

높은 정밀도를 요구하는 CMOS IC 논리 소자에 적용되는 아나로그 커패시터는 개량된 아나로그 MOS 기술, 특히 A/D 컨버터나 switched-capacitor filter 분야의 핵심 요소이다. 이와 같은 커패시터의 구조로는 폴리실리콘 대 폴리실리콘, 폴리실리콘 대 실리콘, 금속 대 실리콘, 금속 대 폴리실리콘 및 금속 대 금속 등 다양한 커패시터 구조들이 사용되어 왔다. 이들 중 금속 대 금속(Metal to metal) 구조(MIM 구조)는 직렬 저항(Series resistance)이 낮아 높은 정전용량을 갖는 커패시터를 만들 수 있으며, 열부담(Thermal budget) 및 Vcc가 낮은 장점으로 인하여 현재 아나로그 커패시터 구조로 널리 이용되고 있다. 이러한 MIM 구조의 커패시터 제조 방법을 간략하게 설명하면 다음과 같다.Analog capacitors in high-precision CMOS IC logic devices are key elements in advanced analog MOS technology, particularly in A / D converters and switched-capacitor filters. As the structure of such a capacitor, various capacitor structures such as polysilicon to polysilicon, polysilicon to silicon, metal to silicon, metal to polysilicon, and metal to metal have been used. Among them, the metal-to-metal structure (MIM structure) has a low series resistance, which makes it possible to make a capacitor having a high capacitance, and is currently known due to its low thermal budget and low Vcc. It is widely used as a log capacitor structure. Brief description of the capacitor manufacturing method of such a MIM structure is as follows.

도 1a 내지 도 1e는 종래 기술에 따른 반도체 소자의 박막 저항 형성 방법을 설명하기 위한 소자의 단면도들이다.1A to 1E are cross-sectional views of devices for describing a method of forming a thin film resistor of a semiconductor device according to the prior art.

도 1a를 참조하면, 트랜지스터와 같이 반도체 소자를 형성하기 위한 여러 요소(도시되지 않음)가 형성된 반도체 기판(101) 상에 제1 층간 절연막(102)을 형성한 후, 제1 층간 절연막(102) 상에 제1 금속층(103), 절연막(104) 및 제2 금속층(105)을 순차적으로 형성한다. 여기서, 절연막(104)은 커패시터의 유전체막을 형성하기 위한 것이다. Referring to FIG. 1A, after forming a first interlayer insulating film 102 on a semiconductor substrate 101 on which various elements (not shown) for forming a semiconductor device, such as a transistor, are formed, a first interlayer insulating film 102 is formed. The first metal layer 103, the insulating film 104, and the second metal layer 105 are sequentially formed thereon. Here, the insulating film 104 is for forming a dielectric film of a capacitor.

도 1b를 참조하면, 제2 금속층(105) 및 절연막(104)을 패터닝한다. 여기서, 제2 금속층(105)은 커패시터의 상부 전극이 된다. Referring to FIG. 1B, the second metal layer 105 and the insulating film 104 are patterned. Here, the second metal layer 105 becomes an upper electrode of the capacitor.

도 1c를 참조하면, 제1 금속층(103)을 패터닝한다. 여기서, 제1 금속층(103)은 커패시터의 하부 전극이 된다. 이때, 제1 금속층(103)은 제2 금속층(105)보다 넓게 패터닝되어, 일부 영역이 노출되도록 한다. Referring to FIG. 1C, the first metal layer 103 is patterned. Here, the first metal layer 103 becomes a lower electrode of the capacitor. In this case, the first metal layer 103 is patterned to be wider than the second metal layer 105 to expose some regions.

도 1d를 참조하면, 제1 금속층(103)을 포함한 전체 구조 상에 제2 층간 절연막(106)을 형성한다. Referring to FIG. 1D, a second interlayer insulating layer 106 is formed on the entire structure including the first metal layer 103.

도 1e를 참조하면, 제1 금속층(103)과 제2 금속층(105)의 일부 영역이 노출되도록 제2 층간 절연막(106)에 비아홀을 형성한 후, 금속층을 형성하고 패터닝 공정을 실시하여 금속 배선(107)을 형성한다. Referring to FIG. 1E, after forming a via hole in the second interlayer insulating layer 106 to expose a portion of the first metal layer 103 and the second metal layer 105, a metal layer is formed and a patterning process is performed to form a metal wiring. 107 is formed.

상기에서 서술한 커패시터 구조의 경우 다음과 같은 공정상의 문제점을 가지고 있다. The capacitor structure described above has the following process problems.

첫째, 얇은 두께의 제2 금속층(105)을 균일하게 식각할 수 있어야 한다.First, it should be possible to uniformly etch the thin second metal layer 105.

둘째, 제2 금속층(105)의 균일하지 못한 두께를 고려하여, 비아홀 형성을 위 한 식각 공정 시 식각 종료 시점을 검출하는 것이 용이해야 한다. Second, in consideration of the non-uniform thickness of the second metal layer 105, it should be easy to detect the etching end point during the etching process for forming the via hole.

셋째, 절연막과 금속층의 식각 선택비를 크게 하여 제2 금속층(105) 식각 시 과도 식각에 대한 마진이 확보되어야 한다. Third, the etching selectivity between the insulating layer and the metal layer is increased to secure a margin for the excessive etching during the etching of the second metal layer 105.

이러한 공정상의 제한은 특정 소자 개발 시 상부 금속 전극이 패턴 밀도에 따라 비아홀 형성 시 식각 종료 시점이나 과도 식각 마진이 변하게 되므로 개발 주기가 길어지게 되며, 상부 금속 전극이 두꺼울 경우 단차가 증가하여 평탄화 측면에서 불리해진다. The limitation of this process is that the development time is longer because the upper metal electrode changes the etch termination point or the excessive etching margin when the via hole is formed according to the pattern density, and when the upper metal electrode is thick, the step is increased to planarize. Disadvantages.

한편, 아나로그 소자의 경우 MIM 구조 이외에 저항이나 인덕터와 같은 모듈이 함께 요구되는데, 이와 같은 모듈을 추가로 형성하기 위해서는 추가의 마스크 스텝이 필요하게 된다. In the analog device, a module such as a resistor or an inductor is required in addition to the MIM structure, and an additional mask step is required to form such a module.

종래의 기술들은 MIM 구조의 커패시터와 저항의 막 구조 차이로 인하여 서로 다른 레이어(layer)를 이용하는 것이 일반적이다. 이와 같이, 서로 다른 레이어를 이용할 경우 공정 스텝의 증가를 초래하여 생산 단가가 증가한다는 단점을 가지고 있다.
Conventional techniques generally use different layers due to differences in the film structure of the capacitor and the resistor of the MIM structure. As such, when different layers are used, production costs increase due to an increase in process steps.

이에 대하여, 본 발명이 제시하는 반도체 소자의 커패시터와 박막 저항 형성 방법은 하부 층간 절연막에는 듀얼 다마신 패턴이 형성되고 듀얼 다마신 패턴에는 비아 플러그와 하부 금속 배선이 형성된 상태에서, 전체 구조 상에 하부 절연막/금속층/상부 절연막으로 이루어진 적층막을 소정의 패턴으로 형성한 후, 하부 금속 배선 상에 형성된 적층막의 하부 절연막과 금속층은 커패시터의 유전체막과 상부 전극으로 각각 사용하고, 하부 층간 절연막 상에 형성된 층 적층막은 박막 저항을 형성하는데 사용함으로써, 커패시터와 박막 저항을 하나의 마스크로 동일한 층에 동시에 형성하여 공정 단계를 감소시키고 단차를 제거하여 공정을 단순화하고 공정의 재현성을 확보할 수 있다.
On the other hand, in the method of forming a capacitor and a thin film resistor of the semiconductor device according to the present invention, a dual damascene pattern is formed on the lower interlayer insulating layer, and a via plug and a lower metal wiring are formed on the dual damascene pattern. After the laminated film made of the insulating film / metal layer / upper insulating film was formed in a predetermined pattern, the lower insulating film and the metal layer of the laminated film formed on the lower metal wiring were respectively used as the dielectric film and the upper electrode of the capacitor, and the layer formed on the lower interlayer insulating film. By using the laminated film to form a thin film resistor, the capacitor and the thin film resistor can be simultaneously formed on the same layer with one mask to reduce the process step and eliminate the step, thereby simplifying the process and ensuring the reproducibility of the process.

본 발명의 실시예에 따른 반도체 소자의 커패시터와 박막 저항 형성 방법은 커패시터 영역과 금속배선 영역에는 금속 배선이 형성되고, 박막저항 영역을 포함한 그 외의 영역에는 층간절연막이 형성된 반도체 기판이 제공되는 단계와, 금속 배선을 포함한 전체 구조 상에 제1 절연막, 금속층 및 제2 절연막을 순차적으로 형성하는 단계, 및 커패시터 영역의 일부와 박막 저항 영역에만 잔류되도록 제2 절연막 및 금속층을 식각하여, 커패시터 영역에는 금속 배선, 제1 절연막 및 금속층으로 이루어진 커패시터를 형성하고, 박막저항 영역에는 금속층으로 이루어진 박막 저항을 형성하는 단계를 포함한다. According to an embodiment of the present invention, a method of forming a capacitor and a thin film resistor of a semiconductor device may include providing a semiconductor substrate on which a metal wiring is formed in the capacitor region and the metal wiring region, and an interlayer insulating film is formed in other regions including the thin film resistance region; And sequentially forming the first insulating film, the metal layer, and the second insulating film on the entire structure including the metal wiring, and etching the second insulating film and the metal layer so that only a portion of the capacitor region and the thin film resistance region remain. And forming a capacitor including a wiring, a first insulating film, and a metal layer, and forming a thin film resistor including a metal layer in the thin film resistance region.

상기에서, 층간 절연막에는 다마신 패턴이 형성되며, 금속 배선은 다마신 패턴 내부에 형성되어, 평탄화된 상태에서 제1 절연막이 형성된다. In the above, the damascene pattern is formed in the interlayer insulating film, and the metal wiring is formed inside the damascene pattern, so that the first insulating film is formed in the planarized state.

한편, 제1 절연막이나 제2 절연막은 질화물로 형성하고, 금속층은 TiN 또는 TaNx로 형성할 수 있다. The first insulating film and the second insulating film may be formed of nitride, and the metal layer may be formed of TiN or TaNx.

커패시터의 하부 금속 배선 및 금속층 상부와, 박막 저항 상부의 소정 영역 상에 플러그가 형성되어 커패시터와 박막 저항이 주변 소자들과 전기적으로 연결된다.
A plug is formed on the lower metal wiring and the upper metal layer of the capacitor and a predetermined area above the thin film resistor to electrically connect the capacitor and the thin film resistor to the peripheral devices.

이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 설명하기로 한다. 그러나, 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 본 발명의 범위가 다음에 상술하는 실시예에 한정되는 것은 아니다. 단지 본 실시예는 본 발명의 개시가 완전하도록 하며 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명의 범위는 본원의 특허 청구 범위에 의해서 이해되어야 한다. Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

한편, 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다라고 기재되는 경우에 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제3의 막이 개재되어질 수도 있다. 또한 도면에서 각 층의 두께나 크기는 설명의 편의 및 명확성을 위하여 과장되었다. 도면 상에서 동일 부호는 동일한 요소를 지칭한다.On the other hand, when a film is described as being "on" another film or semiconductor substrate, the film may exist in direct contact with the other film or semiconductor substrate, or a third film may be interposed therebetween. In the drawings, the thickness or size of each layer is exaggerated for clarity and convenience of explanation. Like numbers refer to like elements on the drawings.

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체 소자의 커패시터와 박막 저항 형성 방법을 설명하기 위한 소자의 단면도들이다.2A to 2E are cross-sectional views of devices for describing a capacitor and a thin film resistor forming method of a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 반도체 소자를 형성하기 위한 여러 요소(도시되지 않음)가 형성된 반도체 기판(201)이 제공된다. 예를 들면, 반도체 기판(201)에는 트랜지스터(도시되지 않음)와 같은 요소들이 형성될 수 있다. 이어서, 반도체 기판(201) 상에 하부 층간 절연막(202)을 형성한 후, 듀얼 다마신 공정으로 하부 층간 절연막 (202)에 콘택홀(도시되지 않음)과 트렌치로 이루어진 듀얼 다마신 패턴을 형성하고, 듀얼 다마신 패턴을 전도성 물질로 매립하여 하부 금속 배선(203)을 형성한다. 이때, 하부 금속 배선(203)은 구리로 형성할 수 있다. 한편, 하부 금속 배선(203)의 금속 성분이 하부 층간 절연막(202)으로 확산되는 것을 방지하기 위하여 하부 금속 배선(203)과 하부 층간 절연막(202) 사이에 장벽 금속층(도시되지 않음)을 형성할 수도 있다. Referring to FIG. 2A, a semiconductor substrate 201 is provided in which various elements (not shown) are formed for forming a semiconductor device. For example, elements such as transistors (not shown) may be formed in the semiconductor substrate 201. Subsequently, after forming the lower interlayer insulating film 202 on the semiconductor substrate 201, a dual damascene pattern formed of a contact hole (not shown) and a trench is formed in the lower interlayer insulating film 202 by a dual damascene process. The dual damascene pattern is embedded with a conductive material to form the lower metal interconnection 203. In this case, the lower metal wiring 203 may be formed of copper. Meanwhile, a barrier metal layer (not shown) may be formed between the lower metal interconnection 203 and the lower interlayer insulation layer 202 to prevent the metal component of the lower metal interconnection 203 from diffusing into the lower interlayer insulation layer 202. It may be.

계속해서, 하부 금속 배선(203)을 포함한 전체 구조 상에 제1 절연막(204), 금속층(205) 및 제2 절연막(206)을 순차적으로 형성한다. 여기서, 제1 절연막(204) 또는 제2 절연막(206)은 질화막으로 형성하는 것이 바람직하며, 금속층(205)은 TiN이나 TaNx로 형성할 수 있다. Subsequently, the first insulating film 204, the metal layer 205, and the second insulating film 206 are sequentially formed on the entire structure including the lower metal wiring 203. The first insulating film 204 or the second insulating film 206 may be formed of a nitride film, and the metal layer 205 may be formed of TiN or TaNx.

한편, 제1 절연막(204)은 커패시터를 형성하는 경우 유전체막으로 사용되며, 그 외에는 식각 정지막이나 단순하게 절연막으로 사용될 수 있다. 그리고, 금속층(205)은 커패시터를 형성하는 경우 상부 전극으로 사용되며, 그 하부에 형성된 하부 금속 배선(203)은 커패시터의 하부 전극으로 사용된다. 그 외에는 금속층(205)이 박막 저항이 된다. 또한, 제2 절연막(206)은 식각 정지막으로 사용된다. On the other hand, the first insulating film 204 is used as a dielectric film when forming a capacitor, otherwise it may be used as an etch stop film or simply an insulating film. When the capacitor is formed, the metal layer 205 is used as an upper electrode, and the lower metal wire 203 formed under the capacitor is used as a lower electrode of the capacitor. Otherwise, the metal layer 205 becomes a thin film resistor. In addition, the second insulating film 206 is used as an etch stop film.

도 2b를 참조하면, 커패시터와 박막 저항이 형성될 영역이 함께 정의된 식각 마스크를 사용하여 제2 절연막(206) 및 금속층(205)을 순차적으로 패터닝한다. 패터닝 공정을 통해, 제2 절연막(206) 및 금속층(205)은 커패시터가 형성될 영역과 박막 저항이 형성될 영역에만 잔류된다. 즉, 커패시터가 형성될 영역에서는 제2 절연막(206) 및 금속층(205)이 하부 금속 배선(203) 상에 잔류되며, 박막 저항이 형 성될 영역에는 제2 절연막(206) 및 금속층(205)이 하부 층간 절연막(202) 상에 잔류된다. 이때, 커패시터가 형성될 영역에서는, 후속 공정에서 하부 금속 배선(203) 상에 플러그가 형성하기 위하여, 제2 절연막(206) 및 금속층(205)이 하부 금속 배선(203)의 일부 영역 상에만 잔류되도록 패터닝된다. 일반 배선이 형성되는 영역에서는 하부 금속 배선(203) 상의 제2 절연막(206) 및 금속층(205)이 모두 제거된다. Referring to FIG. 2B, the second insulating layer 206 and the metal layer 205 are sequentially patterned using an etching mask in which a capacitor and a region in which the thin film resistor is to be formed are defined together. Through the patterning process, the second insulating layer 206 and the metal layer 205 remain only in the region where the capacitor is to be formed and the region where the thin film resistor is to be formed. That is, in the region where the capacitor is to be formed, the second insulating layer 206 and the metal layer 205 remain on the lower metal wiring 203, and in the region where the thin film resistance is to be formed, the second insulating layer 206 and the metal layer 205 are formed. It remains on the lower interlayer insulating film 202. At this time, in the region where the capacitor is to be formed, the second insulating film 206 and the metal layer 205 remain only on a part of the lower metal wiring 203 in order to form a plug on the lower metal wiring 203 in a subsequent process. Patterned as possible. In the region where the general wiring is formed, both the second insulating film 206 and the metal layer 205 on the lower metal wiring 203 are removed.

한편, 제1 절연막(204)은 패터닝되지 않고 전체 구조 상에 잔류된다.On the other hand, the first insulating film 204 remains on the entire structure without being patterned.

이로써, 사실상 커패시터(C200)와 박막 저항(R200)이 동일한 층에 한번의 패터닝 공정으로 동시에 형성된다. As a result, the capacitor C200 and the thin film resistor R200 are simultaneously formed in the same layer in one patterning process.

이하, 커패시터(C200)와 박막 저항(R200)에 배선을 형성하는 공정을 설명하기로 한다. Hereinafter, a process of forming wirings in the capacitor C200 and the thin film resistor R200 will be described.

도 2c를 참조하면, 전체 구조 상에 제3 절연막(207), 식각 정지막(208) 및 제4 절연막(209)을 순차적으로 형성한다. 여기서, 제3 절연막(207) 및 제4 절연막(209)은 산화물로 형성되며, 이들 적층막은 상부 층간 절연막이 된다. Referring to FIG. 2C, the third insulating layer 207, the etch stop layer 208, and the fourth insulating layer 209 are sequentially formed on the entire structure. Here, the third insulating film 207 and the fourth insulating film 209 are formed of an oxide, and these laminated films become upper interlayer insulating films.

도 2d를 참조하면, 식각 공정으로 제4 절연막(209), 식각 정지막(208) 및 제3 절연막(207)을 순차적으로 식각하여 하부 금속 배선(203)과 금속층(205) 상부의 소정 영역에 비아홀(210)을 형성한다. 이때, 제2 절연막(206)이 잔류하는 영역에서는 제2 절연막(206)을 식각 정지막으로 사용하고, 제1 절연막(204)만 잔류하는 영역에서는 제1 절연막(204)을 식각 정지막으로 사용하여 식각 공정의 식각 종료 시점을 설정한다. 즉, 제1 절연막(204)이나 제2 절연막(206)은 제3 절연막(207)과 식각 선택비가 다른 물질(예를 들면, 질화막)으로 형성되므로, 식각 공정 시 이들 물 질이 검출되면 식각 공정을 중지하는 방식으로 식각 공정을 실시할 수 있다. Referring to FIG. 2D, the fourth insulating layer 209, the etch stop layer 208, and the third insulating layer 207 are sequentially etched through an etching process, and then formed on the lower metal interconnection 203 and the upper portion of the metal layer 205. The via hole 210 is formed. In this case, the second insulating film 206 is used as the etch stop film in the region where the second insulating film 206 remains, and the first insulating film 204 is used as the etch stop film in the region where only the first insulating film 204 remains. To set an etching end time of the etching process. That is, since the first insulating film 204 or the second insulating film 206 is formed of a material having a different etching selectivity from the third insulating film 207 (for example, a nitride film), when these materials are detected during the etching process, the etching process is performed. The etching process may be carried out in such a manner as to stop.

이로써, 커패시터가 형성될 영역에서는 비아홀(210)을 통해 제1 절연막(204)과 제2 절연막(206)이 각각 노출되고, 박막저항이 형성될 영역에는 제2 절연막(206)만이 노출되며, 금속배선이 형성될 영역에서는 제2 절연막(206)만이 노출된다. Accordingly, the first insulating layer 204 and the second insulating layer 206 are exposed through the via hole 210 in the region where the capacitor is to be formed, and only the second insulating layer 206 is exposed in the region where the thin film resistor is to be formed. Only the second insulating film 206 is exposed in the region where the wiring is to be formed.

도 2e를 참조하면, 트렌치 마스크를 이용한 식각 공정으로 제3 절연막(207)의 소정 영역을 식각하여 트렌치(211)를 형성한다. 트렌치(211)를 형성하기 위한 식각 공정 시 제3 절연막(207)은 식각 정지막(208)에 의해 식각되지 않고 비아홀(210)이 형성된 형태를 그대로 유지한다. 이로써, 상부 층간 절연막에 비아홀(210) 및 트렌치(211)로 이루어진 듀얼 다마신 패턴이 형성된다. Referring to FIG. 2E, a trench 211 is formed by etching a predetermined region of the third insulating layer 207 by an etching process using a trench mask. In the etching process for forming the trench 211, the third insulating layer 207 is not etched by the etch stop layer 208 and maintains the form in which the via hole 210 is formed. As a result, a dual damascene pattern formed of the via hole 210 and the trench 211 is formed in the upper interlayer insulating layer.

이후, 도면에는 도시되어 있지 않지만, 듀얼 다마신 패턴을 금속 물질로 매립하여 비아 플러그와 상부 금속 배선을 동시에 형성한다. 이로써, 커패시터(C200)와 박막 저항(R200)이 주변 소자들과 전기적으로 연결된다.
Thereafter, although not shown in the drawing, the dual damascene pattern is embedded with a metal material to simultaneously form the via plug and the upper metal wiring. As a result, the capacitor C200 and the thin film resistor R200 are electrically connected to the peripheral devices.

상술한 바와 같이, 본 발명은 하부 층간 절연막에는 듀얼 다마신 패턴이 형성되고 듀얼 다마신 패턴에는 비아 플러그와 하부 금속 배선이 형성된 상태에서, 전체 구조 상에 하부 절연막/금속층/상부 절연막으로 이루어진 적층막을 소정의 패턴으로 형성한 후, 하부 금속 배선 상에 형성된 적층막의 하부 절연막과 금속층은 커패시터의 유전체막과 상부 전극으로 각각 사용하고, 하부 층간 절연막 상에 형성 된 층 적층막은 박막 저항을 형성하는데 사용함으로써, 커패시터와 박막 저항을 하나의 마스크로 동일한 층에 동시에 형성하여 공정 단계를 감소시키고 단차를 제거하여 공정을 단순화하고 공정의 재현성을 확보할 수 있다.As described above, in the present invention, a dual damascene pattern is formed on the lower interlayer insulating film, and a via plug and a lower metal wiring are formed on the dual damascene pattern. After forming in a predetermined pattern, the lower insulating film and the metal layer of the laminated film formed on the lower metal wiring are respectively used as the dielectric film and the upper electrode of the capacitor, and the layer laminated film formed on the lower interlayer insulating film is used to form the thin film resistance. In addition, capacitors and thin film resistors can be simultaneously formed on the same layer with one mask to reduce process steps and eliminate steps to simplify the process and ensure process reproducibility.

Claims (5)

커패시터 영역과 금속배선 영역에는 금속 배선이 형성되고, 박막저항 영역을 포함한 그 외의 영역에는 층간절연막이 형성된 반도체 기판이 제공되는 단계;Providing a semiconductor substrate having a metal wiring formed in the capacitor region and the metal wiring region, and an interlayer insulating film formed in other regions including the thin film resistance region; 상기 금속 배선을 포함한 전체 구조 상에 제1 절연막, 금속층 및 제2 절연막을 순차적으로 형성하는 단계; 및 Sequentially forming a first insulating film, a metal layer, and a second insulating film on the entire structure including the metal wires; And 상기 커패시터 영역의 일부와 상기 박막 저항 영역에만 잔류되도록 상기 제2 절연막 및 상기 금속층을 식각하여, 상기 커패시터 영역에는 상기 금속 배선, 상기 제1 절연막 및 상기 금속층으로 이루어진 커패시터를 형성하고, 상기 박막저항 영역에는 상기 금속층으로 이루어진 박막 저항을 형성하는 단계를 포함하는 반도체 소자의 커패시터와 박막 저항 형성 방법.The second insulating film and the metal layer are etched so as to remain only in a portion of the capacitor area and the thin film resistance area, and a capacitor including the metal wire, the first insulating film, and the metal layer is formed in the capacitor area, and the thin film resistance area. And forming a thin film resistor formed of the metal layer. 제 1 항에 있어서,The method of claim 1, 상기 층간 절연막에는 다마신 패턴이 형성되며, 상기 금속 배선은 상기 다마신 패턴 내부에 형성되어, 평탄화된 상태에서 상기 제1 절연막이 형성되는 반도체 소자의 커패시터와 박막 저항 형성 방법.The damascene pattern is formed on the interlayer insulating film, and the metal wiring is formed inside the damascene pattern, wherein the first insulating film is formed in the planarized state. 제 1 항에 있어서,The method of claim 1, 상기 제1 절연막 또는 상기 제2 절연막이 질화물로 형성되는 반도체 소자의 커패시터와 박막 저항 형성 방법.The method of claim 1, wherein the first insulating film or the second insulating film is formed of nitride. 제 1 항에 있어서,The method of claim 1, 상기 금속층이 TiN 또는 TaNx로 형성되는 반도체 소자의 커패시터와 박막 저항 형성 방법.The method of claim 1, wherein the metal layer is formed of TiN or TaNx. 제 1 항에 있어서, The method of claim 1, 상기 커패시터의 상기 하부 금속 배선 및 상기 금속층 상부와, 상기 박막 저항 상부의 소정 영역 상에 플러그가 형성되어 상기 커패시터와 상기 박막 저항이 주변 소자들과 전기적으로 연결되는 반도체 소자의 커패시터와 박막 저항 형성 방법.A method of forming a capacitor and a thin film resistor of a semiconductor device in which a plug is formed on the lower metal wiring and the metal layer of the capacitor, and a predetermined region above the thin film resistor to electrically connect the capacitor and the thin film resistor to peripheral devices. .
KR1020040055931A 2004-07-19 2004-07-19 Method of forming a capacitor and a thin film resistor in a semiconductor device KR20060007173A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786356A (en) * 2017-11-13 2019-05-21 台湾积体电路制造股份有限公司 Device including MIM capacitor and resistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109786356A (en) * 2017-11-13 2019-05-21 台湾积体电路制造股份有限公司 Device including MIM capacitor and resistor

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