JPS53109437A - Address and break signal generator - Google Patents

Address and break signal generator

Info

Publication number
JPS53109437A
JPS53109437A JP2271778A JP2271778A JPS53109437A JP S53109437 A JPS53109437 A JP S53109437A JP 2271778 A JP2271778 A JP 2271778A JP 2271778 A JP2271778 A JP 2271778A JP S53109437 A JPS53109437 A JP S53109437A
Authority
JP
Japan
Prior art keywords
address
signal generator
break signal
break
generator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2271778A
Other languages
English (en)
Inventor
Kennesu Berugu Ooke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of JPS53109437A publication Critical patent/JPS53109437A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
    • G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Hardware Redundancy (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Manufacturing Of Electric Cables (AREA)
  • Computer And Data Communications (AREA)
  • Storage Device Security (AREA)
JP2271778A 1977-03-01 1978-02-28 Address and break signal generator Pending JPS53109437A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE7702263A SE399773B (sv) 1977-03-01 1977-03-01 Adress- och avbrottsignalgenerator

Publications (1)

Publication Number Publication Date
JPS53109437A true JPS53109437A (en) 1978-09-25

Family

ID=20330590

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2271778A Pending JPS53109437A (en) 1977-03-01 1978-02-28 Address and break signal generator

Country Status (24)

Country Link
US (1) US4208713A (ja)
JP (1) JPS53109437A (ja)
AU (1) AU517304B2 (ja)
BE (1) BE864150A (ja)
BR (1) BR7801210A (ja)
CA (1) CA1099363A (ja)
CH (1) CH626484A5 (ja)
DD (1) DD134177A5 (ja)
DE (1) DE2807175C2 (ja)
DK (1) DK91478A (ja)
EG (1) EG13276A (ja)
ES (1) ES467392A1 (ja)
FI (1) FI63499C (ja)
FR (1) FR2382719B1 (ja)
GB (1) GB1575868A (ja)
HU (1) HU176778B (ja)
IN (1) IN148500B (ja)
IT (1) IT1092895B (ja)
MX (1) MX143953A (ja)
NL (1) NL7802066A (ja)
NO (1) NO146006C (ja)
PL (1) PL113598B1 (ja)
SE (1) SE399773B (ja)
YU (1) YU45378A (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6237750A (ja) * 1985-08-12 1987-02-18 Matsushita Electric Ind Co Ltd アドレス発生回路
JPS6361325A (ja) * 1986-09-02 1988-03-17 Canon Inc デ−タ入出力メモリ
JPS6361324A (ja) * 1986-09-02 1988-03-17 Canon Inc デ−タ入出力メモリ
JPS6429926A (en) * 1987-07-24 1989-01-31 Matsushita Electric Ind Co Ltd Fifo circuit
JPH0421123A (ja) * 1990-05-16 1992-01-24 Nec Commun Syst Ltd Ｆｉｆｏレジスタ
JPH05197520A (ja) * 1992-01-22 1993-08-06 Japan Radio Co Ltd Ｆｉｆｏメモリ

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0012497B1 (en) * 1978-09-29 1984-11-28 The Marconi Company Limited Apparatus and method using a memory for processing television picture signals and other information
CA1143856A (en) * 1979-09-26 1983-03-29 Anthony K. Fung Circular-queue structure
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
DE3118621A1 (de) * 1981-05-11 1982-11-25 Siemens AG, 1000 Berlin und 8000 München Anordnung zum auslesen eindeutiger informationen aus einem digitalen schaltwerk bei zueinander asynchronen steuersignalen fuer das weiterschalten des schaltwerks und das uebernehmen der informationen
US4433391A (en) * 1981-08-17 1984-02-21 Burroughs Corporation Buffered handshake bus with transmission and response counters for avoiding receiver overflow
DE3203070C2 (de) * 1982-01-30 1984-01-05 Standard Elektrik Lorenz Ag, 7000 Stuttgart Schaltungsanordnung zum Steuern von Anlagen im Echtzeitbetrieb, insbesondere von Fernmeldevermittlungsanlagen
DE3213345C2 (de) * 1982-04-08 1984-11-22 Siemens Ag, 1000 Berlin Und 8000 Muenchen Datenübertragungseinrichtung zwischen zwei asynchron gesteuerten Datenverarbeitungssystemen
DE3305693A1 (de) * 1983-02-18 1984-08-30 Nixdorf Computer Ag Schaltungsanordnung zur zwischenspeicherung von befehlsworten
DE3431785A1 (de) * 1984-08-29 1986-03-13 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung fuer einen nach dem warteschlangenprinzip arbeitenden steuerspeicher (fifo-speicher)
US5179692A (en) * 1985-08-07 1993-01-12 Seiko Epson Corporation Emulation device for driving a LCD with signals formatted for a CRT display
JPH084340B2 (ja) * 1985-08-07 1996-01-17 セイコーエプソン株式会社 インタ−フエイス装置
US4860246A (en) * 1985-08-07 1989-08-22 Seiko Epson Corporation Emulation device for driving a LCD with a CRT display
US4717950A (en) * 1985-10-17 1988-01-05 Ampex Corporation Signal phase control by memory cycle read/write groups unlock
DE68926833T2 (de) * 1988-05-09 1997-02-20 Sgs Thomson Microelectronics Flagge für einen FIFO
JPH0237422A (ja) * 1988-07-28 1990-02-07 Oki Electric Ind Co Ltd 数値管理方式
US5206817A (en) * 1989-03-31 1993-04-27 Sgs-Thomson Microelectronics, Inc. Pipelined circuitry for allowing the comparison of the relative difference between two asynchronous pointers and a programmable value
US4994830A (en) * 1990-01-22 1991-02-19 Eastman Kodak Company Tele pan camera data back shifts and reduces printed data with changes in mode
GB9111524D0 (en) * 1991-05-29 1991-07-17 Hewlett Packard Co Data storage method and apparatus
US5682554A (en) * 1993-01-15 1997-10-28 Silicon Graphics, Inc. Apparatus and method for handling data transfer between a general purpose computer and a cooperating processor
IES65387B2 (en) * 1995-03-24 1995-10-18 Lake Res Ltd Communication apparatus for communicating two microprocessors

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2907004A (en) * 1954-10-29 1959-09-29 Rca Corp Serial memory
DE1247050B (de) * 1964-11-25 1967-08-10 Telefunken Patent Einrichtung mit einem Pufferspeicher zur Weitergabe unregelmaessig anfallender Digitaldaten in gleichmaessigen Zeitabstaenden
GB1195899A (en) * 1967-11-21 1970-06-24 Mini Of Technology Improvements in or relating to Synchronising Arrangements in Digital Communications Systems.
US3566363A (en) * 1968-07-11 1971-02-23 Ibm Processor to processor communication in a multiprocessor computer system
NL7011048A (ja) * 1970-07-25 1972-01-27
US3699529A (en) * 1971-01-07 1972-10-17 Rca Corp Communication among computers
US3715729A (en) * 1971-03-10 1973-02-06 Ibm Timing control for a multiprocessor system
US3988716A (en) * 1974-08-05 1976-10-26 Nasa Computer interface system
DE2610428C3 (de) * 1976-03-12 1980-06-19 Siemens Ag, 1000 Berlin Und 8000 Muenchen Anordnung zur Steuerung der Zwischenspeicherung von zwischen zwei Funktionseinheiten zu übertragenden Daten in einem Pufferspeicher

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6237750A (ja) * 1985-08-12 1987-02-18 Matsushita Electric Ind Co Ltd アドレス発生回路
JPS6361325A (ja) * 1986-09-02 1988-03-17 Canon Inc デ−タ入出力メモリ
JPS6361324A (ja) * 1986-09-02 1988-03-17 Canon Inc デ−タ入出力メモリ
JPS6429926A (en) * 1987-07-24 1989-01-31 Matsushita Electric Ind Co Ltd Fifo circuit
JPH0421123A (ja) * 1990-05-16 1992-01-24 Nec Commun Syst Ltd Ｆｉｆｏレジスタ
JPH05197520A (ja) * 1992-01-22 1993-08-06 Japan Radio Co Ltd Ｆｉｆｏメモリ

Also Published As

Publication number Publication date
AU517304B2 (en) 1981-07-23
CA1099363A (en) 1981-04-14
IT1092895B (it) 1985-07-12
CH626484A5 (ja) 1981-11-13
US4208713A (en) 1980-06-17
DE2807175C2 (de) 1985-07-11
YU45378A (en) 1982-06-30
DE2807175A1 (de) 1978-09-07
FI780564A (fi) 1978-09-02
IN148500B (ja) 1981-03-14
BR7801210A (pt) 1978-10-31
AU3350978A (en) 1979-08-30
ES467392A1 (es) 1978-11-01
BE864150A (fr) 1978-06-16
FR2382719A1 (fr) 1978-09-29
FI63499B (fi) 1983-02-28
HU176778B (en) 1981-05-28
PL113598B1 (en) 1980-12-31
NO146006C (no) 1982-07-21
GB1575868A (en) 1980-10-01
DD134177A5 (de) 1979-02-07
NL7802066A (nl) 1978-09-05
SE399773B (sv) 1978-02-27
NO780697L (no) 1978-09-04
FI63499C (fi) 1983-06-10
IT7820782A0 (it) 1978-03-01
FR2382719B1 (fr) 1985-11-15
PL204965A1 (pl) 1978-12-18
NO146006B (no) 1982-03-29
DK91478A (da) 1978-09-02
EG13276A (en) 1980-12-31
MX143953A (es) 1981-08-05

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