JPS5258376A - Etching for flattening of semiconductor surface - Google Patents

Etching for flattening of semiconductor surface

Info

Publication number
JPS5258376A
JPS5258376A JP13403675A JP13403675A JPS5258376A JP S5258376 A JPS5258376 A JP S5258376A JP 13403675 A JP13403675 A JP 13403675A JP 13403675 A JP13403675 A JP 13403675A JP S5258376 A JPS5258376 A JP S5258376A
Authority
JP
Japan
Prior art keywords
etching
flattening
semiconductor surface
serration
flatten
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13403675A
Other languages
English (en)
Japanese (ja)
Inventor
Kaoru Niino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13403675A priority Critical patent/JPS5258376A/ja
Priority to DE19762651125 priority patent/DE2651125A1/de
Priority to NL7612499A priority patent/NL7612499A/xx
Publication of JPS5258376A publication Critical patent/JPS5258376A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
JP13403675A 1975-11-10 1975-11-10 Etching for flattening of semiconductor surface Pending JPS5258376A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP13403675A JPS5258376A (en) 1975-11-10 1975-11-10 Etching for flattening of semiconductor surface
DE19762651125 DE2651125A1 (de) 1975-11-10 1976-11-09 Verfahren zum flachaetzen der oberflaeche von halbleitern
NL7612499A NL7612499A (nl) 1975-11-10 1976-11-10 Werkwijze voor het vlak etsen van het opper- vlak van een halfgeleider.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13403675A JPS5258376A (en) 1975-11-10 1975-11-10 Etching for flattening of semiconductor surface

Publications (1)

Publication Number Publication Date
JPS5258376A true JPS5258376A (en) 1977-05-13

Family

ID=15118859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13403675A Pending JPS5258376A (en) 1975-11-10 1975-11-10 Etching for flattening of semiconductor surface

Country Status (3)

Country Link
JP (1) JPS5258376A (de)
DE (1) DE2651125A1 (de)
NL (1) NL7612499A (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0286855A1 (de) * 1987-04-15 1988-10-19 BBC Brown Boveri AG Verfahren zum Aetzen von Vertiefungen in ein Siliziumsubstrat

Also Published As

Publication number Publication date
NL7612499A (nl) 1977-05-12
DE2651125A1 (de) 1977-05-18

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