JPS52151575A - Semiconductor i2l circuit and method of producing same - Google Patents
Semiconductor i2l circuit and method of producing sameInfo
- Publication number
- JPS52151575A JPS52151575A JP4192677A JP4192677A JPS52151575A JP S52151575 A JPS52151575 A JP S52151575A JP 4192677 A JP4192677 A JP 4192677A JP 4192677 A JP4192677 A JP 4192677A JP S52151575 A JPS52151575 A JP S52151575A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- circuit
- producing same
- producing
- same
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US67602376A | 1976-04-12 | 1976-04-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS52151575A true JPS52151575A (en) | 1977-12-16 |
JPS6228577B2 JPS6228577B2 (ja) | 1987-06-22 |
Family
ID=24712903
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4192677A Granted JPS52151575A (en) | 1976-04-12 | 1977-04-12 | Semiconductor i2l circuit and method of producing same |
Country Status (3)
Country | Link |
---|---|
US (1) | US4137109A (ja) |
JP (1) | JPS52151575A (ja) |
DE (1) | DE2716123C2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61263150A (ja) * | 1986-01-10 | 1986-11-21 | Toshiba Corp | 半導体装置の製造方法 |
JPS6323335A (ja) * | 1985-09-25 | 1988-01-30 | モノリシツク メモリ−ズ,インコ−ポレイテツド | 半導体装置及びその製造方法 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4268847A (en) * | 1977-09-16 | 1981-05-19 | Nippon Electric Co., Ltd. | Semiconductor device having an insulated gate type field effect transistor and method for producing the same |
US4140558A (en) * | 1978-03-02 | 1979-02-20 | Bell Telephone Laboratories, Incorporated | Isolation of integrated circuits utilizing selective etching and diffusion |
DE2816949C3 (de) * | 1978-04-19 | 1981-07-16 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte Halbleiteranordnung und deren Verwendung zum Aufbau einer Speicheranordnung |
JPS55153342A (en) * | 1979-05-18 | 1980-11-29 | Fujitsu Ltd | Semiconductor device and its manufacture |
EP0051488B1 (en) * | 1980-11-06 | 1985-01-30 | Kabushiki Kaisha Toshiba | Method for manufacturing a semiconductor device |
US4390802A (en) * | 1980-12-22 | 1983-06-28 | Motorola, Inc. | Low-voltage, high-noise immunity I2 L interface |
US4373965A (en) * | 1980-12-22 | 1983-02-15 | Ncr Corporation | Suppression of parasitic sidewall transistors in locos structures |
EP0093304B1 (en) * | 1982-04-19 | 1986-01-15 | Matsushita Electric Industrial Co., Ltd. | Semiconductor ic and method of making the same |
US4546539A (en) * | 1982-12-08 | 1985-10-15 | Harris Corporation | I2 L Structure and fabrication process compatible with high voltage bipolar transistors |
SE433787B (sv) * | 1983-07-15 | 1984-06-12 | Ericsson Telefon Ab L M | Multipel transistor med gemensam emitter och sparata kollektorer |
US4547793A (en) * | 1983-12-27 | 1985-10-15 | International Business Machines Corporation | Trench-defined semiconductor structure |
US4556585A (en) * | 1985-01-28 | 1985-12-03 | International Business Machines Corporation | Vertically isolated complementary transistors |
US4824797A (en) * | 1985-10-31 | 1989-04-25 | International Business Machines Corporation | Self-aligned channel stop |
US5021856A (en) * | 1989-03-15 | 1991-06-04 | Plessey Overseas Limited | Universal cell for bipolar NPN and PNP transistors and resistive elements |
US5206182A (en) * | 1989-06-08 | 1993-04-27 | United Technologies Corporation | Trench isolation process |
US5248894A (en) * | 1989-10-03 | 1993-09-28 | Harris Corporation | Self-aligned channel stop for trench-isolated island |
US5270256A (en) * | 1991-11-27 | 1993-12-14 | Intel Corporation | Method of forming a guard wall to reduce delamination effects |
US5341011A (en) * | 1993-03-15 | 1994-08-23 | Siliconix Incorporated | Short channel trenched DMOS transistor |
US5539233A (en) * | 1993-07-22 | 1996-07-23 | Texas Instruments Incorporated | Controlled low collector breakdown voltage vertical transistor for ESD protection circuits |
US5859450A (en) * | 1997-09-30 | 1999-01-12 | Intel Corporation | Dark current reducing guard ring |
KR100253372B1 (ko) | 1997-12-08 | 2000-04-15 | 김영환 | 반도체 소자 및 그 제조방법 |
DE102012018611B3 (de) * | 2012-09-20 | 2013-10-24 | Infineon Technologies Ag | Chiprandversiegelung |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
JPS48101089A (ja) * | 1972-03-31 | 1973-12-20 | ||
JPS4937585A (ja) * | 1972-08-09 | 1974-04-08 | ||
JPS50152682A (ja) * | 1974-04-26 | 1975-12-08 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3503124A (en) * | 1967-02-08 | 1970-03-31 | Frank M Wanlass | Method of making a semiconductor device |
US3550260A (en) * | 1968-12-26 | 1970-12-29 | Motorola Inc | Method for making a hot carrier pn-diode |
NL6906939A (ja) * | 1969-05-06 | 1970-11-10 | ||
NL170348C (nl) * | 1970-07-10 | 1982-10-18 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult. |
NL170901C (nl) * | 1971-04-03 | 1983-01-03 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
DE2212168C2 (de) * | 1972-03-14 | 1982-10-21 | Ibm Deutschland Gmbh, 7000 Stuttgart | Monolithisch integrierte Halbleiteranordnung |
JPS5228550B2 (ja) * | 1972-10-04 | 1977-07-27 | ||
GB1457139A (en) * | 1973-09-27 | 1976-12-01 | Hitachi Ltd | Method of manufacturing semiconductor device |
US3909807A (en) * | 1974-09-03 | 1975-09-30 | Bell Telephone Labor Inc | Integrated circuit memory cell |
US3962717A (en) * | 1974-10-29 | 1976-06-08 | Fairchild Camera And Instrument Corporation | Oxide isolated integrated injection logic with selective guard ring |
US3982266A (en) * | 1974-12-09 | 1976-09-21 | Texas Instruments Incorporated | Integrated injection logic having high inverse current gain |
CA1056513A (en) * | 1975-06-19 | 1979-06-12 | Benjamin J. Sloan (Jr.) | Integrated logic circuit and method of fabrication |
-
1977
- 1977-02-03 US US05/765,325 patent/US4137109A/en not_active Expired - Lifetime
- 1977-04-12 JP JP4192677A patent/JPS52151575A/ja active Granted
- 1977-04-12 DE DE2716123A patent/DE2716123C2/de not_active Expired
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3648125A (en) * | 1971-02-02 | 1972-03-07 | Fairchild Camera Instr Co | Method of fabricating integrated circuits with oxidized isolation and the resulting structure |
JPS48101089A (ja) * | 1972-03-31 | 1973-12-20 | ||
JPS4937585A (ja) * | 1972-08-09 | 1974-04-08 | ||
JPS50152682A (ja) * | 1974-04-26 | 1975-12-08 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6323335A (ja) * | 1985-09-25 | 1988-01-30 | モノリシツク メモリ−ズ,インコ−ポレイテツド | 半導体装置及びその製造方法 |
JPS61263150A (ja) * | 1986-01-10 | 1986-11-21 | Toshiba Corp | 半導体装置の製造方法 |
JPH0431189B2 (ja) * | 1986-01-10 | 1992-05-25 |
Also Published As
Publication number | Publication date |
---|---|
DE2716123C2 (de) | 1986-02-06 |
DE2716123A1 (de) | 1977-10-20 |
JPS6228577B2 (ja) | 1987-06-22 |
US4137109A (en) | 1979-01-30 |
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