JPS52119186A - Manufacture of semiconductor - Google Patents
Manufacture of semiconductorInfo
- Publication number
- JPS52119186A JPS52119186A JP3582476A JP3582476A JPS52119186A JP S52119186 A JPS52119186 A JP S52119186A JP 3582476 A JP3582476 A JP 3582476A JP 3582476 A JP3582476 A JP 3582476A JP S52119186 A JPS52119186 A JP S52119186A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- substrate
- manufacture
- impurity
- sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/30—Diffusion for doping of conductive or resistive layers
- H10P32/302—Doping polycrystalline silicon or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/02—Contacts, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/96—Porous semiconductor
Landscapes
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3582476A JPS52119186A (en) | 1976-03-31 | 1976-03-31 | Manufacture of semiconductor |
| US05/782,418 US4063901A (en) | 1976-03-31 | 1977-03-29 | Method of manufacturing a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3582476A JPS52119186A (en) | 1976-03-31 | 1976-03-31 | Manufacture of semiconductor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52119186A true JPS52119186A (en) | 1977-10-06 |
| JPS6135705B2 JPS6135705B2 (enExample) | 1986-08-14 |
Family
ID=12452692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3582476A Granted JPS52119186A (en) | 1976-03-31 | 1976-03-31 | Manufacture of semiconductor |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4063901A (enExample) |
| JP (1) | JPS52119186A (enExample) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL190710C (nl) * | 1978-02-10 | 1994-07-01 | Nec Corp | Geintegreerde halfgeleiderketen. |
| JPS5939906B2 (ja) * | 1978-05-04 | 1984-09-27 | 超エル・エス・アイ技術研究組合 | 半導体装置の製造方法 |
| DE2927824A1 (de) * | 1978-07-12 | 1980-01-31 | Vlsi Technology Res Ass | Halbleitervorrichtungen und ihre herstellung |
| NL7900280A (nl) * | 1979-01-15 | 1980-07-17 | Philips Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
| DE2926874A1 (de) * | 1979-07-03 | 1981-01-22 | Siemens Ag | Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie |
| NL186352C (nl) * | 1980-08-27 | 1990-11-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
| US6251470B1 (en) * | 1997-10-09 | 2001-06-26 | Micron Technology, Inc. | Methods of forming insulating materials, and methods of forming insulating materials around a conductive component |
| US6858526B2 (en) * | 1998-07-14 | 2005-02-22 | Micron Technology, Inc. | Methods of forming materials between conductive electrical components, and insulating materials |
| US6333556B1 (en) | 1997-10-09 | 2001-12-25 | Micron Technology, Inc. | Insulating materials |
| US6103590A (en) * | 1997-12-12 | 2000-08-15 | Texas Instruments Incorporated | SiC patterning of porous silicon |
| US6350679B1 (en) | 1999-08-03 | 2002-02-26 | Micron Technology, Inc. | Methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry |
| US6437417B1 (en) * | 2000-08-16 | 2002-08-20 | Micron Technology, Inc. | Method for making shallow trenches for isolation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3600651A (en) * | 1969-12-08 | 1971-08-17 | Fairchild Camera Instr Co | Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon |
-
1976
- 1976-03-31 JP JP3582476A patent/JPS52119186A/ja active Granted
-
1977
- 1977-03-29 US US05/782,418 patent/US4063901A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US4063901A (en) | 1977-12-20 |
| JPS6135705B2 (enExample) | 1986-08-14 |
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