JPS51117588A - Manufacturing method of semiconductor equipment - Google Patents

Manufacturing method of semiconductor equipment

Info

Publication number
JPS51117588A
JPS51117588A JP50042184A JP4218475A JPS51117588A JP S51117588 A JPS51117588 A JP S51117588A JP 50042184 A JP50042184 A JP 50042184A JP 4218475 A JP4218475 A JP 4218475A JP S51117588 A JPS51117588 A JP S51117588A
Authority
JP
Japan
Prior art keywords
manufacturing
semiconductor equipment
semiconductor
equipment
accommodate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50042184A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5753983B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Yoshinobu Monma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP50042184A priority Critical patent/JPS51117588A/ja
Publication of JPS51117588A publication Critical patent/JPS51117588A/ja
Publication of JPS5753983B2 publication Critical patent/JPS5753983B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP50042184A 1975-04-09 1975-04-09 Manufacturing method of semiconductor equipment Granted JPS51117588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50042184A JPS51117588A (en) 1975-04-09 1975-04-09 Manufacturing method of semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50042184A JPS51117588A (en) 1975-04-09 1975-04-09 Manufacturing method of semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS51117588A true JPS51117588A (en) 1976-10-15
JPS5753983B2 JPS5753983B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-11-16

Family

ID=12628903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50042184A Granted JPS51117588A (en) 1975-04-09 1975-04-09 Manufacturing method of semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS51117588A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005723A1 (de) * 1978-05-25 1979-12-12 International Business Machines Corporation Hochintegrierte Halbleiterschaltung und Verfahren zu ihrer Herstellung
FR2443185A1 (fr) * 1978-11-30 1980-06-27 Ibm Topologie de circuits integres semi-conducteurs et procede pour l'obtention de cette topologie
JPH04218943A (ja) * 1991-04-19 1992-08-10 Toshiba Corp １チップｌｓｉの製造方法
JPH10150083A (ja) * 1988-05-16 1998-06-02 Glenn J Leedy 集積回路の製作および試験方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0005723A1 (de) * 1978-05-25 1979-12-12 International Business Machines Corporation Hochintegrierte Halbleiterschaltung und Verfahren zu ihrer Herstellung
FR2443185A1 (fr) * 1978-11-30 1980-06-27 Ibm Topologie de circuits integres semi-conducteurs et procede pour l'obtention de cette topologie
JPH10150083A (ja) * 1988-05-16 1998-06-02 Glenn J Leedy 集積回路の製作および試験方法
JPH04218943A (ja) * 1991-04-19 1992-08-10 Toshiba Corp １チップｌｓｉの製造方法

Also Published As

Publication number Publication date
JPS5753983B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1982-11-16

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