JPH1168087A - Resonance tunnel transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resonance tunnel transistor having a negative resistance characteristic which is superior in controllability by the gate voltage. SOLUTION: A transistor has a drain layer 2 formed on a substrate 1, a spacer layer 3 selectively formed at the drain layer 2, a double barrier quantum well structure 4 formed on the spacer layer 3, a channel layer 5 formed on the structure 4, a carrier supply layer 6 formed on the channel layer 5, a gate insulation layer 7 formed on the supply layer 6, a gate electrode 8 formed at the insulation layer 7, a drain electrode 9 ohmic-contacted to the drain layer 2, and a source electrode 10 ohmic-contacted to the channel layer 5. The drain layer 2 is selectively formed on the substrate 1, a spacer layer 3 is formed on the substrate 1 and part of the drain layer 2, and the source electrode 10 is ohmic-contacted to the channel layer 5 form at other than the drain layer 2 region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a transistor utilizing a tunnel phenomenon which can be multifunctional and operates at high speed, and a method of manufacturing the transistor.

[0002]

2. Description of the Related Art Conventionally, a resonance tunnel transistor has been proposed as a transistor capable of operating at high speed and having a function by controlling a resonance tunnel current by a gate voltage. For this device, for example, KF
Longenbach et al. (KFLongenbach et al., "Tw
o-dimensional electron gas modulated resonant tunn
eling transistor ", Appl. Phys. Lett. vol.59, p967
) In FIG. With this transistor, a functional circuit can be formed with a small number of elements, and high integration can be achieved. The structure and operation of this conventional tunnel transistor will be described below with reference to the structural diagram.

FIG. 3 is a sectional view showing the structure of a conventional tunnel transistor. The conventional tunnel transistor shown in FIG. 3 includes a substrate 1, a drain layer 2 having n-type conductivity, a spacer layer 3, and a semiconductor double barrier quantum well structure (hereinafter referred to as a quantum well structure) 4. A channel layer 5, a carrier supply layer 6 to the channel 5, a gate insulating layer 7, a gate electrode 8 on the gate insulating layer 7,
The configuration has a drain electrode 9 and a source electrode 10.

[0004] The operation of the conventional tunnel transistor shown in FIG. 3 is described by using a semi-insulating GaAs substrate, an n ⁺ -GaAs layer as a drain layer 2, and an i-G layer as a spacer layer 3.
An aAs layer is used, a quantum well structure 4 is used, and a channel layer 5 is used with a stacked structure in which both sides of a GaAs layer are sandwiched between AlAs layers.
An i-GaAs layer is used for the carrier supply layer 6 and n-Al
_{A 0.3} Ga _0.7 As layer is used, and i-Al
_{A 0.3} Ga _0.7 As layer is used, Al is used for the gate electrode 8, and AuGe /
An example using an Au film will be described. Here, "i-"
Is an abbreviation that means a non-doped semiconductor that can be regarded as intrinsic or substantially intrinsic.

Electrons are supplied to the channel layer 5 from the carrier supply layer 6 to form a two-dimensional electron gas layer. The channel layer 5 has an n-type conductivity. The source electrode 10
An ohmic contact is formed with the two-dimensional electron gas layer. The source electrode 10 is set to the ground potential, and a voltage is applied between the source and the drain. Between the channel layer 5 and the drain layer 2, there is a quantum well structure 4 including an AlAs / GaAs / AlAs layer.

When the electron energy incident on the quantum well structure 4 from the channel layer 5 coincides with the quantization energy level of the electrons formed in the quantum well structure 4, the tunneling probability of the electrons increases resonantly, Resonant tunnel current flows. On the other hand, when the incident electron energy and the quantum energy level do not match, the tunnel probability decreases, and a differential negative resistance appears in the current-voltage characteristics. Since the number of electrons in the channel can be controlled by the gate voltage, the differential negative resistance characteristic is controlled by the voltage applied to the gate electrode, and the operation of a transistor having functionality can be obtained.

[0007]

In the above-described structure of the conventional tunnel transistor, the number of electrons directly below the source electrode cannot be controlled by the gate voltage, so that a current exceeding a certain amount always flows between the source and the drain. Flows.
For this reason, there is a problem that the modulation efficiency of the tunnel current due to the gate voltage is small and the operation with low power consumption is difficult.

In view of the foregoing, an object of the present invention is to provide a resonance tunnel transistor having a negative resistance characteristic excellent in controllability by a gate voltage.

[0009]

Means for Solving the Problems To achieve the above object, a resonant tunneling transistor of the present invention comprises a substrate (1) having at least a surface portion exhibiting an insulating property, and a substrate (1) formed on the surface of the substrate (1). A drain layer (2) comprising a first semiconductor exhibiting one conductivity; and a spacer layer (3) selectively formed on the drain layer (2) and comprising a second semiconductor.
And a third semiconductor formed on the spacer layer (3) and having an electron affinity smaller than that of the second semiconductor.
A double barrier quantum well structure (4) sandwiching a fourth semiconductor exhibiting the same characteristics as the semiconductor of (5), and a fifth barrier formed on the double barrier quantum well structure (4) and exhibiting first conductivity A channel layer (5) including the semiconductor of (5), a carrier supply layer (6) formed on the channel layer (5), and a carrier supply layer (6) formed on the carrier supply layer (6). A gate insulating layer (7) including a sixth semiconductor having a large band gap energy; a gate electrode (8) formed on the gate insulating layer (7); and an ohmic contact with the drain layer (2). Drain electrode (9)
And a source electrode (10) in ohmic contact with the channel layer (5), wherein the drain layer (2) is selectively formed on the surface of the substrate (1). The spacer layer (3) is formed on the surface of the substrate (1) and a part of the surface of the drain layer (2), and the source electrode (10) is formed with the drain layer (2). In ohmic contact with the channel layer (5) formed in the non-existing region.

In the above-described resonant tunneling transistor of the present invention, the gate electrode (8) is connected to the source electrode (10).
And a region where the drain layer (2) is formed.

According to the method for manufacturing a resonant tunneling transistor of the present invention, at least the surface of the substrate exhibits an insulating property.
Forming a drain layer (2) comprising a first semiconductor exhibiting a first conductivity on the surface of the substrate, and selecting a spacer layer (3) comprising a second semiconductor on the drain layer (2) Forming a fourth semiconductor having the same characteristics as the second semiconductor on the spacer layer (3) by using a third semiconductor having a smaller electron affinity than the second semiconductor. Forming a double-barrier quantum well structure (4) by sandwiching the same, and forming a channel layer (5) including a fifth semiconductor exhibiting first conductivity on the double-barrier quantum well structure (4) Forming a carrier supply layer (6) on the channel layer (5); and forming a sixth semiconductor having a band gap energy larger than that of the fifth semiconductor on the carrier supply layer (6). Forming a gate insulating layer (7) comprising: Layer (7) a gate electrode on (8)
Forming a drain electrode (9) in ohmic contact with the drain layer (2); and forming a source electrode (1).
0) contacting the channel layer (5) with the channel layer (5), comprising the steps of: selectively forming the drain layer (2) on the surface of the substrate (1); The spacer layer (3) is applied to the substrate (1).
Forming the source electrode (10) on the surface of the drain layer (2) and a part of the surface of the drain layer (2); ) To make ohmic contact.

The method of manufacturing a resonant tunnel transistor according to the present invention includes the step of forming the gate electrode (8) between the source electrode (10) and the region where the drain layer (2) is formed. Can have.

By adopting such a structure and a manufacturing method, an overlapping region between the source and the drain can be eliminated, so that a leak current component flowing directly between the source and the drain is suppressed, and the ON of the tunnel current by the gate voltage is suppressed. It is possible to increase the / OFF ratio.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of a resonant tunneling transistor according to a first embodiment of the present invention. 1, the same reference numerals as those in FIG. 3 denote the same components as those in FIG. 3 and perform the same functions.

The resonant tunnel transistor shown in FIG. 1 has substantially the same structure as the conventional tunnel transistor described with reference to FIG. 3, except that a drain layer 2 is selectively formed on the surface of a substrate 1 and a spacer layer is formed. 3 is formed on the surface of the substrate 1 and on a part of the drain layer 2, except that the source electrode 10 is in ohmic contact with the channel layer 5 formed in a region where the drain layer 2 is not formed.

The resonance tunnel transistor shown in FIG.
The operation is performed using a semi-insulating GaAs substrate 1 and a drain layer.
2 to n⁺ I-Ga is used for the spacer layer 3 using a GaAs layer.
Using an As layer, the quantum well structure 4 has A on both sides of the GaAs layer.
The laminated structure sandwiched between the lAs layers is used for the channel layer 5.
Using an i-GaAs layer, n-Al
_0.3 Ga_0.7 Using an As layer, i-Al
_0.3 Ga_0.7 Al is used for the gate electrode 8 using an As layer.
AuGe / drain electrode 9 and source electrode 10
An example using an Au film will be described. Here, "i-"
Is an undoped semiconductor that can be regarded as intrinsic or substantially intrinsic
Is an abbreviation that means

In the resonance tunnel transistor of the first embodiment, as in the conventional tunnel transistor described with reference to FIG. 3, the resonance tunnel current via the quantum well structure 4 between the source and the drain is applied to the gate. Control by voltage. However, in the structure of the first embodiment shown in FIG. 1, the conductive drain layer 2 is located immediately below the source electrode.
Does not exist, the leakage current component flowing directly between the source and the drain is suppressed. Therefore, controllability by the gate voltage is improved.

Next, a method of manufacturing the resonant tunnel transistor according to the first embodiment will be described. A 600 nm-thick n ⁺ -GaAs is formed on the (100) plane on the GaAs substrate 1.
The s layer 2 is formed by molecular beam epitaxial growth (Molecular Beam).
It is formed at a substrate temperature of 600 ° C. by using Epitaxy (hereinafter referred to as MBE method). This n ⁺ -GaAs layer 2 contains Si at a concentration of 3 × 10 ¹⁸ cm ⁻³ as a dopant.

N other than the part to be the drain⁺ -GaAs
After removing the layer 2, i-GaAs having a thickness of 50 nm is formed on the entire surface.
s spacer layer 3 and a 7 nm thick i-GaAs layer
Quantum well structure 4 sandwiched between 2.8 nm i-AlAs layers
And an i-GaAs channel layer 5 having a thickness of 50 nm and a thickness of
10 nm n-Al_0.3 Ga_0.7 As carrier supply layer 6
And i-Al with a thickness of 350 nm_0.3 Ga_0.7 As gate
The laminated structure having the insulating layer 7 is formed on a substrate by using the MBE method.
Regrows at a temperature of 560 degrees. This n-Al _0.3 G
a_0.7 The As carrier supply layer 6 has a concentration of 2 × 10¹⁸cm^-3
Of Si as a dopant.

In order to partially overlap the drain layer 2,
After depositing an Al film having a thickness of 50 nm in the shape of the gate electrode 9, the laminated structures 3 to 7 formed on the drain layer 2 where the drain electrode 9 is to be formed are removed. Finally, a drain electrode 9 and a source electrode 10 made of an AuGe / Au multilayer film are formed by a lift-off method.

By forming a semiconductor device having such a structure, a leak current component flowing between a source and a drain is suppressed, and a tunnel current caused by a gate voltage is reduced.
The N / OFF ratio increases by two digits or more compared to the conventional example.

[Second Embodiment] FIG. 2 is a sectional view showing a structure of a resonant tunneling transistor according to a second embodiment of the present invention. 2, the same reference numerals as those in FIG. 3 denote the same components as those in FIG. 3 and perform the same functions.

The structure of the resonant tunneling transistor shown in FIG. 2 is substantially the same as that of the first embodiment described with reference to FIG. 1, except that a gate electrode 8 is provided with a source electrode 10 and a drain layer 2. The difference is that it is formed only between the region and the non-existing region.

The resonance tunnel transistor shown in FIG.
The operation is performed using a semi-insulating GaAs substrate 1 and a drain layer.
2 to n⁺ I-Ga is used for the spacer layer 3 using a GaAs layer.
Using an As layer, the quantum well structure 4 has A on both sides of the GaAs layer.
The laminated structure sandwiched between the lAs layers is used for the channel layer 5.
Using an i-GaAs layer, n-Al
_0.3 Ga_0.7 Using an As layer, i-Al
_0.3 Ga_0.7 Al is used for the gate electrode 8 using an As layer.
AuGe / drain electrode 9 and source electrode 10
An example using an Au film will be described. Here, "i-"
Is an undoped semiconductor that can be regarded as intrinsic or substantially intrinsic
Is an abbreviation that means

In the resonance tunnel transistor of the second embodiment, as in the conventional tunnel transistor described with reference to FIG. 3, the resonance tunnel current via the quantum well structure 4 between the source and the drain is applied to the gate. Control by voltage. However, similarly to the first embodiment described with reference to FIG. 1, in the structure of the second embodiment, since the conductive drain layer 2 does not exist immediately below the source electrode, the source-drain Is suppressed. Therefore, controllability by the gate voltage is improved. Also, the gate electrode 8 is different from that of the first embodiment.
, The gate length is short, and high-speed operation can be achieved.

Next, a method for manufacturing the resonant tunnel transistor according to the second embodiment will be described. The manufacturing method according to the second embodiment differs from the manufacturing method according to the first embodiment only in the method of forming the gate electrode 8. That is, in the manufacturing method of the first embodiment,
By forming the gate electrode between the source electrode and the end of the drain layer, the manufacturing method of the second embodiment can be obtained.

An n ⁺ -GaAs layer 2 having a thickness of 600 nm is formed on the (100) plane of the GaAs substrate 1 at a substrate temperature of 600 ° C. by MBE. This n ⁺ -GaAs layer 2
Contains Si at a concentration of 3 × 10 ¹⁸ cm ⁻³ as a dopant.

N other than the part to be the drain⁺ -GaAs
After removing the layer 2, i-GaAs having a thickness of 50 nm is formed on the entire surface.
s spacer layer 3 and a 7 nm thick i-GaAs layer
Quantum well structure 4 sandwiched between 2.8 nm i-AlAs layers
And an i-GaAs channel layer 5 having a thickness of 50 nm and a thickness of
10 nm n-Al_0.3 Ga_0.7 As carrier supply layer 6
And i-Al with a thickness of 350 nm_0.3 Ga_0.7 As gate
The laminated structure having the insulating layer 7 is formed on a substrate by using the MBE method.
Regrows at a temperature of 560 degrees. This n-Al _0.3 G
a_0.7 The As carrier supply layer 6 has a concentration of 2 × 10¹⁸cm^-3
Of Si as a dopant.

An Al film having a thickness of 50 nm was deposited in the shape of the gate electrode 9 so as not to overlap the region where the drain layer 2 is formed, and then formed on the drain layer 2 where the drain electrode 9 is to be formed. A part of the laminated structures 3 to 7 is removed. Finally, a drain electrode 9 and a source electrode 10 made of an AuGe / Au multilayer film are formed by a lift-off method.

By forming a semiconductor device having such a structure, a leak current component flowing between a source and a drain is suppressed, and a tunnel current caused by a gate voltage is reduced.
The N / OFF ratio increases by two digits or more compared to the conventional example. Further, by shortening the gate length of the gate electrode 8,
The operating speed is improved three times.

In the present invention, the conductivity type of the channel layer 5 is made n-type by providing the carrier supply layer 6 on the channel layer 5. However, conductivity may be ensured by directly doping the channel layer 5 with an impurity. Further, although the case where a GaAs / AlGaAs system is used has been described as an embodiment, it is apparent that the present invention can be applied to a case where another material system is used.

[0033]

As described above, according to the present invention, it is possible to realize a resonance tunnel transistor having a negative resistance characteristic excellent in controllability by a gate voltage, and as a result, high speed, low power consumption and room temperature operation can be achieved. This has the effect that an ultra-high density tunnel device integrated circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a resonant tunnel transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a resonant tunneling transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the structure of a conventional tunnel transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Drain layer 3 Spacer layer 4 Semiconductor double barrier quantum well structure 5 Channel layer 6 Carrier supply layer 7 Gate insulating layer 8 Gate electrode 9 Drain electrode 10 Source electrode

Claims (4)

[Claims] 1. A substrate having at least a surface portion exhibiting an insulating property, a drain layer formed on a surface of the substrate and including a first semiconductor exhibiting a first conductivity, and selectively formed on the drain layer. And a spacer layer comprising a second semiconductor;
A double-barrier quantum well structure sandwiching a fourth semiconductor formed on the spacer layer and having the same characteristics as the second semiconductor by using a third semiconductor having a smaller electron affinity than the second semiconductor. A channel layer formed on the double barrier quantum well structure and including a fifth semiconductor exhibiting a first conductivity; a carrier supply layer formed on the channel layer; A gate insulating layer including a sixth semiconductor having a bandgap energy larger than that of the fifth semiconductor, a gate electrode formed on the gate insulating layer, and ohmic contact with the drain layer. A resonant tunneling transistor having a drain electrode and a source electrode in ohmic contact with the channel layer, wherein the drain layer is selectively formed on a surface of the substrate; A layer is formed on a surface of the substrate and a part of a surface of the drain layer, and the source electrode is in ohmic contact with the channel layer formed in a region where the drain layer is not formed. A resonant tunnel transistor, characterized by: 2. The resonance tunnel transistor according to claim 1, wherein said gate electrode is formed between said source electrode and a region where said drain layer is formed. 3. A step of forming a drain layer including a first semiconductor having a first conductivity on a surface of a substrate having at least a surface portion having an insulating property;
Selectively forming a spacer layer including the semiconductor of the above, and using a third semiconductor having an electron affinity smaller than that of the second semiconductor on the spacer layer to exhibit the same characteristics as the second semiconductor. Forming a double-barrier quantum well structure with a fourth semiconductor interposed therebetween, and forming a channel layer including a fifth semiconductor having first conductivity on the double-barrier quantum well structure; Forming a carrier supply layer on the channel layer, forming a gate insulating layer including a sixth semiconductor having a bandgap energy larger than that of the fifth semiconductor on the carrier supply layer, Forming a gate electrode on an insulating layer; making a drain electrode ohmic contact with the drain layer; and making a source electrode ohmic contact with the channel layer. In the method for manufacturing a transistor, a step of selectively forming the drain layer on a surface of the substrate; a step of forming the spacer layer on a surface of the substrate and a partial surface of the drain layer; Making ohmic contact with the channel layer formed in a region where the drain layer is not formed. 4. The method according to claim 3, further comprising the step of forming the gate electrode between the source electrode and the region where the drain layer is formed. .