JPH05235057A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05235057A
JPH05235057A JP4070459A JP7045992A JPH05235057A JP H05235057 A JPH05235057 A JP H05235057A JP 4070459 A JP4070459 A JP 4070459A JP 7045992 A JP7045992 A JP 7045992A JP H05235057 A JPH05235057 A JP H05235057A
Authority
JP
Japan
Prior art keywords
source
semiconductor
drain
gaas
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4070459A
Other languages
Japanese (ja)
Inventor
Minoru Sawada
稔 澤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP4070459A priority Critical patent/JPH05235057A/en
Publication of JPH05235057A publication Critical patent/JPH05235057A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures

Abstract

PURPOSE:To realize a function other than an operation like a three-pole vacuum tube by semiconductor device which utilizes a tunnel effect. CONSTITUTION:A GaAs quantum well layer held between barrier layers consisting of an AlAs layer having an electron affinity smaller than that of a GaAs layer is provided between respective ohmic contacts (GaAs layers) of a source 2 and a drain 3. Only when the quantum well layer and the ohmic contact of the source 2 are brought in a resonance state, the source and a channel are connected to each other, a tunnel junction is formed between the source and the drain and a drain current flows. As a result, negative resistance is shown at a voltage region in a state exceeding the resonance state.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、トンネル効果によりド
レイン電流を制御する電界効果型半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device which controls a drain current by a tunnel effect.

【0002】[0002]

【従来の技術】微細化に適する新しい原理の量子効果デ
バイスとして表面トンネルトランジスタが提案されてい
る(「表面トンネルトランジスタの提案と試作」p.116
0, 馬場寿夫;日本電気(株)基礎研究所:応用物理学
会秋季講演会9a-K-2)。図1は上述の表面トンネルトラ
ンジスタの構成を示す模式的断面図であって、GaAs基板
1には n+ - GaAsをオーミックコンタクトとするソース
2、及びソース2と異なった伝導型で、不純物を高濃度
に含む縮退半導体の p+ - GaAsをオーミックコンタクト
とするドレイン3が形成され、ソース2・ドレイン3間
にはAlGaAs絶縁層4を介してAlゲート電極5が接続され
ている。
2. Description of the Related Art A surface tunnel transistor has been proposed as a quantum effect device of a new principle suitable for miniaturization ("Proposal and Prototype of Surface Tunnel Transistor" p.116).
0, Toshio Baba; Basic Research Laboratories, NEC Corporation: Autumn Meeting, Japan Society of Applied Physics 9a-K-2). FIG. 1 is a schematic cross-sectional view showing the structure of the surface tunnel transistor described above. The GaAs substrate 1 has a source 2 having an ohmic contact of n + -GaAs and a conductivity type different from that of the source 2 and a high impurity concentration. A drain 3 having ohmic contact with p + -GaAs, which is a degenerate semiconductor included in the concentration, is formed, and an Al gate electrode 5 is connected between the source 2 and the drain 3 via an AlGaAs insulating layer 4.

【0003】次に動作について説明する。ソース・ドレ
イン間には逆バイアスを印加する。ゲート電圧を正にし
てゲート下のチャネルに電子が蓄積されるとソース・チ
ャネル間が接続され、チャネル・ドレイン間にはトンネ
ル接合が形成される。このため、ゲート電圧に依存して
トンネル接合にはドレイン電流(トンネル電流)が流
れ、トランジスタは三極真空管的な非飽和特性を示す。
Next, the operation will be described. Reverse bias is applied between the source and drain. When the gate voltage is made positive and electrons are accumulated in the channel under the gate, the source and the channel are connected and a tunnel junction is formed between the channel and the drain. Therefore, a drain current (tunnel current) flows through the tunnel junction depending on the gate voltage, and the transistor exhibits non-saturation characteristics like a triode vacuum tube.

【0004】[0004]

【発明が解決しようとする課題】上述の表面トンネルト
ランジスタはトンネル効果を利用してドレイン電流を制
御することにより三極真空管的な動作はするが、これ以
外の機能は持っていない。
The surface tunnel transistor described above operates as a triode vacuum tube by controlling the drain current by utilizing the tunnel effect, but has no other function.

【0005】本発明はこのような問題点を解決するため
になされたものであって、トンネル効果を利用してドレ
イン電流を制御する半導体装置に三極真空管的動作以外
の機能を持たせた半導体装置の提供を目的とする。
The present invention has been made to solve the above problems, and a semiconductor device in which the drain current is controlled by utilizing the tunnel effect has a function other than a triode vacuum tube operation. The purpose is to provide a device.

【0006】[0006]

【課題を解決するための手段】本発明に係る半導体装置
は、一伝導型の第1の半導体からなるソース領域及び他
伝導型の第1の半導体からなるドレイン領域間にチャネ
ル層を有し、チャネル層に、第1の半導体より電子親和
力が小さい第2の半導体を介してゲート電極が接続され
た半導体装置において、チャネル層に、ソース領域から
ドレイン領域方向に、第1の半導体より電子親和力が小
さい第3の半導体からなるバリア層,第1の半導体から
なる量子井戸層及び第3の半導体からなるバリア層がこ
の順で形成されていることを特徴とする。
A semiconductor device according to the present invention has a channel layer between a source region made of a first semiconductor of one conductivity type and a drain region made of a first semiconductor of another conductivity type, In a semiconductor device in which a gate electrode is connected to a channel layer via a second semiconductor having an electron affinity lower than that of the first semiconductor, the channel layer has an electron affinity higher than that of the first semiconductor in the direction from the source region to the drain region. It is characterized in that a small barrier layer made of a third semiconductor, a quantum well layer made of a first semiconductor, and a barrier layer made of a third semiconductor are formed in this order.

【0007】[0007]

【作用】本発明に係る半導体装置は、量子井戸層の両端
に印加される電圧により量子井戸層とソースのオーミッ
クコンタクトとが共鳴トンネル状態になったときのみチ
ャネル・ソース間が接続され、ソース・ドレイン間にト
ンネル接合が形成されて電流が流れるが、共鳴トンネル
状態を超えるとバリア層がトンネル接合の形成を阻み、
電圧の増加とともにドレイン電流が減少する負性抵抗を
示す。
In the semiconductor device according to the present invention, the channel and source are connected only when the quantum well layer and the ohmic contact of the source are in a resonant tunnel state due to the voltage applied across the quantum well layer, and the source and source are connected. A tunnel junction is formed between the drains and current flows, but when the resonance tunnel state is exceeded, the barrier layer prevents the formation of a tunnel junction.
It shows a negative resistance in which the drain current decreases with increasing voltage.

【0008】[0008]

【実施例】以下、本発明をその実施例を示す図に基づい
て説明する。図2は本発明に係る電界効果トランジスタ
の構成を示す模式的断面図である。n+ - GaAs基板1に
は n+ - GaAs(n=6×1018cm-3, 250nm)をオーミックコン
タクトとするソース2,GaAsより電子親和力が小さいun
doped AlAsのバリア層(5nm),undoped GaAsの量子井戸層
(5nm),undoped AlAsのバリア層(5nm)及びundoped GaAs
層(190nm) 及びソース2と異なった伝導型で不純物を高
濃度に含む縮退半導体の p+ - GaAs(p=5×1019cm-3,10
0nm)をオーミックコンタクトとするドレイン3がこの順
で横方向に結晶成長されており、メサ構造形成後、ソー
ス2・ドレイン3間に再成長させた、GaAsより電子親和
力が小さいAlGaAs絶縁層4(100nm) を介してAlゲート電
極5, AuGe/Au ソース・ドレイン電極が形成されてい
る。
The present invention will be described below with reference to the drawings showing the embodiments thereof. FIG. 2 is a schematic sectional view showing the structure of the field effect transistor according to the present invention. n + -GaAs substrate 1 has n + -GaAs (n = 6 × 10 18 cm -3 , 250 nm) as ohmic contact source 2 and has a smaller electron affinity than GaAs.
Barrier layer of doped AlAs (5 nm), quantum well layer of undoped GaAs
(5nm), undoped AlAs barrier layer (5nm) and undoped GaAs
P + -GaAs (p = 5 × 10 19 cm -3 , 10) which is a conduction type different from the layer (190 nm) and source 2 and contains a high concentration of impurities
The drain 3 having an ohmic contact of 0 nm) is laterally grown in this order, and the AlGaAs insulating layer 4 (having a smaller electron affinity than GaAs) regrown between the source 2 and the drain 3 after the mesa structure is formed. An Al gate electrode 5 and AuGe / Au source / drain electrodes are formed via 100 nm).

【0009】上述のバリア層及び量子井戸層の幅は、ト
ンネル効果により電子波を伝達し得る幅に設定されてい
る。
The widths of the barrier layer and the quantum well layer described above are set so that electron waves can be transmitted by the tunnel effect.

【0010】次に、動作について説明する。ソース・ド
レイン間には逆方向バイアスを印加する。ゲート電圧を
正にするとゲート下のチャネルに電子が蓄積され、量子
井戸層(GaAs)がソース2のオーミックコンタクト(n+ -G
aAs)と共鳴トンネル状態になったときのみソース・チャ
ネル間が接続され、チャネル・ドレイン間に大きな電流
が流れる。
Next, the operation will be described. A reverse bias is applied between the source and drain. When the gate voltage is positive, electrons are accumulated in the channel under the gate, and the quantum well layer (GaAs) is connected to the ohmic contact (n + -G) of the source 2.
The source-channel is connected and a large current flows between the channel-drain only when it enters a resonance tunnel state with (aAs).

【0011】しかし、共鳴トンネル状態を超えるとドレ
イン電圧の増加とともにドレイン電流が減少する負性抵
抗を示すようになる。さらにドレイン電圧が増すと通常
の拡散電流が流れる。本発明に係る電界効果トランジス
タの負性抵抗特性は77Kにて確認された。
However, when the resonance tunnel state is exceeded, the drain current decreases and the drain current decreases. When the drain voltage further increases, a normal diffusion current flows. The negative resistance characteristic of the field effect transistor according to the present invention was confirmed at 77K.

【0012】以上のような負性抵抗特性により、増幅・
発振などの機能が実現可能となる。
Due to the above negative resistance characteristics, amplification
Functions such as oscillation can be realized.

【0013】[0013]

【発明の効果】以上のように、本発明に係る半導体装置
は負性抵抗を示すので、三極真空管的な動作以外の機能
を実現するという優れた効果を奏する。
As described above, since the semiconductor device according to the present invention exhibits a negative resistance, it has an excellent effect of realizing a function other than a triode vacuum tube operation.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来の表面トンネルトランジスタの模式的断面
図である。
FIG. 1 is a schematic cross-sectional view of a conventional surface tunnel transistor.

【図2】本発明に係る電界効果トランジスタの模式的断
面図である。
FIG. 2 is a schematic sectional view of a field effect transistor according to the present invention.

【符号の説明】[Explanation of symbols]

2 ソース 3 ドレイン 5 ゲート電極 7 チャネル層 2 source 3 drain 5 gate electrode 7 channel layer

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 // H01L 29/88 Z 8225−4M ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location // H01L 29/88 Z 8225-4M

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 一伝導型の第1の半導体からなるソース
領域及び他伝導型の第1の半導体からなるドレイン領域
間にチャネル層を有し、チャネル層に、第1の半導体よ
り電子親和力が小さい第2の半導体を介してゲート電極
が接続された半導体装置において、チャネル層に、ソー
ス領域からドレイン領域方向に、第1の半導体より電子
親和力が小さい第3の半導体からなるバリア層,第1の
半導体からなる量子井戸層及び第3の半導体からなるバ
リア層がこの順で形成されていることを特徴とする半導
体装置。
1. A channel layer is provided between a source region made of one conductivity type first semiconductor and a drain region made of another conductivity type first semiconductor, and the channel layer has an electron affinity higher than that of the first semiconductor. In a semiconductor device in which a gate electrode is connected via a small second semiconductor, a barrier layer made of a third semiconductor having an electron affinity smaller than that of the first semiconductor in a direction from a source region to a drain region in a channel layer, 2. A semiconductor device having a quantum well layer made of the above semiconductor and a barrier layer made of a third semiconductor in this order.
JP4070459A 1992-02-19 1992-02-19 Semiconductor device Pending JPH05235057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4070459A JPH05235057A (en) 1992-02-19 1992-02-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4070459A JPH05235057A (en) 1992-02-19 1992-02-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05235057A true JPH05235057A (en) 1993-09-10

Family

ID=13432126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4070459A Pending JPH05235057A (en) 1992-02-19 1992-02-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05235057A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08186272A (en) * 1994-12-29 1996-07-16 Nec Corp Tunnel transistor
US5589696A (en) * 1991-10-15 1996-12-31 Nec Corporation Tunnel transistor comprising a semiconductor film between gate and source/drain
EP3087610A4 (en) * 2013-12-23 2017-08-02 Intel Corporation Heterogeneous pocket for tunneling field effect transistors (tfets)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5589696A (en) * 1991-10-15 1996-12-31 Nec Corporation Tunnel transistor comprising a semiconductor film between gate and source/drain
JPH08186272A (en) * 1994-12-29 1996-07-16 Nec Corp Tunnel transistor
JP2643890B2 (en) * 1994-12-29 1997-08-20 日本電気株式会社 Tunnel transistor
EP3087610A4 (en) * 2013-12-23 2017-08-02 Intel Corporation Heterogeneous pocket for tunneling field effect transistors (tfets)

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