JPS60196976A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60196976A JPS60196976A JP3265385A JP3265385A JPS60196976A JP S60196976 A JPS60196976 A JP S60196976A JP 3265385 A JP3265385 A JP 3265385A JP 3265385 A JP3265385 A JP 3265385A JP S60196976 A JPS60196976 A JP S60196976A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate electrode
- gate
- electrons
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 16
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 239000000969 carrier Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
【発明の利用分野〕
本発明は高速スイッチング特性の極めて優れた電界効果
トランジスタに関する。このトランジスタを集積化した
条種回路素子はたとえば超高速コンピューター用の論理
素子などに適したものである。DETAILED DESCRIPTION OF THE INVENTION Field of Application of the Invention The present invention relates to a field effect transistor with extremely excellent high-speed switching characteristics. A circuit element in which this transistor is integrated is suitable for use as a logic element for an ultra-high-speed computer, for example.
ノンドープのG a A sとn型AfiGaAsを接
触させることによってQ a A s側に発生した電子
をゲート電界で制御する新しい電界効果トランジスタが
開発されている(日経エレクトロニクス1980.7.
21 P、66〜69)。ドナー不純物をAQGaAs
側に、ドナーからの電子をG a A s側に集めてい
るため、低温で電子は不純物散乱を受けずに走行でき、
移動度を高くすることができる。A new field effect transistor has been developed in which electrons generated on the Q a As side are controlled by a gate electric field by bringing non-doped Ga As and n-type AfiGaAs into contact (Nikkei Electronics 1980.7.
21 P, 66-69). AQGaAs donor impurity
Since electrons from donors are collected on the Ga As side, electrons can travel at low temperatures without being scattered by impurities.
Mobility can be increased.
しかしながらこの1−ランジスタでは、ショットキゲー
トを用いているため、ゲート電極にゲート・リーク電流
が流れ、論理振幅が大きくとれないということ等が判明
した。However, since this 1-transistor uses a Schottky gate, it has been found that a gate leak current flows through the gate electrode, making it impossible to obtain a large logic amplitude.
本発明は、安定な膜が得られ、またゲート電極にゲート
・リーク電流が流れない構造を有する新しい電界効果ト
ランジスタである半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device, which is a new field effect transistor, which has a structure in which a stable film is obtained and no gate leakage current flows through the gate electrode.
本発明は選択的ドーピング法で電子供与体となる不純物
ドーピング層と、電子を走らせる層とを分離し、且つ電
子を走らせる層に金属−酸化物一半導体接合(MO8接
合と称する。)をゲート電極として用いるものである。The present invention uses a selective doping method to separate an impurity doped layer that serves as an electron donor and a layer through which electrons run, and also forms a metal-oxide-semiconductor junction (referred to as MO8 junction) in the layer through which electrons run. It is used as a gate electrode.
第1図に本発明の基本構造を示す。素子の断面図を示し
ている。半絶縁性GaAs基板(比抵抗:10°Ω・c
m)1上に高純度QaAsJ12、n型GaAQAs層
3を設ける。FIG. 1 shows the basic structure of the present invention. A cross-sectional view of the element is shown. Semi-insulating GaAs substrate (specific resistance: 10°Ω・c
m) High purity QaAsJ12 and n-type GaAQAs layer 3 are provided on 1.
更にGaAΩAs層3の上に酸化物9を形成し、オーミ
ック電極なるソース6、ドレイン8.およびゲート電極
7なる金属を設けてトランジスタは構成される。n型c
aAnAs層3は電子供与体となる不純物ドーピング層
であり、このGaAQAs層3と高純度GaAs層2の
界面にキャリアを貯蓄し、このキャリアをゲート電極7
を通して、ドレイン電流を変調する。Further, an oxide 9 is formed on the GaAΩAs layer 3, and a source 6, a drain 8, which serves as ohmic electrodes are formed. A transistor is constructed by providing a metal as a gate electrode 7. n type c
The aAnAs layer 3 is an impurity-doped layer that serves as an electron donor, and stores carriers at the interface between the GaAQAs layer 3 and the high-purity GaAs layer 2, and transfers these carriers to the gate electrode 7.
modulates the drain current through the
〔発明の実施例〕 以下、実施例にて説明する。[Embodiments of the invention] Examples will be described below.
実施例1
半絶縁性G a A s基板上1に良く知られている液
相成長法で高純度n型G a A s 2、その上にn
+型GaAQxAsx−x (x=0.4)3をそれぞ
れ0.3μm、0.1μm成長させた。n型GaAs2
はアンドープであり、n+型GaAnAs3はSnドー
プし、キャリア濃度として5 X 1017cm−3で
ある。その後SiH4ガスの熱分解法で5i02膜を3
500人被着する。この上にソース、ドレイン電極とな
るパターンを通常のホトレジストを用いた処理で形成す
る。次いでn型GaAQ層2に達するまでエツチングし
た。エツチング後。Example 1 High-purity n-type GaAs 2 was deposited on a semi-insulating GaAs substrate 1 by a well-known liquid phase growth method, and then n
+-type GaAQxAsx-x (x=0.4)3 was grown to 0.3 μm and 0.1 μm, respectively. n-type GaAs2
is undoped, n+ type GaAnAs3 is doped with Sn, and has a carrier concentration of 5 x 1017 cm-3. After that, the 5i02 film was made into 3 layers using SiH4 gas thermal decomposition method.
Covers 500 people. On top of this, patterns that will become source and drain electrodes are formed by processing using normal photoresist. Next, etching was performed until the n-type GaAQ layer 2 was reached. After etching.
AuGeNd系金屈5を被金属、オーミック電極とした
。ソース、ドレイン電極形成後、酸素プラズマ中でn型
GaARAsを酸化し、酸化膜9を1000人の厚さに
形成した。酸化膜形成後、ゲート金属7としてA u
/ M oとして用いた。すなわち、酸化膜上にMo(
モリブデン)金属を、更にMo金属上に金(Au)を連
続被着させた。次いでホトレジストを用いた処理により
ゲートパターンのホトレジスト膜を残す。このホトレジ
スト膜をマスクとしてA’uをイオンエツチングし、M
OをCF4(フレオン)ガスでプラズマエッチして、ゲ
ート電極は形成した。その結果、GaAQAsを酸化し
た膜はG a A sを酸化した膜より耐熱性にも優れ
、しかも、フラットバンド電圧V□、・。は再現性よく
出来た。本来、GaAQAs3中の電子移動度は小さい
が、本デバイスはチャネルとしてアンドープのG a
A sの方を用いるので、高い電子移動度で電子を動か
すことができる。そのため酸化膜を安定して製作できる
事の方が大きな利点となる。又、デプレション型で動作
させ、ソース、グー1〜.ドレイン間が分離させた構造
となり、入力容量が小さくなり、高速動作ができた。AuGeNd-based Kinku 5 was used as a metal target and an ohmic electrode. After forming the source and drain electrodes, the n-type GaARAs was oxidized in oxygen plasma to form an oxide film 9 with a thickness of 1000 nm. After forming the oxide film, A u as the gate metal 7
/ M o. That is, Mo(
Molybdenum) metal and gold (Au) were continuously deposited on the Mo metal. Next, a photoresist film is left as a gate pattern by processing using a photoresist. Using this photoresist film as a mask, A'u is ion-etched, and M
A gate electrode was formed by plasma etching O with CF4 (Freon) gas. As a result, a film made of oxidized GaAQAs has better heat resistance than a film made of oxidized GaAs, and has a flat band voltage of V□, ·. was achieved with good reproducibility. Originally, the electron mobility in GaAQAs3 is small, but this device uses undoped Ga as a channel.
Since A s is used, electrons can be moved with high electron mobility. Therefore, it is a great advantage to be able to stably produce an oxide film. Also, operate in depression type, source, goo 1~. The structure separates the drains, reducing input capacitance and allowing high-speed operation.
実施例2
実施例1で示した製法の中で、アンドープGaAs2.
n十型GaAl2As3を分子線エピタキシャル法で形
成した。分子線エピタキシャル法は10 ”−9Tor
r以下の超高真空内で、Ga 、 A s 。Example 2 Among the manufacturing methods shown in Example 1, undoped GaAs2.
n-type GaAl2As3 was formed by molecular beam epitaxial method. Molecular beam epitaxial method is 10”-9 Tor
Ga, As in an ultra-high vacuum below r.
AQのそれぞれのオーブンからG a A s 2の場
合、GaとAsを、GaAQAs、3の場合はG a’
、 A Q 。From each oven of AQ, Ga and As for 2, Ga' for GaAQAs, and 3.
, AQ.
Asと不純物源となるSiを同時に分子にして半絶縁性
G a A s基板上にGaAs、GaAQAsを形成
した。他は実施例1と同一である。GaAs and GaAQAs were formed on a semi-insulating GaAs substrate by simultaneously converting As and Si, which serves as an impurity source, into molecules. The rest is the same as in Example 1.
以上本発明の特徴をまとめると下記の様になる。 The features of the present invention can be summarized as follows.
ヘテロ接合(GaAQAs/GaAs)を用いた二次元
伝導現象を利用した]・ランジスタであって、GaAl
Asの酸化膜/GaA(lAs/GaAsの積層構造に
する。又、GaAQAsを直接酸化する。A transistor using two-dimensional conduction phenomenon using a heterojunction (GaAQAs/GaAs)
As oxide film/GaA (lAs/GaAs layered structure is formed. GaAQAs is directly oxidized.
その効果は次の通りすである。The effects are as follows.
(1) GaAQAsを酸化することで安定した膜が得
られる。(1) A stable film can be obtained by oxidizing GaAQAs.
(2) ゲート電極にゲート・リーク電流が流れること
が極めて小さく、従って論理振幅が大きくと九る。(2) Gate leakage current flowing through the gate electrode is extremely small, so the logic amplitude is large.
(3) ゲート酸化膜容量と空乏層容量とが直列に入り
、素子の入力容量が小さくでき、従って高速動作が出来
る。(3) Since the gate oxide film capacitance and the depletion layer capacitance are connected in series, the input capacitance of the device can be reduced, and therefore high-speed operation can be achieved.
(4) GaAQAs系の酸化膜は誘電率が大きく、ゲ
ート印加電圧での電圧損失が少ない。(4) A GaAQAs-based oxide film has a high dielectric constant and has little voltage loss at the gate applied voltage.
当然の事からアンドープGaAs2と半絶縁性G a
A s基板1との間にp型G a A sあるいはp型
GaAQAsを入れても、動作上は相異がなく、本発明
は適用される。Naturally, undoped GaAs2 and semi-insulating Ga
Even if p-type GaAs or p-type GaAQAs is inserted between the As substrate 1, there is no difference in operation and the present invention is applicable.
本発明は高速論理ICLSIを始めとして、マイクロ波
帯の低雑音増幅素子、高出力素子として応用できる。The present invention can be applied to high-speed logic ICLSI, low-noise amplification elements in the microwave band, and high-output elements.
又、他の材料としてInP基板上にアンドープr n
1−X A Q X A sに形成し、II型In1y
AQyAsを形成後、n型
I 111−y A Q y A sを酸化しても可能
である。In addition, as another material, undoped r n
1-X A Q X A s, type II In1y
It is also possible to oxidize the n-type I 111-y A Q y As after forming AQyAs.
第1図は本発明の半導体装置の断面図である。
■・・・半絶縁性G a A s基板、2・・・アンド
ープ又高純度G a A s、3− n十型GaAQA
s。
4− n型G a A s、5−AuGe−Ni系金属
、6.8・・・ソース、ドレイン電極の配線金属。
7・・・グー1〜金居、9・・・GaAQAsの酸化膜
。
藁1図FIG. 1 is a sectional view of a semiconductor device of the present invention. ■...Semi-insulating GaAs substrate, 2...Undoped or high purity GaAs, 3-n0 type GaAQA
s. 4-n-type GaAs, 5-AuGe-Ni metal, 6.8... Wiring metal for source and drain electrodes. 7...Goo 1~Kanai, 9...GaAQAs oxide film. Straw 1 diagram
Claims (1)
1の半導体層と、不純物を含有する第2の半導体層とが
、この第1と第2の半導体層の界面近傍に電子が貯蓄さ
れる如く積層され、この第2の半導体層上に絶踪物層を
介して電子の制御用電極およびこの制御用電極をはさん
で、前記第1の半導体層の前記第1と第2の半導体層の
界面近傍に貯蓄される電子と電気的に接続されたところ
の第1.第2電極を少なくとも有することを特徴とする
半導体装置。A first semiconductor layer that does not substantially contain impurities and a second semiconductor layer that contains impurities are formed on a predetermined semiconductor substrate so that electrons are formed near the interface between the first and second semiconductor layers. The first and second semiconductor layers of the first semiconductor layer are laminated so as to be stored, and an electrode for controlling electrons is sandwiched between the second semiconductor layer and the second semiconductor layer with the missing object layer interposed therebetween. The first point is electrically connected to the electrons stored near the interface of the semiconductor layer. A semiconductor device comprising at least a second electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3265385A JPS60196976A (en) | 1985-02-22 | 1985-02-22 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3265385A JPS60196976A (en) | 1985-02-22 | 1985-02-22 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60196976A true JPS60196976A (en) | 1985-10-05 |
Family
ID=12364821
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3265385A Pending JPS60196976A (en) | 1985-02-22 | 1985-02-22 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60196976A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7649215B2 (en) * | 2003-12-05 | 2010-01-19 | International Rectifier Corporation | III-nitride device passivation and method |
WO2020004198A1 (en) * | 2018-06-28 | 2020-01-02 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and high frequency module |
-
1985
- 1985-02-22 JP JP3265385A patent/JPS60196976A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7649215B2 (en) * | 2003-12-05 | 2010-01-19 | International Rectifier Corporation | III-nitride device passivation and method |
WO2020004198A1 (en) * | 2018-06-28 | 2020-01-02 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and high frequency module |
JPWO2020004198A1 (en) * | 2018-06-28 | 2021-07-08 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor devices and high frequency modules |
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