WO2020004198A1

WO2020004198A1 - Semiconductor device and high frequency module

Info

Publication number: WO2020004198A1
Application number: PCT/JP2019/024368
Authority: WO
Inventors: 孝紀東; 将志柳田
Original assignee: ソニーセミコンダクタソリューションズ株式会社
Priority date: 2018-06-28
Filing date: 2019-06-19
Publication date: 2020-01-02
Also published as: JP7345464B2; JPWO2020004198A1

Abstract

This semiconductor device comprises first and second transistors that are high-electron-mobility transistors. The plane area of a source electrode or drain electrode (140) of the first transistor (11) is larger than the plane area of a source electrode or drain electrode (140) of the second transistor (12), and the cross-sectional width of a contact layer (130) provided below the source electrode or drain electrode (140) of the first transistor (11) is of a size that corresponds to the cross-sectional width of a contact layer (130) provided below the source electrode or drain electrode (140) of the second transistor (12).

Description

Semiconductor device and high frequency module

The present disclosure relates to a semiconductor device and a high-frequency module.

A high electron mobility transistor (HEMT) using a heterojunction of a compound semiconductor has characteristics such as high withstand voltage, high heat resistance, high saturation electron velocity, and high channel electron concentration compared to other transistors. Have. Therefore, the high electron mobility transistor is expected to be applied to a small and high-performance power device or high-frequency device.

In such a high electron mobility transistor, a channel layer and a barrier layer formed of different compound semiconductors are heterojuncted to form a two-dimensional electron gas serving as a channel at an interface of the channel layer in contact with the barrier layer. I have. However, since the barrier layer has a high potential barrier and it is difficult to form a favorable ohmic contact, the high electron mobility transistor tends to have a high contact resistance.

Therefore, various methods for reducing the contact resistance of the high electron mobility transistor have been studied.

For example, in Patent Literature 1 below, a compound semiconductor layer having a small band gap is selectively regrown under a source electrode or a drain electrode, and a source electrode or a drain electrode and a two-dimensional electron gas are formed by the compound semiconductor layer. A technique for forming a contact is disclosed. According to the technique disclosed in Patent Literature 1, the ohmic characteristics between the source or drain electrode and the two-dimensional electron gas serving as the channel can be improved, so that the contact resistance of the high electron mobility transistor is reduced. can do.

JP 2011-159799 A

However, the growth rate and crystal quality of the compound semiconductor differ depending on the plane area on which the compound semiconductor is grown. Therefore, when a plurality of types of transistors having different source or drain areas are mixedly mounted on one chip or substrate, the crystal quality or the thickness of the regrown compound semiconductor layer may be different. In such a case, it has been difficult to obtain the same ohmic characteristics with a plurality of mixed transistors.

Therefore, there has been a demand for a technique capable of obtaining the same good contact resistance in any of the transistors having different source or drain areas.

According to the present disclosure, a channel layer formed of a first compound semiconductor, a barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor, and the barrier layer A gate electrode provided on the layer, a source electrode and a drain electrode provided on both sides of the gate electrode on the barrier layer, and the barrier layer below the source electrode and the drain electrode, respectively. And a contact layer provided therethrough. The source and drain electrodes of the first transistor each have a planar area equal to the source electrode of the second transistor. Alternatively, a cross section larger than a plane area of the drain electrode and cut by a straight line connecting the source electrode and the drain electrode of the first transistor. Width of the contact layer in is sized to correspond to the width of the contact layer in the source electrode and the section cut along a straight line connecting said drain electrode of said second transistor, a semiconductor device is provided.

Further, according to the present disclosure, a channel layer formed of a first compound semiconductor, a barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor, A gate electrode provided on the barrier layer, a source electrode and a drain electrode provided on both sides of the gate electrode with the gate electrode interposed therebetween, and the barrier electrode provided under the source electrode and the drain electrode, respectively. And a contact layer provided through the layer. The first and second transistors each have a contact layer, and the planar area of the source electrode or the drain electrode of the first transistor is the same as that of the second transistor. Cut by a straight line that is larger than the plane area of the source electrode or the drain electrode and that connects the source electrode and the drain electrode of the first transistor; The width of the contact layer in the cross section taken is a size corresponding to the width of the contact layer in a cross section cut by a straight line connecting the source electrode and the drain electrode of the second transistor. You.

According to the present disclosure, in the first transistor and the second transistor having different shapes or sizes, the areas of the contact layers are formed so as to correspond to each other. According to this, in each of the first transistor and the second transistor, the growth rate of the crystal of the contact layer can be made substantially the same.

According to the present disclosure as described above, it is possible to obtain the same good contact resistance in any of the transistors having different source and drain areas.

Note that the above effects are not necessarily limited, and any of the effects described in the present specification or other effects that can be grasped from the present specification, together with or instead of the above effects. May be played.

1 is a longitudinal sectional view illustrating an outline of a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a plan view and a longitudinal sectional view showing a planar structure and a sectional structure of a source or drain region SD2 in FIG. 1. 2A and 2B are a plan view and a longitudinal sectional view showing a planar structure and a sectional structure of a source or drain region SD1 in FIG. 4A and 4B are a vertical cross-sectional view and a plan view illustrating a specific cross-sectional structure and a specific planar structure of a first transistor. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIG. 4 is a longitudinal sectional view illustrating one step of a method for manufacturing a first transistor included in the semiconductor device according to the same embodiment. FIGS. 9A and 9B are a vertical cross-sectional view and a plan view illustrating a cross-sectional structure and a planar structure of a first transistor according to a first modification. FIGS. FIGS. 9A and 9B are a vertical cross-sectional view and a plan view illustrating a cross-sectional structure and a planar structure of a first transistor according to a second modification. FIGS. FIGS. 13A and 13B are a vertical cross-sectional view and a plan view illustrating a cross-sectional structure and a planar structure of a first transistor according to a third modification. FIGS. FIGS. 15A and 15B are a vertical cross-sectional view and a plan view illustrating a cross-sectional structure and a planar structure of a first transistor according to a fourth modification. FIGS. FIGS. 19A and 19B are a vertical cross-sectional view and a plan view illustrating a cross-sectional structure and a planar structure of a first transistor according to a fifth modification. FIGS. FIG. 3 is a schematic perspective view illustrating a high-frequency module to which the semiconductor device according to the same embodiment is applied.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the specification and the drawings, components having substantially the same functional configuration are denoted by the same reference numerals, and redundant description is omitted.

では In the drawings referred to in the following description, the size of some components may be exaggerated for convenience of explanation. Therefore, the relative sizes of the components illustrated in the drawings do not always accurately represent the magnitude relationship between the actual components. In the following description, the direction in which the substrate and the layers are stacked is referred to as an up-down direction, the direction in which the substrate is present is referred to as a down direction, and the direction facing the down direction is referred to as an up direction.

In this specification, the expression “substantially the same” allows the case where there is a difference due to a manufacturing or design factor, in addition to the case where they completely match. For example, the expression “substantially the same” may include a case where there is a difference of 10% or less, in addition to a case where there is a perfect match.

The description will be made in the following order.
1. Overview 2. Structure example 3. 3. Manufacturing method Modification 5. Application example

<1. Overview>
First, an overview of a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS. FIG. 1 is a longitudinal sectional view showing an outline of the semiconductor device according to the present embodiment.

As shown in FIG. 1, the semiconductor device according to the present embodiment includes a first transistor 11 and a second transistor 12 having different shapes or sizes from each other. Specifically, the first transistor 11 includes a substrate 110, a channel layer 111, a barrier layer 113, a gate insulating film 121, a gate electrode 120, a source or drain electrode 140, and a contact layer 130. Prepare. The second transistor 12 includes a substrate 110, a channel layer 111, a barrier layer 113, a gate insulating film 121, a gate electrode 220, a source or drain electrode 240, and a contact layer 230. The first transistor 11 and the second transistor 12 are high electron mobility transistors in which a high mobility two-dimensional electron gas 150 is formed at an interface between the channel layer 111 and the barrier layer 113.

In the following, the semiconductor device according to the present embodiment is described as including two types of high electron mobility transistors having different shapes or sizes from each other, but the present embodiment is not limited to this example. The semiconductor device according to the present embodiment may include three or more types of high electron mobility transistors having different shapes or sizes.

The high electron mobility transistor will be described below with reference to the second transistor 12 as an example. Note that the gate electrode 120, the source or drain electrode 140, and the contact layer 130 are substantially the same as the gate electrode 220, the source or drain electrode 240, and the contact layer 230 except that the shape or size is different.

In the following, the second transistor 12 will be described as a high electron mobility transistor having a so-called MIS (Metal-Insulator-Semiconductor) gate structure, but the present embodiment is not limited to this example. The gate structure of the second transistor 12 may be any known gate structure.

The substrate 110 is a substrate on which each layer of the first transistor 11 or the second transistor 12 is stacked. The substrate 110 may be, for example, a substrate formed of a compound semiconductor. The substrate 110 may be a substrate used for a general semiconductor device such as a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a sapphire substrate.

The channel layer 111 is formed using the first compound semiconductor and is provided over the substrate 110. A two-dimensional electron gas 150 in which electrons travel with high mobility is formed in the channel layer 111 due to a difference in polarization charge amount from the barrier layer 113. The channel layer 111 may be formed of, for example, a nitride semiconductor.

The barrier layer 113 is formed of a second compound semiconductor different from the first compound semiconductor, and is provided on the channel layer 111. The barrier layer 113 accumulates electrons in the channel layer 111 due to a difference in polarization charge amount from the channel layer 111, and forms a two-dimensional electron gas 150 in the channel layer 111. The barrier layer 113 may be formed of, for example, a nitride semiconductor different from the channel layer 111.

(4) The gate insulating film 121 is formed of an insulating dielectric and provided on the barrier layer 113. Specifically, the gate insulating film 121 is provided over the barrier layer 113 in a region excluding a region where the source or drain electrode 240 is provided. The gate insulating film 121 may be formed of, for example, an inorganic oxide or an inorganic nitride.

(4) The gate electrode 220 is formed of a conductive material and provided on the gate insulating film 121. Specifically, the gate electrode 220 may be configured by, for example, stacking a plurality of metal materials.

The source or drain electrode 240 is formed of a conductive material, and is provided on the barrier layer 113 on both sides of the gate electrode 220. One of the source or drain electrodes 240 is a source electrode with the gate electrode 220 interposed therebetween, and the other is a drain electrode. The source or drain electrode 240 is electrically connected to the two-dimensional electron gas 150 formed in the channel layer 111 via a contact layer 230 provided below the source or drain electrode 240. The source or drain electrode 240 may be configured by, for example, stacking a plurality of metal materials.

The contact layer 230 is formed of a compound semiconductor into which a conductive impurity is introduced, and is provided below the source or drain electrode 240 so as to reach the channel layer 111 through the barrier layer 113. Specifically, the contact layer 230 is formed of the same compound semiconductor as the channel layer 111 or a compound semiconductor having a small band gap with the channel layer 111 so that the contact layer 230 is in contact with the two-dimensional electron gas 150 of the channel layer 111. Decrease contact resistance. For example, the contact layer 230 may be formed of a nitride semiconductor like the channel layer 111. In addition, the contact layer 230 lowers the contact resistance with the source or drain electrode 240 by introducing a conductive impurity at a high concentration. Accordingly, the contact layer 230 can form a current path from the source or drain electrode 240 to the two-dimensional electron gas 150. For example, in the contact layer 230, after the barrier layer 113 and a part of the channel layer 111 are removed by etching to form an opening, the compound semiconductor is recrystallized while adding a conductive impurity into the opening. It can be formed by growing.

では In the semiconductor device according to the present embodiment, the first transistor 11 and the second transistor 12 are formed so as to have different shapes or sizes from each other. Specifically, the first transistor 11 is formed so that the source or drain electrode 140, the gate electrode 120, and the channel length are increased in order to reduce power loss when a large current flows. On the other hand, the second transistor 12 is formed so that the source or drain electrode 240, the gate electrode 220, and the channel length are reduced in order to reduce signal loss due to parasitic capacitance.

Therefore, the first transistor 11 is provided at, for example, about several tens of μm, and the second transistor 12 is provided at, for example, about several μm. In such a case, the size of the region where the source or drain electrode 140 of the first transistor 11 is provided and the size of the region where the source or drain electrode 240 of the second transistor 12 is provided greatly differ.

Here, the contact layers 130 and 230 are formed by crystal regrowth of the compound semiconductor, and the crystal growth rate in the crystal regrowth increases as the area of the area decreases. This is because the crystal growth rate in the crystal regrowth of the compound semiconductor depends on the supply amount of the raw material. Therefore, when a contact layer is simultaneously formed in regions having different areas by crystal regrowth, the thickness of the formed contact layer, crystal quality, and connectivity at the interface with the channel layer 111 form the contact layer. It depends on the area of the region.

In such a case, the contact layers having different thicknesses, crystal qualities, and connectivity at the interface with the channel layer 111 have different contact resistances with the channel layer 111. In addition, since these contact layers have different thicknesses, the amount of the conductive impurity introduced is also different, and the contact resistance with the source or drain electrode is also different. Therefore, when the contact layers 130 and 230 are simultaneously formed by crystal regrowth in the regions below the source or drain electrodes 140 and the source or drain electrodes 240 having different areas, the first transistor 11 and the second transistor 12 are formed. Will be different from each other. According to this, there is a high possibility that a desired contact resistance cannot be achieved with either the first transistor 11 or the second transistor 12.

In the semiconductor device according to the present embodiment, in the first transistor 11 and the second transistor 12 having different shapes or sizes, the areas of the contact layers 130 and 230 are formed to have sizes corresponding to each other. Specifically, the contact layer 130 formed below the source or drain electrode 140 is formed in a part of the region where the source or drain electrode 140 is formed, and has approximately the same ohmic width as the contact layer 230. It is formed as follows. Thus, in the semiconductor device according to the present embodiment, the contact layers 130 and 230 of the first transistor 11 and the second transistor 12 can be formed to have the same thickness, crystal quality, and the like.

Here, the ohmic width indicates the width of the contact layer in a cross section obtained by cutting the transistor with a straight line connecting each of the source and drain electrodes. Alternatively, when the source or drain electrode is formed in a straight line or a broken line shape, the ohmic width may represent a width in a direction orthogonal to a direction in which the contact layer extends. Note that, in the following, a straight extending direction connecting each of the source or drain

electrodes

140 and 240 is also referred to as a channel direction.

According to the present embodiment, even when the first transistor 11 and the second transistor 12 having different shapes or sizes are mixedly mounted, the semiconductor device can achieve the same appropriate contact resistance for each. It is.

When the semiconductor device according to this embodiment includes three or more types of transistors having different shapes or sizes, the ohmic width of the contact layer of each transistor is substantially equal to the ohmic width of the contact layer of the smallest transistor. It can be formed to be the same.

Here, the planar structure of the contact layer 130 of the first transistor 11 and the planar structure of the contact layer 230 of the second transistor 12 will be described more specifically with reference to FIGS. 2A and 2B. 2A is a plan view and a longitudinal sectional view showing a planar structure and a sectional structure of the source or drain region SD2 of FIG. 1, and FIG. 2B is a plan view showing a planar structure and a sectional structure of the source or drain region SD1 of FIG. It is a figure and a longitudinal cross-sectional view. 2A and 2B are cross-sectional views taken along line AAA of the plan views of the upper part of FIGS. 2A and 2B.

As shown in FIG. 2A, in the second transistor 12, the source or drain electrode 240 is formed in a rectangular planar shape extending in a direction orthogonal to the channel direction, and is provided below the source or drain electrode 240. The contact layer 230 is formed in a region corresponding to the region where the source or drain electrode 240 is formed. For example, the contact layer 230 may be formed in a region having substantially the same size as a region where the source or drain electrode 240 is formed. At this time, assuming that the width in the channel direction of the source or drain electrode 240 determined by the characteristics of the second transistor 12 is w2, the ohmic width of the contact layer 230 (the width of the contact layer 230 in the channel direction) is w2. , The width of the source or drain electrode 240 in the channel direction is substantially the same.

On the other hand, as shown in FIG. 2B, in the first transistor 11, the source or drain electrode 140 is formed in a rectangular planar shape extending in the channel direction, and a contact layer provided below the source or drain electrode 140. 130 is formed in a part of the region where the source or drain electrode 140 is formed. For example, the source or drain electrode 140 may be formed in a hollow rectangular shape along the outer periphery of the source or drain electrode 140. At this time, assuming that the width of the source or drain electrode 140 in the channel direction determined by the characteristics of the first transistor 11 is w1, the ohmic width of the contact layer 130 formed in a hollow rectangular shape is ws1 smaller than w1. It becomes.

Here, by forming the contact layer 130 with the ohmic width ws1 of the contact layer 130 being substantially the same as the ohmic width w2 of the contact layer 230 of the second transistor 12, the crystal growth speed can be reduced. Can be substantially the same as As a result, the semiconductor device according to the present embodiment can control the contact resistance of the first transistor 11 and the second transistor 12 that are mounted together at the same level. However, the length of the source or

drain electrode

140, 240 in the direction orthogonal to the channel direction is the same for the first transistor 11 and the second transistor 12.

Note that the contact layer 130 of the first transistor 11 may have various planar shapes other than the hollow rectangular shape shown in FIG. 2B. That is, the planar shape of the contact layer 130 of the first transistor 11 may be any shape as long as the crystal growth rate can be made substantially the same as that of the contact layer 230 of the second transistor 12. For example, the planar shape of the contact layer 130 of the first transistor 11 may be a shape obtained by modifying or combining a plurality of planar shapes of the contact layer 230 of the second transistor 12.

<2. Structure example>
Subsequently, a specific structure example of the first transistor 11 provided in the semiconductor device according to the present embodiment will be described with reference to FIG. FIG. 3 is a longitudinal sectional view and a plan view showing a specific sectional structure and a planar structure of the first transistor 11. The upper cross-sectional view of FIG. 3 shows a cross section taken along line AAA of the lower plan view of FIG.

As shown in FIG. 3, the first transistor 11 includes a substrate 110, a buffer layer 115, a channel layer 111, a barrier layer 113, a gate insulating film 121, a gate electrode 120, a source or drain electrode 140, , And a contact layer 130. Although not illustrated, the first transistor 11 is assumed to be mounted on the same substrate 110 as the second transistor 12 having a smaller planar area than the first transistor 11.

Note that the first transistor 11 is electrically insulated from other transistors (for example, the second transistor 12 and the like) by the element isolation region 117. The element isolation region 117 may be formed by, for example, increasing the resistance of the channel layer 111 and the barrier layer 113 by introducing boron (B), and removing the channel layer 111 and the barrier layer 113 by etching or the like. It may be formed.

The substrate 110 is a support for each component of the first transistor 11. The substrate 110 may be a substrate formed of a compound semiconductor, and more specifically, may be a substrate formed of a III-V compound semiconductor. For example, the substrate 110 may be a single-crystal gallium nitride (GaN) substrate having a semi-insulating property. However, by providing the buffer layer 115 described later, the substrate 110 does not have to have a lattice constant substantially equal to that of the channel layer 111. In such a case, as the substrate 110, a substrate formed of a material having a different lattice constant from the channel layer 111 such as silicon (Si), silicon carbide (SiC), or sapphire can be used.

The buffer layer 115 is formed of a compound semiconductor and provided on the substrate 110. Specifically, the buffer layer 115 is formed by epitaxially growing a compound semiconductor having a lattice constant close to that of the first compound semiconductor forming the channel layer 111 on the substrate 110. The buffer layer 115 can improve the crystal state of the channel layer 111 by controlling the lattice constant of the surface on which the channel layer 111 is formed, and can reduce the warpage of the substrate 110 after the channel layer 111 is formed. Can be controlled. For example, when the substrate 110 is formed of silicon and the channel layer 111 is formed of GaN, the buffer layer 115 may be formed of AlN, AlGaN, or GaN.

The channel layer 111 is formed using the first compound semiconductor and is provided over the buffer layer 115. The channel layer 111 accumulates electrons serving as carriers due to a difference in polarization charge amount from the barrier layer 113. Thus, a two-dimensional electron gas 150 functioning as a channel is formed in the channel layer 111. The channel layer 111 may be a layer formed of a nitride semiconductor, for example, epitaxial growth of Al _1-ab Ga _a In _b N (where 0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1). It may be a layer.

The barrier layer 113 is formed using a second compound semiconductor different from the first compound semiconductor, and is provided over the channel layer 111. The barrier layer 113 causes carriers serving as carriers to be accumulated in the channel layer 111 due to a difference in polarization charge amount from the channel layer 111. Barrier layer 113 may be a layer formed of a different nitride semiconductor as a channel layer 111, for _{_{example, Al 1-c-d Ga}} c In d N ( However, 0 ≦ c ≦ 1,0 ≦ d ≦ 1, The epitaxial growth layer may satisfy c + d ≦ 1, (c, d) ≠ (a, b)).

The barrier layer 113, impurities are not added (i.e., _undoped) may be formed of _{_{Al 1-c-d Ga c}} In d N. In such a case, the barrier layer 113 can suppress impurity scattering of electrons in the channel layer 111, so that the mobility of the two-dimensional electron gas 150 can be further increased.

The gate insulating film 121 is formed of a dielectric having an insulating property, and is provided on the barrier layer 113. Specifically, the gate insulating film 121 is provided over the barrier layer 113 in a region excluding a region where the source or drain electrode 240 is provided. For example, the gate insulating film 121 may be formed of a dielectric having an insulating property with respect to the barrier layer 113 and the gate electrode 120, and may be formed of SiO ₂ , Si ₃ N _4, Al ₂ O ₃ , HfO ₂ , or the like. May be done.

The gate electrode 120 is formed of a conductive material and provided on the gate insulating film 121. Specifically, the gate electrode 120 is provided so as to cross the gate insulating film 121 from one element isolation region 117 to the other element isolation region 117. For example, the gate electrode 120 may be formed by, for example, sequentially stacking nickel (Ni) and gold (Au) from the gate insulating film 121 side.

The source or drain electrode 140 is provided on both sides of the gate electrode 120 on the barrier layer 113. One of the source or drain electrodes 140 is a source electrode with the gate electrode 120 interposed therebetween, and the other is a drain electrode. The source or drain electrode 140 is electrically connected to a two-dimensional electron gas 150 formed in the channel layer 111 through a contact layer 130 provided in a partial region below the source or drain electrode 140. The source or drain electrode 140 may be formed, for example, by sequentially stacking titanium (Ti), A aluminum (Al), nickel (Ni), and gold (Au) from the barrier layer 113 side.

The contact layer 130 is formed of a compound semiconductor into which a conductive impurity is introduced, and is provided below the source or drain electrode 140 so as to reach the channel layer 111 through the barrier layer 113. Specifically, the contact layer 130 is formed using the same compound semiconductor as the channel layer 111 or a compound semiconductor having a small difference in band gap from the channel layer 111 so that the channel layer 111 can be in contact with the two-dimensional electron gas 150. Decrease resistance. In addition, the contact layer 130 lowers the contact resistance with the source or drain electrode 140 by introducing a conductive impurity at a high concentration. Specifically, contact layer 130 may be formed of a nitride semiconductor into which an n-type impurity has been introduced. For example, the contact layer 130 is formed by forming an epitaxial layer of Al _1-ab Ga _a In _b N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1) on silicon (Si) or germanium (Ge). Or the like may be introduced at 1 × 10 ¹⁸ / cm ³ or more.

The contact layer 130 is provided in a partial region below the source or drain electrode 140 in a planar shape based on the planar shape of the contact layer 230 of the second transistor 12. Specifically, the contact layer 130 may be provided in a hollow rectangular shape along the outer periphery of the region where the source or drain electrode 140 is formed. The difference between the outer diameter and the inner diameter of the hollow rectangular shape, which is the planar shape of the contact layer 130 (ie, the width of the frame shape), is substantially the same as the width of the contact layer 230 of the second transistor 12 in the channel direction. It may be. According to this, the contact layer 130 can have a crystal growth rate substantially equal to that of the contact layer 230 of the second transistor 12. Therefore, in the semiconductor device, the first transistor 11 and the second transistor 12 can be formed with approximately the same contact resistance.

However, the contact layer 130 may be provided at least in a region facing the gate electrode 120 in a region where the source or drain electrode 140 is formed. Specifically, when the source or drain electrode 140 is formed in a rectangular shape, the contact layer 130 may be provided at least on a side of the rectangular shape of the source or drain electrode 140 facing the gate electrode 120. The channel length of the first transistor 11 is determined by the distance at which each of the contact layers 130 connects to the two-dimensional electron gas 150. Therefore, according to this configuration, the first transistor 11 can control the channel length formed between one and the other of the source or drain electrode 140 with higher accuracy.

In FIG. 3, the contact layer 130 penetrates through the barrier layer 113 and is formed up to the inside of the channel layer 111 so as to fill a recess formed in the channel layer 111. However, the structure of the first transistor 11 Is not limited to such an example. For example, the contact layer 130 may be provided on the surface of the channel layer 111 on which the barrier layer 113 is provided. That is, no concave portion is formed in the channel layer 111, and the contact layer 130 may be provided on one main surface of the channel layer 111, similarly to the barrier layer 113.

{Circle around (2)} The two-dimensional electron gas 150 serving as a channel in the first transistor 11 is formed at the interface between the barrier layer 113 and the channel layer 111. Therefore, if the contact layer 130 is provided on one main surface of the channel layer 111 as in the case of the barrier layer 113, the contact layer 130 can be electrically connected to the two-dimensional electron gas 150 at the bottom surface.

According to the first transistor 11 having the above structure, the semiconductor device according to the present embodiment can obtain the same good contact resistance with any of the transistors having different planar areas.

<3. Manufacturing method>
Next, a method for manufacturing the first transistor 11 included in the semiconductor device according to the present embodiment will be described with reference to FIGS. 4A to 4H. 4A to 4H are vertical cross-sectional views illustrating each step of the method for manufacturing the first transistor 11 provided in the semiconductor device according to the present embodiment.

First, as shown in FIG. 4A, a buffer layer 115, a channel layer 111, a barrier layer 113, and an insulating layer 160 are sequentially stacked on a substrate 110 formed of silicon or the like.

Specifically, the buffer layer 115 is formed by epitaxially growing AlN, AlGaN, or GaN on the substrate 110 formed of silicon or the like. Next, the channel layer 111 is formed by epitaxially growing GaN on the buffer layer 115 without adding an impurity. Subsequently, the barrier layer 113 is formed by epitaxially growing AlInN on the channel layer 111. After that, the insulating layer 160 is formed of SiO ₂ on the barrier layer 113 by using CVD (Chemical Vapor Deposition) or the like.

(4) Next, as shown in FIG. 4B, an opening 161 is formed by patterning the insulating layer 160, the barrier layer 113, and the channel layer 111.

Specifically, after a resist patterned by photolithography is formed on the insulating layer 160, the barrier layer 113 and the channel layer 111 are wet-etched or dry-etched using the resist as a mask. Thus, an opening 161 can be formed in the insulating layer 160, the barrier layer 113, and the channel layer 111. Note that, at this time, a recess structure may be formed in the outer peripheral region by etching the outer peripheral region of the region serving as the source or drain of the first transistor 11.

Subsequently, as shown in FIG. 4C, a contact layer 130 is selectively formed on the channel layer 111 inside the opening 161.

Specifically, the contact layer 130 is epitaxially grown on the channel layer 111 inside the opening 161 using the insulating layer 160 formed on the barrier layer 113 as a mask. At this time, the contact layer 130 may be formed of GaN similarly to the channel layer 111. Such epitaxial growth of the contact layer 130 is also called crystal regrowth. The introduction of the n-type impurity into the contact layer 130 may be performed by performing epitaxial growth while incorporating an n-type impurity such as Si or Ge at the time of crystal regrowth. Alternatively, the introduction of the n-type impurity into the contact layer 130 may be performed by ion-implanting an n-type impurity such as Si or Ge after crystal regrowth. Note that the concentration of the n-type impurity introduced into the contact layer 130 may be, for example, 1 × 10 ¹⁸ / cm ³ or more.

The regrowth of the crystal of the contact layer 130 is performed under the condition that an etching gas or the like is not used. In normal deposition such as CVD, the deposition rate can be controlled for each deposition region by using an etching gas or the like. However, in the crystal regrowth of the contact layer 130 where it is important to grow a crystal epitaxially, etching is performed. It is difficult to adjust with gas or the like. Therefore, in the semiconductor device according to this embodiment, the growth rate of the crystal of the contact layer 130 is controlled by the planar shape of the contact layer 130.

Next, as shown in FIG. 4D, the insulating layer 160 is removed by wet etching or dry etching.

(4) Subsequently, as shown in FIG. 4E, a source or drain electrode 140 is formed on the contact layer 130 and in a region to be a source or a drain of the first transistor 11.

{Specifically, the source or drain electrode 140 is formed by sequentially stacking Ti, Al, Ni, and Au in a region to be a source or a drain of the first transistor 11. After that, although not shown, an element isolation region 117 is formed around the first transistor 11 to electrically insulate the first transistor 11 from other transistors (for example, the second transistor 12 and the like). The element isolation region 117 may be formed by, for example, introducing boron (B) by ion implantation and increasing the resistance of the barrier layer 113 and the channel layer 111 formed of a compound semiconductor. The element isolation region 117 may be formed by, for example, removing the barrier layer 113 and the channel layer 111 by dry etching.

Next, as shown in FIG. 4F, the gate insulating film 121 is formed uniformly over the source or drain electrode 140 and the barrier layer 113. The gate insulating film 121 may be formed of, for example, Al ₂ O ₃ or may be formed of a stacked structure of a plurality of dielectrics or insulating materials.

4G, a gate electrode 120 is formed on the gate insulating film 121 as shown in FIG. 4G. Specifically, the gate electrode 120 is formed by sequentially stacking Ni and Au on the gate insulating film 121 between the source or drain electrodes 140.

(4) Thereafter, as shown in FIG. 4H, the gate insulating film 121 formed on the source or drain electrode 140 is removed. Specifically, the source or drain electrode 140 is exposed by removing the gate insulating film 121 formed over the source or drain electrode 140 by wet etching or dry etching.

According to the above steps, the first transistor 11 provided in the semiconductor device according to the present embodiment can be manufactured.

<4. Modification>
Subsequently, a modification of the structure of the first transistor 11 provided in the semiconductor device according to the present embodiment will be described with reference to FIGS. 5 to 9 are a longitudinal sectional view and a plan view showing a sectional structure and a planar structure of a first transistor according to first to fifth modifications, respectively. 5 to 9 are cross-sectional views taken along line A-AA of the plan views in the lower part of FIGS. 5 to 9, respectively.

(First Modification)
As shown in FIG. 5, in the first transistor 11A, the source or drain electrode 141 is patterned similarly to the contact layer 130, and the source or drain electrode 141 is provided in a planar shape corresponding to the contact layer 130. obtain. That is, the first transistor 11A is different from the first transistor 11 shown in FIG. 3 in that the source or drain electrode 141 is formed only on the contact layer 130.

Specifically, the source or drain electrode 141 is provided in a hollow rectangular planar shape, and the contact layer 130 is provided in a hollow rectangular planar shape like the source or drain electrode 141. At this time, the difference between the outer diameter and the inner diameter of the hollow rectangular shape of the source or drain electrode 141 and the contact layer 130 (that is, the width of the frame shape) depends on the channel direction of the contact layer 230 of the second transistor 12. It is almost the same as the width.

Even in such a case, the ohmic width of the contact layer 130 can be made substantially the same as the ohmic width of the contact layer 230 of the second transistor 12, so that the crystal growth rate can be reduced. Can be substantially the same as Therefore, the contact resistance of the contact layer 130 can be substantially the same as that of the contact layer 230 of the second transistor 12.

According to the first modification, since the source or drain electrode 141 is not provided on the barrier layer 113, it is possible to suppress occurrence of an unintended leak current from the source or drain electrode 141. Further, according to the first modification, it is possible to prevent the occurrence of resistance or loss between the source or drain electrode 141 and the barrier layer 113.

(Second Modification)
As shown in FIG. 6, in the first transistor 11B, the contact layer 131 is provided in a partial region below the source or drain electrode 140 in a plurality of rectangular planar shapes extending in a direction orthogonal to the channel direction. Can be That is, the first transistor 11B is different from the first transistor 11 shown in FIG. 3 in that the planar shape of the contact layer 131 is different.

Specifically, the contact layer 131 can be provided in three rectangular planar shapes extending in a direction orthogonal to the channel direction. At this time, the width of the contact layer 131 in the channel direction may be substantially the same as the width of the contact layer 230 of the second transistor 12 in the channel direction. That is, one rectangular shape of the planar shape of the contact layer 131 may be substantially the same as the planar shape of the contact layer 230 of the second transistor 12.

Even in such a case, the ohmic width of the contact layer 131 can be made substantially the same as the ohmic width of the contact layer 230 of the second transistor 12, so that the crystal growth rate can be reduced. Can be substantially the same as Therefore, the contact resistance of the contact layer 131 can be substantially the same as that of the contact layer 230 of the second transistor 12.

According to the second modification, since the planar shape of the contact layer 131 is formed by a combination of the planar shape of the contact layer 230 of the second transistor 12, the crystal growth rate of the contact layer 131 is reduced by the second transistor 12. Can be made more consistent with the contact layer 230 of FIG. Therefore, according to the second modification, it is possible to make the contact resistances of the first transistor 11 and the second transistor 12 more consistent.

(Third Modification)
As shown in FIG. 7, in the first transistor 11C, the source or drain electrode 142 is patterned similarly to the contact layer 131, and the source or drain electrode 142 is provided in a planar shape corresponding to the contact layer 131. obtain. That is, the first transistor 11C is different from the first transistor 11B shown in FIG. 6 in that the source or drain electrode 142 is formed only on the contact layer 131.

Specifically, the source or drain electrode 142 is provided in a plurality of rectangular planar shapes extending in a direction orthogonal to the channel direction, and the contact layer 131 is orthogonal to the channel direction like the source or drain electrode 142. It is provided in a plurality of rectangular planar shapes extending in the direction. At this time, the width of the source or drain electrode 142 and the contact layer 131 in the channel direction may be substantially the same as the width of the contact layer 230 of the second transistor 12 in the channel direction. That is, one of the planar shapes of the source or drain electrode 142 and the contact layer 131 may be substantially the same as the planar shape of the contact layer 230 of the second transistor 12.

According to the third modification, since the source or drain electrode 142 is not provided on the barrier layer 113, it is possible to suppress the occurrence of an unintended leak current from the source or drain electrode 142. Further, according to the third modification, it is possible to prevent the occurrence of resistance or loss between the source or drain electrode 142 and the barrier layer 113.

(Fourth modification)
As shown in FIG. 8, in the first transistor 11D, the contact layer 132 is provided in a partial region below the source or drain electrode 140 in a plurality of rectangular planar shapes extending in a direction orthogonal to the channel direction. Can be That is, the first transistor 11D is different from the first transistor 11 shown in FIG. 3 in that the planar shape of the contact layer 132 is different.

Specifically, the contact layer 132 can be provided in two rectangular planar shapes extending in a direction orthogonal to the channel direction. More specifically, the contact layer 132 may be provided in two rectangular shapes along two sides of the rectangular shape of the source or drain electrode 140 in the channel direction. At this time, the width of the contact layer 132 in the channel direction may be substantially the same as the width of the contact layer 230 of the second transistor 12 in the channel direction. That is, one rectangular shape of the planar shape of the contact layer 132 may be substantially the same as the planar shape of the contact layer 230 of the second transistor 12.

Even in such a case, since the ohmic width of the contact layer 132 can be made substantially the same as the ohmic width of the contact layer 230 of the second transistor 12, the crystal growth rate can be reduced. Can be substantially the same as Therefore, the contact resistance of the contact layer 132 can be substantially the same as that of the contact layer 230 of the second transistor 12.

According to the fourth modification, since the planar shape of the contact layer 132 is formed by a combination of the planar shape of the contact layer 230 of the second transistor 12, the crystal growth rate of the contact layer 132 is reduced. Can be made more consistent with the contact layer 230 of FIG. Therefore, according to the fourth modification, it is possible to make the contact resistances of the first transistor 11 and the second transistor 12 more consistent.

(Fifth Modification)
As shown in FIG. 9, in the first transistor 11E, the source or drain electrode 143 is patterned similarly to the contact layer 132, and the source or drain electrode 143 is provided in a planar shape corresponding to the contact layer 132. obtain. That is, the first transistor 11E is different from the first transistor 11D shown in FIG. 8 in that the source or drain electrode 143 is formed only on the contact layer 132.

Specifically, the source or drain electrode 143 is provided in two rectangular planar shapes extending in a direction orthogonal to the channel direction, and the contact layer 132 is orthogonal to the channel direction similarly to the source or drain electrode 143. Are provided in a plurality of rectangular planar shapes extending in the direction in which they extend. At this time, the width of the source or drain electrode 143 and the contact layer 132 in the channel direction may be substantially the same as the width of the contact layer 230 of the second transistor 12 in the channel direction. That is, one of the planar shapes of the source or drain electrode 143 and the contact layer 132 may be substantially the same as the planar shape of the contact layer 230 of the second transistor 12.

According to the fifth modification, since the source or drain electrode 143 is not provided on the barrier layer 113, the occurrence of an unintended leak current from the source or drain electrode 143 can be suppressed. Further, according to the fifth modification, it is possible to prevent the occurrence of resistance or loss between the source or drain electrode 143 and the barrier layer 113.

<5. Application example>
Next, a high-frequency module to which the semiconductor device according to the present embodiment is applied will be described with reference to FIG. FIG. 10 is a schematic perspective view illustrating a high-frequency module to which the semiconductor device according to the present embodiment is applied.

As shown in FIG. 10, the high-frequency module 1 includes, for example, an edge antenna 20, a driver 31, a phase adjustment circuit 32, a switch 10, a low-noise amplifier 41, a band-pass filter 42, a power amplifier 43, Is provided.

The high-frequency module 1 is an antenna in which an edge antenna 20 formed in an array and front-end components such as a switch 10, a low-noise amplifier 41, a band-pass filter 42, and a power amplifier 43 are integrally mounted as one module. It is an integrated module. Such a high-frequency module 1 can be used, for example, as a transceiver for communication. The transistors included in the switch 10, the low-noise amplifier 41, the power amplifier 43, and the like included in the high-frequency module 1 may be configured by, for example, high electron mobility transistors in order to increase the gain at high frequencies.

Here, the transistors constituting the switch 10 and the low-noise amplifier 41 can be formed smaller to reduce signal loss. Also, the transistors constituting the control IC (Integrated @ Circuit) of the high-frequency module 1 can be formed smaller to reduce the power consumption. For example, such a transistor can be formed on the order of several μm.

On the other hand, the transistor constituting the power amplifier 43 can be formed larger to reduce power loss when a large current flows. For example, such a transistor can be formed on the order of tens of μm.

That is, the high-frequency module 1 may include high electron mobility transistors of different sizes mixedly. By applying the semiconductor device according to the present embodiment to such a high-frequency module 1, it is possible to realize good contact resistance in each of transistors formed simultaneously on one chip and having different sizes. is there.

Although the preferred embodiments of the present disclosure have been described above in detail with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is apparent that a person having ordinary knowledge in the technical field of the present disclosure can conceive various changes or modifications within the scope of the technical idea described in the claims. It is understood that also belongs to the technical scope of the present disclosure.

効果 In addition, the effects described in this specification are merely illustrative or exemplary, and are not restrictive. That is, the technology according to the present disclosure can exhibit other effects that are obvious to those skilled in the art from the description in the present specification, in addition to or instead of the above effects.

For example, in the above embodiment, the semiconductor device includes the first transistor 11 and the second transistor 12 having different shapes or sizes from each other, but the technology according to the present disclosure is not limited to such an example. The semiconductor device according to the present embodiment may include a transistor having a single shape or size. Even in such a case, the semiconductor device according to the present embodiment can obtain the favorable contact resistance as described above by patterning the planar shape of the contact layer of the transistor as described above.

The following configuration also belongs to the technical scope of the present disclosure.
(1)
A channel layer formed of the first compound semiconductor;
A barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor;
A gate electrode provided on the barrier layer,
Source and drain electrodes provided on both sides of the gate electrode on the barrier layer,
Contact layers provided under the source electrode and the drain electrode, respectively, through the barrier layer;
And a first and a second transistor respectively having
The planar area of the source electrode or the drain electrode of the first transistor is larger than the planar area of the source electrode or the drain electrode of the second transistor,
A width of the contact layer in a cross section cut by a straight line connecting the source electrode and the drain electrode of the first transistor is a cross section cut by a straight line connecting the source electrode and the drain electrode of the second transistor. A semiconductor device having a size corresponding to the width of the contact layer.
(2)
The semiconductor device according to (1), wherein the width of the contact layer of the first transistor is substantially the same as the width of the contact layer of the second transistor.
(3)
The semiconductor device according to (1) or (2), wherein the source electrode or the drain electrode of the second transistor is provided in a single rectangular shape.
(4)
The semiconductor device according to any one of (1) to (3), wherein the contact layer of the first transistor is provided in a part of a planar region where the source electrode or the drain electrode is provided. .
(5)
The semiconductor device according to (4), wherein the contact layer of the first transistor is provided in a part of the source electrode or the drain electrode facing the gate electrode.
(6)
(4) or (5), wherein the planar shape of the contact layer of the first transistor is a hollow rectangular shape provided along an outer periphery of a planar region provided with the source electrode or the drain electrode. 3. The semiconductor device according to claim 1.
(7)
The semiconductor according to (4) or (5), wherein the planar shape of the contact layer of the first transistor is a plurality of rectangular shapes extending in a direction orthogonal to a straight line connecting the source electrode and the drain electrode. apparatus.
(8)
The semiconductor device according to any one of (1) to (3), wherein the contact layer of the first transistor is provided in a plane region where the source electrode or the drain electrode is provided.
(9)
The semiconductor device according to (8), wherein a planar shape of the source electrode or the drain electrode of the first transistor is a hollow rectangular shape.
(10)
The semiconductor according to (8), wherein the planar shape of the source electrode or the drain electrode of the first transistor is a plurality of rectangular shapes extending in a direction orthogonal to a straight line connecting the source electrode and the drain electrode. apparatus.
(11)
The semiconductor device according to any one of (1) to (10), wherein the first compound semiconductor and the second compound semiconductor are nitride semiconductors.
(12)
The semiconductor device according to any one of (1) to (11), wherein the contact layers of the first and second transistors are formed of a compound semiconductor into which a conductive impurity is introduced.
(13)
The semiconductor device according to any one of (1) to (12), wherein the contact layers of the first and second transistors are provided on a surface of the channel layer on which the barrier layer is provided.
(14)
The contact layer of any of (1) to (12), wherein the contact layer of the first and second transistors is provided so as to fill a recess formed in a surface of the channel layer on which the barrier layer is provided. 13. The semiconductor device according to item 9.
(15)
The semiconductor according to any one of (1) to (14), wherein the contact layer of the first and second transistors is provided so as to contact an interface between the barrier layer and the channel layer on a side surface. apparatus.
(16)
The semiconductor device according to (1), wherein the gate electrode is provided on the barrier layer via a gate insulating film.
(17)
A channel layer formed of the first compound semiconductor;
A barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor;
A gate electrode provided on the barrier layer,
Source and drain electrodes provided on both sides of the gate electrode on the barrier layer,
Contact layers provided under the source electrode and the drain electrode, respectively, through the barrier layer;
And a first and a second transistor respectively having
The planar area of the source electrode or the drain electrode of the first transistor is larger than the planar area of the source electrode or the drain electrode of the second transistor,
A width of the contact layer in a cross section cut by a straight line connecting the source electrode and the drain electrode of the first transistor is a cross section cut by a straight line connecting the source electrode and the drain electrode of the second transistor. A high-frequency module having a size corresponding to the width of the contact layer in the above.

DESCRIPTION OF SYMBOLS 1 High frequency module 11 1st transistor 12 2nd transistor 110 Substrate 111 Channel layer 113 Barrier layer 115 Buffer layer 117

Element isolation region

120, 220 Gate electrode 121

Gate insulating film

130, 230

Contact layer

140, 240 Drain electrode 150 Two-dimensional Electron gas

Claims

A channel layer formed of the first compound semiconductor;
A barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor;
A gate electrode provided on the barrier layer,
Source and drain electrodes provided on both sides of the gate electrode on the barrier layer,
Contact layers provided under the source electrode and the drain electrode, respectively, through the barrier layer;
And a first and a second transistor respectively having
The planar area of the source electrode or the drain electrode of the first transistor is larger than the planar area of the source electrode or the drain electrode of the second transistor,
A width of the contact layer in a cross section cut by a straight line connecting the source electrode and the drain electrode of the first transistor is a cross section cut by a straight line connecting the source electrode and the drain electrode of the second transistor. A semiconductor device having a size corresponding to the width of the contact layer.
The semiconductor device according to claim 1, wherein the width of the contact layer of the first transistor is substantially the same as the width of the contact layer of the second transistor.
The semiconductor device according to claim 1, wherein the source electrode or the drain electrode of the second transistor is provided in a single rectangular shape.
2. The semiconductor device according to claim 1, wherein the contact layer of the first transistor is provided in a part of a plane region where the source electrode or the drain electrode is provided.
The semiconductor device according to claim 4, wherein the contact layer of the first transistor is provided in a part of the source electrode or the drain electrode facing the gate electrode.
5. The semiconductor device according to claim 4, wherein a planar shape of the contact layer of the first transistor is a hollow rectangular shape provided along an outer periphery of a planar region provided with the source electrode or the drain electrode. 6. .
The semiconductor device according to claim 4, wherein the planar shape of the contact layer of the first transistor is a plurality of rectangular shapes extending in a direction orthogonal to a straight line connecting the source electrode and the drain electrode.
The semiconductor device according to claim 1, wherein the contact layer of the first transistor is provided in a plane region where the source electrode or the drain electrode is provided.
The semiconductor device according to claim 8, wherein the planar shape of the source electrode or the drain electrode of the first transistor is a hollow rectangular shape.
9. The semiconductor device according to claim 8, wherein the planar shape of the source electrode or the drain electrode of the first transistor is a plurality of rectangular shapes extending in a direction orthogonal to a straight line connecting the source electrode and the drain electrode. .
The semiconductor device according to claim 1, wherein the first compound semiconductor and the second compound semiconductor are nitride semiconductors.
The semiconductor device according to claim 1, wherein the contact layers of the first and second transistors are formed of a compound semiconductor into which a conductive impurity is introduced.
2. The semiconductor device according to claim 1, wherein the contact layers of the first and second transistors are provided on a surface of the channel layer on which the barrier layer is provided.
2. The semiconductor device according to claim 1, wherein the contact layers of the first and second transistors are provided so as to fill a recess formed in a surface of the channel layer on which the barrier layer is provided. 3.
2. The semiconductor device according to claim 1, wherein the contact layers of the first and second transistors are provided so as to contact an interface between the barrier layer and the channel layer on a side surface. 3.
The semiconductor device according to claim 1, wherein the gate electrode is provided on the barrier layer via a gate insulating film.
A channel layer formed of the first compound semiconductor;
A barrier layer formed on the channel layer with a second compound semiconductor different from the first compound semiconductor;
A gate electrode provided on the barrier layer,
Source and drain electrodes provided on both sides of the gate electrode on the barrier layer,
Contact layers provided under the source electrode and the drain electrode, respectively, through the barrier layer;
And a first and a second transistor respectively having
The planar area of the source electrode or the drain electrode of the first transistor is larger than the planar area of the source electrode or the drain electrode of the second transistor,
A width of the contact layer in a cross section cut by a straight line connecting the source electrode and the drain electrode of the first transistor is a cross section cut by a straight line connecting the source electrode and the drain electrode of the second transistor. A high-frequency module having a size corresponding to the width of the contact layer in the above.