WO2024000183A1

WO2024000183A1 - Nitride-based semiconductor device and method for manufacturing the same

Info

Publication number: WO2024000183A1
Application number: PCT/CN2022/101997
Authority: WO
Inventors: Weixing DU
Original assignee: Innoscience (suzhou) Semiconductor Co., Ltd.
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2024-01-04
Also published as: CN118077055A

Abstract

A nitride-based semiconductor device includes a first nitride-based transistor, a second nitride-based transistor, and a first electrical compensation layer. The first nitride-based transistor includes a first gate electrode and a first source electrode. The first gate electrode is electrically connected to a first node. The first source electrode is electrically connected to a second node. The second nitride-based transistor has at least one electrical characteristic different than that of the first nitride-based transistor. The second nitride-based transistor includes a second gate electrode and a second source. The second gate electrode is electrically connected to the first node. The second source electrode is electrically connected to the second node. The first electrical compensation layer is electrically coupled between the first source electrode and the second node.

Description

NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Inventors: Weixing DU

Field of the Invention:

The present invention generally relates to a semiconductor device. More specifically, the present invention relates to a high electron mobility transistor (HEMT) semiconductor device applied to a circuit with resistance compensated.

Background of the Invention:

In recent years, intense research on high-electron-mobility transistors (HEMTs) has been prevalent, particularly for high power switching and high frequency applications. The HEMT utilizes a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure, which accommodates a two-dimensional electron gas (2DEG) region, satisfying demands of high power/frequency devices. In addition to HEMTs, examples of devices having heterostructures further include heterojunction bipolar transistors (HBT) , heterojunction field effect transistor (HFET) , and modulation-doped FETs (MODFET) . At present, there is a need to improve the yield rate for HMET devices, thereby making them suitable for mass production.

Summary of the Invention:

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes a first nitride-based transistor, a second nitride-based transistor, and a first electrical compensation layer. The first nitride-based transistor includes a first gate electrode and a first source electrode. The first gate electrode is electrically connected to a first node. The first source electrode is electrically connected to a second node. The second nitride-based transistor has at least one electrical characteristic different than that of the first nitride-based transistor. The second nitride-based transistor includes a second gate electrode and a second source. The second gate electrode is electrically connected to the first node. The second source electrode is electrically connected to the second node. The first electrical compensation layer is electrically coupled between the first source electrode and the second node.

In accordance with one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes steps as follows. A first nitride-based semiconductor layer is formed. A second nitride-based semiconductor layer is formed over the first nitride-based semiconductor layer. A first nitride-based transistor and a second nitride-based transistor are formed over the second nitride-based semiconductor layer, in which the first nitride-based transistor has at least one electrical characteristic different than that of the second nitride-based transistor. An electrical compensation layer is formed over the second nitride-based semiconductor layer. The first nitride-based transistor is connected to the electrical compensation layer such that an equivalent resistance of the first nitride-based transistor in combination with the electrical compensation layer is close to a resistance of the second nitride-based transistor.

In accordance with one aspect of the present disclosure, a nitride-based semiconductor device is provided. The nitride-based semiconductor device includes an epitaxy growth substrate, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first nitride-based transistor, an electrical compensation layer, and an isolation structure. The first nitride-based semiconductor layer is disposed over the epitaxy growth substrate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region. The first nitride-based transistor is disposed over the second nitride-based semiconductor layer and includes a source electrode. The electrical compensation layer is disposed over the second nitride-based semiconductor layer and is electrically coupled with the source electrode. The isolation structure is embedded into the first and second nitride-based semiconductor layers and is located between the electrical compensation layer and the first nitride-based transistor.

By applying the above configuration, the first nitride-based transistor is electrically connected to the electrical compensation layer such that an equivalent resistance of the first nitride-based transistor in combination with the electrical compensation layer can get close to a resistance of the second nitride-based transistor.

Brief Description of the Drawings:

Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Embodiments of the present disclosure are described in more detail hereinafter with reference to the drawings, in which:

FIG. 1 is a circuit diagram of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure;

FIG. 2A is a cross-sectional view of the nitride-based transistor A according to some embodiments of the present disclosure;

FIG. 2B is a cross-sectional view of the nitride-based transistor B according to some embodiments of the present disclosure;

FIGS. 3A, 3B, 3C, and 3D illustrate different stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

FIG. 4 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure;

FIG. 5 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure;

FIG. 6 is a circuit diagram of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure;

FIG. 7 is a circuit diagram of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure; and

FIG. 8 is a circuit diagram of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure.

Detailed Description:

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as "above, " "below, " "up, " "left, " "right, " "down, " "top, " "bottom, " "vertical, " "horizontal, " "side, " "higher, " "lower, " "upper, " "over, " "under, " and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component (s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG. 1 is a circuit diagram of a nitride-based semiconductor device 1A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A includes nitride-based transistors A and B, and a compensator C1, which are integrated into a circuit. In the circuit, the different components which are electrically coupled/connected to each other can be achieved by using via, conductive layer, wire, trace, pad, or combinations thereof.

The nitride-based transistor A includes a gate electrode AG, a source electrode AS, and a drain electrode AD. The drain electrode AD is electrically coupled/connected to a power supply VDD. In some embodiments, the power supply VDD includes a positive supply voltage. The gate electrode AG is electrically coupled/connected to a node N1. The node N1 can be electrically coupled/connected to a power supply VG. In some embodiments, the power supply VG includes a gate voltage. The source electrode AS is electrically coupled/connected to a node N2. The node N2 can be electrically coupled/connected to a ground, which can include a ground voltage.

The nitride-based transistor B includes a gate electrode BG, a source electrode BS, and a drain electrode BD. The drain electrode BD is electrically coupled/connected to the power supply VDD. The gate electrode BG is electrically coupled/connected to the node N1. The source electrode BS is electrically coupled/connected to the node N2.

The nitride-based transistor A can have at least one electrical characteristic different than that of the nitride-based transistor B. Accordingly, the nitride-based transistors A and B are distinguishable. Such the difference is physical and measurable. The difference of the nitride-based transistors A and B may result from manufacturing tolerance. In some embodiments, the nitride-based transistors A and B are formed simultaneously over the same substrate.

The compensator C1 is electrically coupled/connected between the source electrode AS of the nitride-based transistor A and the node N2. The compensator C1 is configured to compensate the difference between the nitride-based transistors A and B. For example, in a case that the nitride-based transistors A and B are required having the same equivalent resistance, it may be hard to avoid resistance difference between the nitride-based transistors A and B. The compensator C1 can be applied for acting as a resistor to compensate for the equivalent resistance with the nitride-based transistor A, such that the nitride-based transistors A and B can have substantially the same equivalent resistance as required.

The characteristic of the compensator C1 can be turned in accordance with what the different characteristic between the nitride-based transistors A and B is. In some embodiments, the nitride-based transistor A has an electrical resistance different than an electrical resistance of the nitride-based transistor B. Correspondingly, the compensator C1 is configured to compensate for an equivalent resistance between the source electrode AS of the nitride-based transistor A and the node N2. As such, the equivalent resistance between the source electrode AS of the nitride-based transistor A and the node N2 is substantially the same as an equivalent resistance between the source electrode BS of the nitride-based transistor B and the node N2.

The difference between the nitride-based transistors A and B can be reached by batch statistics. For example, a device integrated the circuit above can be mass-produced, and the difference between the nitride-based transistors A and B (e.g., resistance difference) of a lot of devices is counted so as to obtain the desired compensation value. This approach is better than directly adjusting the properties/parameters of the nitride-based transistors A and B.

FIG. 2A is a cross-sectional view of the nitride-based transistor A according to some embodiments of the present disclosure. The nitride-based semiconductor device 1A further includes a substrate 10, nitride-based semiconductor layers 12 and 14, an isolation structure 16, contact vias 30, 34, 42, patterned

conductive layers

32, 36, passivation layers 60, 62.

The substrate 10 may be a semiconductor substrate. The substrate 10 may be an epitaxy growth substrate. The exemplary materials of the substrate 10 can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI) , or other suitable semiconductor materials. In some embodiments, the substrate 10 can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds) . In other embodiments, the substrate 10 can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated) . The buffer layer can be disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate 10 and the nitride-based semiconductor layer 12, thereby curing defects due to the mismatches/difference.

The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate 10 and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The nitride-based semiconductor layer 12 is disposed over the substrate 10. The exemplary materials of the nitride-based semiconductor layer 12 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, In _xAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1. The nitride-based semiconductor layer 14 is disposed on the nitride-based semiconductor layer 12. The exemplary materials of the nitride-based semiconductor layer 14 can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAl _yGa _(1–x–y)N where x+y ≤ 1, Al _yGa _(1–y)N where y ≤ 1.

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected such that the nitride-based semiconductor layer 14 has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer 12, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer 14 can be selected as an AlGaN layer having bandgap of approximately 4.0 eV.

As such, the nitride-based semiconductor layers 12 and 14 can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device 1A is available to include at least one GaN-based high-electron-mobility transistor (HEMT) .

The nitride-based semiconductor device 1A further includes

electrodes

20, 22, 24. The

electrodes

20, 22, 24 are disposed on the nitride-based semiconductor layer 14. The nitride-based transistor A as afore mentioned can be constituted by the

electrodes

20, 22, 24 in combination with the 2DEG region. The electrode 20 can serve as the source electrode AS of the nitride-based transistor A as afore mentioned; the electrode 22 can serve as the drain electrode AD of the nitride-based transistor A as afore mentioned; and the electrode 24 can serve as the gate electrode AG of the nitride-based transistor A as afore mentioned.

The electrode 24 is located between the

electrodes

20 and 22. A distance from the electrode 20 to the electrode 24 is less than a distance from the electrode 22 to the electrode 24. In some embodiments, the nitride-based semiconductor device 1A further includes a doped nitride-based semiconductor layer (not shown) between the nitride-based semiconductor layer 14 and the electrode 24 so as to get into an enhancement mode. For example, a p-doped nitride-based semiconductor layer can be disposed between the nitride-based semiconductor layer 14 and the electrode 24, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof.

In some embodiments, the

electrodes

20, 22 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the

electrodes

20, 22 can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The

electrodes

20, 22 may be a single layer, or plural layers of the same or different composition. In some embodiments, the electrodes 20, 22form ohmic contact with the nitride-based semiconductor layer 14. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the

electrodes

20, 22.

In some embodiments, each of the

electrodes

20, 22 is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer can include, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

In some embodiments, the electrode 24 may include metals or metal compounds. The electrode 24 may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the electrode 24 may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof.

The nitride-based semiconductor device 1A further includes an electrical compensation layer 50 disposed on the nitride-based semiconductor layer 14. The electrical compensation layer 50 in combination with the 2DEG region can serve as the compensator C1 as aforementioned. The electrical compensation layer 50 can be electrically coupled/connected to the electrode 20.

The electrical compensation layer 50 can includes two or more pads. In the exemplary embodiment as illustrated in FIG. 2A, the electrical compensation layer 50 includes two

pads

502 and 504. The

pads

502 and 504 are separated from each other. The pad 502 is located between the electrode 20 and the pad 504. The

pads

502 and 504 are electrically coupled with each other through the 2DEG region thereunder. Specifically, the

pads

502 and 504 are in contact with the nitride-based semiconductor layer 14. As such, carries can flow via the 2DEG region so as to get into or out the

pads

502 and 504.

In some embodiments, the

pads

502 and 504 can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon) , compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The materials of the

pads

502 and 504 can serve as one of factors for determining the equivalent resistance compensated for the electrode 20. In some embodiments, the materials of the

pads

502 and 504 are different than those of the electrode 20. In some embodiments, the

pads

502 and 504 have thickness different than that of the electrode 20. In some embodiments, the

pads

502 and 504 and the electrode 20 have the same material and thickness, but the

pads

502 and 504 different width than that of the electrode 20. Other factors may include area and length of each of the

pads

502 and 504 and a distance between the

pads

502 and 504. That is, the equivalent resistance compensated for the electrode 20 is controllable and tunable.

The isolation structure 16 is embedded into the substrate 10 and the nitride-based semiconductor layers 12, 14. The isolation structure 16 is located between the electrode 20 and the electrical compensation layer 50. The isolation structure 16 can make the 2DEG region discontinuous so carriers are hard to flow from the electrode 20 to the electrical compensation layer 50 directly through the 2DEG region. That is, in the 2DEG region, a path beneath the electrode 20 and the electrical compensation layer 50 can be taken as being broken. The isolation structure 16 can be made of at least one dielectric material.

The passivation layer 60 is disposed over the nitride-based semiconductor layer 14. The passivation layer 60 covers the isolation structure 16, the

electrodes

20, 22, 24, and the electrical compensation layer 50. The exemplary materials of the passivation layer 60 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof. In some embodiments, the passivation layer 60 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The contact vias 30 and 42 are disposed within the passivation layer 60. The contact vias 30 are shorter than the contact vias 42. The contact vias 30 and 42 penetrate the passivation layer 60. The contact vias 30 extend longitudinally to electrically couple with the

electrodes

20, 22, 24. The contact vias 42 extend longitudinally to electrically couple with the

pads

502 and 504 of the electrical compensation layer 50. The upper surfaces of the

contact vias

30 and 42 are free from coverage of the passivation layer 60. The exemplary materials of the

contact vias

30 and 42 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned conductive layer 32 is disposed on the passivation layer 60 and the

contact vias

30, 42. The patterned conductive layer 32 is in contact with the

contact vias

30, 42. The patterned conductive layer 32 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 74 can form at least one circuit. For example, the patterned conductive layer 32 includes a connection trace 320 connecting two

vias

30 and 42 so carriers can flow from the electrode 20 to the pad 502 of the electrical compensation layer 50 through the connection trace 320. The exemplary materials of the patterned conductive layer 32 can include, for example but are not limited to, conductive materials. The patterned conductive layer 32 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer 62 is disposed over the passivation layer 60 and the patterned conductive layer 32. The passivation layer 62 covers the patterned conductive layer 32. The exemplary materials of the passivation layer 62 can include, for example but are not limited to, SiN _x, SiO _x, Si ₃N ₄, SiON, SiC, SiBN, SiCBN, oxides, or combinations thereof. In some embodiments, the passivation layer 62 is a multi-layered structure, such as a composite dielectric layer of Al ₂O ₃/SiN, Al ₂O ₃/SiO ₂, AlN/SiN, AlN/SiO ₂, or combinations thereof.

The contact vias 34 are disposed within the passivation layer 60. The contact vias 34 penetrate the passivation layer 62. The contact vias 34 extend longitudinally to electrically couple with the patterned conductive layer 32. The upper surfaces of the contact vias 34 are free from coverage of the passivation layer 62. The exemplary materials of the contact vias 34 can include, for example but are not limited to, conductive materials, such as metals or alloys.

The patterned conductive layer 36 is disposed on the passivation layer 62 and the contact vias 34. The patterned conductive layer 36 is in contact with the contact vias 34. The patterned conductive layer 36 may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer 36 can form at least one circuit. The exemplary materials of the patterned conductive layer 36 can include, for example but are not limited to, conductive materials. The patterned conductive layer 36 may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof. The patterned conductive layer 36 can be configured to electrically connect to external elements (e.g., power supply) . By the patterned conductive layer 36, the electrode 20 can be electrically coupled/connected to the node N2 through the electrical compensation layer 50; the electrode 22 can be electrically coupled/connected to the power supply VDD; and the electrode 24 can be electrically coupled/connected to the node N1.

FIG. 2B is a cross-sectional view of the nitride-based transistor B according to some embodiments of the present disclosure. The nitride-based transistor B can share the substrate 10, the nitride-based semiconductor layers 12 and 14 and the 2DEG region therebetween with the nitride-based transistor A. The structure of the nitride-based transistor B is similarly to the structure of the nitride-based transistor A. The nitride-based transistor B excludes the electrical compensation layer 50 as aforementioned. The nitride-based semiconductor device 1A further includes

electrodes

70, 72, 74 disposed on the nitride-based semiconductor layer 14. The nitride-based transistor B as afore mentioned can be constituted by the

electrodes

70, 72, 74 in combination with the 2DEG region. The electrode 70 can serve as the source electrode BS of the nitride-based transistor B as afore mentioned; the electrode 72 can serve as the drain electrode BD of the nitride-based transistor B as afore mentioned; and the electrode 74 can serve as the gate electrode BG of the nitride-based transistor B as afore mentioned. The description with respect to the similar or identical layers illustrated in FIG. 2B to the illustration in FIG. 2A is omitted.

Different stages of a method for manufacturing the semiconductor device 1A are shown in FIGS. 3A, 3B, 3C, and 3D as described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD) , physical vapor deposition (PVD) , chemical vapor deposition (CVD) , metal organic CVD (MOCVD) , plasma enhanced CVD (PECVD) , low-pressure CVD (LPCVD) , plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring to FIG. 3A, a substrate 10 is provided. Nitride-based semiconductor layers 12 and 14 can be formed over the substrate 10 in sequence by using the above-mentioned deposition techniques. An isolation structure 16 is formed. The isolation structure 16 is embedded into the nitride-based semiconductor layers 12 and 14.

Referring to FIG. 3B,

electrodes

20, 22, 24 are formed over the nitride-based semiconductor layer 14 so as to form a transistor A over the nitride-based semiconductor layer 14. Simultaneously, although it is not illustrated in FIG. 3B, another transistor (i.e., the transistor B as afore mentioned) is formed over the nitride-based semiconductor layer 14 as well.

Referring to FIG. 3C, an electrical compensation layer 50 is formed over the nitride-based semiconductor layer 14. The electrical compensation layer 50 is formed to make contact with the nitride-based semiconductor layer 14. The electrical compensation layer 50 is formed such that the electrical compensation layer 16 is located between the electrical compensation layer 50 and the nitride-based transistor A. The formation of the electrical compensation layer 50 includes forming

pads

502 and 504 over the nitride-based semiconductor layer 14.

Referring to FIG. 3D, the nitride-based transistor A is electrically connected to the electrical compensation layer 50 such that an equivalent resistance of the nitride-based transistor A in combination with the electrical compensation layer 50 is close to a resistance of the nitride-based transistor B, as afore described. The connection process includes forming

contact vias

30 and 42 and metal lines 33 over the nitride-based transistor A and the electrical compensation layer 50.

FIG. 4 is a cross-sectional view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 2A and 2B, except that the electrical compensation layer 50 is replaced by an electrical compensation layer 50B.

The electrical compensation layer 50B is a continuous layer. Herein, the term “continuous layer” means the electrical compensation layer 50B has no separated portions. When carriers enter the electrical compensation layer 50B, the carriers can get out of the electrical compensation layer 50B through flowing in the electrical compensation layer 50B only.

FIG. 5 is a cross-sectional view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A as described and illustrated with reference to FIGS. 1A and 1B, except that the electrical compensation layer 50 is replaced by an electrical compensation layer 50C.

The electrical compensation layer 50C includes

pads

502C and 504C. The

pads

502C and 504C have different lengths. The pad 502C is shorter than the pad 504C. The pad 502C is narrower than the pad 504C. Since the pad 502C is shorter than the pad 504C, parasitic capacitance between the pad 502C and the layers of the nitride-based transistor A can be reduced.

In the following, embodiments show the compensator present at different locations. The compensator (s) as follows can be achieved by forming at least one electrical compensation layer. The compensator (s) at different location in the circuit can be achieved by shifting the electrical compensation layer in the structure (i.e., forming the electrical compensation layer at different position in the structure) .

FIG. 6 is a circuit diagram of a nitride-based semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D has a circuit diagram similar to that of the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the compensator C1 is omitted and a compensator C2 is disposed to electrically couple/connect between the source electrode AD of the nitride-based transistor A and the power supply VDD. The compensator C2 is configured to compensate for an equivalent resistance with respect to the desired component so the position of the compensator C2 is adjustable. The compensator C2 electrically couple/connect between the drain electrode AD of the nitride-based transistor A and the power supply VDD still can compensate for an equivalent resistance with respect to the nitride-based transistor A, thereby balancing the difference between equivalent resistance of the nitride-based transistors A and B.

FIG. 7 is a circuit diagram of a nitride-based semiconductor device 1E according to some embodiments of the present disclosure. The semiconductor device 1E has a circuit diagram similar to that of the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the compensator C1 is omitted; a compensator C3 is disposed to electrically couple/connect between the source electrode AS of the nitride-based transistor A and the node N2; and a compensator C4 is disposed to electrically couple/connect between the source electrode BS of the nitride-based transistor B and the node N2

The compensator C3 is configured to compensate for an equivalent resistance between the source electrode AS of the nitride-based transistor A and the node N2. The compensator C4 is configured to compensate for an equivalent resistance between the source electrode BS of the nitride-based transistor B and the node N2. In some embodiments, the compensators C3 and C4 have different electrical characteristics. For example, the compensators C3 and C4 may have different resistance. As such, the difference between equivalent resistance of the nitride-based transistors A and B can be balanced. The compensators C3 and C4 can be integrated into the structure of the nitride-based transistors A and B, which means the compensators C3 and C4 and nitride-based transistors A and B can share the same substrate and nitride-based semiconductor layers.

FIG. 8 is a circuit diagram of a nitride-based semiconductor device 1F according to some embodiments of the present disclosure. The semiconductor device 1F has a circuit diagram similar to that of the semiconductor device 1A as described and illustrated with reference to FIG. 1, except that the compensator C1 is omitted; a compensator C5 is disposed to electrically couple/connect between the drain electrode AD of the nitride-based transistor A and the power supply VDD; a compensator C6 is disposed to electrically couple/connect between the drain electrode BD of the nitride-based transistor B and the node power supply VDD; a compensator C7 is disposed to electrically couple/connect between the source electrode AS of the nitride-based transistor A and the node N2; and a compensator C8 is disposed to electrically couple/connect between the source electrode BS of the nitride-based transistor B and the node N2.

The compensator C5 is configured to compensate for an equivalent resistance between the drain electrode AD of the nitride-based transistor A and the power supply VDD. The compensator C6 is configured to compensate for an equivalent resistance between the drain electrode BD of the nitride-based transistor B and the node power supply VDD. The compensator C7 is configured to compensate for an equivalent resistance between the source electrode AS of the nitride-based transistor A and the node N2. The compensator C8 is configured to compensate for an equivalent resistance between the source electrode BS of the nitride-based transistor B and the node N2.

In some embodiments, at least two of the compensators C5, C6, C7, and C8 have different electrical characteristics. For example, the compensators C5 and C6 may have different resistance. As such, the difference between equivalent resistance of the nitride-based transistors A and B can be balanced. By increasing the number of the compensators, the adjustment to the equivalent resistance can be more accuracy, which results from more factors to be tunable. These compensators C5-C8 can be intergraded into the structure of the nitride-based transistors A and B so they are compatible with the HEMT device.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially, " "substantial, " "approximately" and "about" are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10%of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm of lying along the same plane.

As used herein, the singular terms “a, ” “an, ” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.

Claims

A nitride-based semiconductor device comprising:

a first nitride-based transistor comprising:

a first gate electrode electrically connected to a first node; and

a first source electrode electrically connected to a second node;

a second nitride-based transistor having at least one electrical characteristic different than that of the first nitride-based transistor, wherein the second nitride-based transistor comprises:

a second gate electrode electrically connected to the first node; and

a second source electrode electrically connected to the second node; and

a first electrical compensation layer electrically coupled between the first source electrode and the second node.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first nitride-based transistor has an electrical resistance different than an electrical resistance of the second nitride-based transistor.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first electrical compensation layer is configured to compensate for an equivalent resistance between the first source electrode and the second node.
The nitride-based semiconductor device of any one of the preceding claims, wherein the equivalent resistance between the first source electrode and the second node is substantially the same as an equivalent resistance between the second source electrode and the second node.
The nitride-based semiconductor device of any one of the preceding claims, further comprising;

a first nitride-based semiconductor layer; and

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region, wherein the first nitride-based transistor applies the 2DEG region as a channel.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first gate electrode, the first source electrode, and the first electrical compensation layer are disposed on the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein the first electrical compensation layer comprises two or more pads, the pads are separated from each other and are electrically coupled with each other through the 2DEG region.
The nitride-based semiconductor device of any one of the preceding claims, wherein at least two of the pads have different lengths.
The nitride-based semiconductor device of any one of the preceding claims, wherein the pads are in contact with the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, further comprising an isolation structure embedded into the first and second nitride-based semiconductor layers and located between the first electrical compensation layer and the first source electrode.
The nitride-based semiconductor device of any one of the preceding claims0, wherein the isolation structure makes the 2DEG region discontinuous.
The nitride-based semiconductor device of any one of the preceding claims, further comprising an epitaxy growth substrate disposed beneath the first nitride-based transistor, the second nitride-based transistor, and the first electrical compensation layer.
The nitride-based semiconductor device of any one of the preceding claims, further comprising:

a second electrical compensation layer electrically coupled between the second source electrode and the second node.
The nitride-based semiconductor device of any one of the preceding claims3, wherein the second electrical compensation layer is configured to compensate for an equivalent resistance between the second source electrode and the second node.
The nitride-based semiconductor device of any one of the preceding claims3, wherein the first and second electrical compensation layers have different electrical characteristics.
A method for manufacturing a nitride-based semiconductor device, comprising:

forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer over the first nitride-based semiconductor layer;

forming a first nitride-based transistor and a second nitride-based transistor over the second nitride-based semiconductor layer, wherein the first nitride-based transistor has at least one electrical characteristic different than that of the second nitride-based transistor;

forming an electrical compensation layer over the second nitride-based semiconductor layer; and

connecting the first nitride-based transistor to the electrical compensation layer such that an equivalent resistance of the first nitride-based transistor in combination with the electrical compensation layer is close to a resistance of the second nitride-based transistor.
The method of any one of the preceding claims, wherein forming the electrical compensation layer comprises forming a plurality of pads over the second nitride-based semiconductor layer.
The method of any one of the preceding claims, further comprising:

forming an isolation structure embedded into the first and second nitride-based semiconductor layers and located between the electrical compensation layer and the first nitride-based transistor.
The method of any one of the preceding claims, wherein connecting the first nitride-based transistor to the electrical compensation layer comprises forming at least one contact via and at least one metal line.
The method of any one of the preceding claims, wherein the electrical compensation layer is formed to make contact with the second nitride-based semiconductor layer.
A nitride-based semiconductor device comprising:

an epitaxy growth substrate;

a first nitride-based semiconductor layer disposed over the epitaxy growth substrate; and

a second nitride-based semiconductor layer disposed on the first nitride-based semiconductor layer and having a bandgap greater than a bandgap of the first nitride-based semiconductor layer, so as to form a heterojunction therebetween with a two-dimensional electron gas (2DEG) region;

a first nitride-based transistor disposed over the second nitride-based semiconductor layer and comprising a source electrode;

an electrical compensation layer disposed over the second nitride-based semiconductor layer and electrically coupled with the source electrode; and

an isolation structure embedded into the first and second nitride-based semiconductor layers and located between the electrical compensation layer and the first nitride-based transistor.
The nitride-based semiconductor device of any one of the preceding claims, further comprising:

a second nitride-based transistor disposed over the second nitride-based semiconductor layer and having at least one electrical characteristic different than that of the first nitride-based transistor.
The nitride-based semiconductor device of any one of the preceding claims, wherein the electrical compensation layer comprises a plurality of pads over the second nitride-based semiconductor layer.
The nitride-based semiconductor device of any one of the preceding claims, wherein two of the pads have different lengths.
The nitride-based semiconductor device of any one of the preceding claims, wherein the pads and the source electrode comprise different materials.