JP6301863B2 - Nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nitride semiconductor device manufactured using a nitride semiconductor and a manufacturing method thereof.

  Nitride semiconductors such as GaN have characteristics such as high breakdown field strength, high thermal conductivity, and high electron saturation speed, and are excellent as materials for high-frequency high-power devices. For example, a heterojunction structure having an AlGaN barrier layer formed on a sapphire substrate whose main surface is a C-plane via a GaN buffer layer whose main surface is a group III polar surface (C-plane) is Electrons are accumulated at a high concentration in the vicinity of the heterojunction interface to form a so-called two-dimensional electron gas (2DEG) (see Non-Patent Document 1).

  This two-dimensional electron gas exhibits high electron mobility because it is formed in an undoped GaN layer that does not have conductive impurities that cause scattering. Therefore, by using a two-dimensional electron gas as a channel, it can be operated as a so-called high electron mobility transistor (HEMT). In the nitride-based HEMT, since the two-dimensional electron gas concentration generated by the polarization effect is very high, transistor operation at a high current density is possible, which is also advantageous for high power devices.

By the way, when a HEMT using a heterostructure of AlGaN and GaN is applied to, for example, a millimeter wave band power amplifier (PA) or a monolithic microwave integrated circuit (MMIC), the cutoff frequency f _T and the maximum oscillation frequency f _max are several. It is necessary to set it to 100 GHz. In order to improve the high-speed performance of the HEMT using GaN or the like, miniaturization according to the scaling law and reduction of parasitic resistance are effective as in other transistors.

Non-Patent Document 2 discloses that f _T exceeding 450 GHz and f f close to 600 GHz due to miniaturization such as shorter gate length and reduction of parasitic resistance due to regrowth of the low resistance n-type layer in the ohmic access region. The value of _max has been reported. In this HEMT, as shown in FIG. 5, an AlGaN layer 502 is formed on a SiC substrate 501, a GaN layer 503 and an AlN layer 504 are stacked thereon, and n ⁺ -The GaN layer 505 is regrown. A T-shaped gate electrode 506 having a T-shaped cross section is formed on the AlN layer 504, and a source electrode 507 and a drain electrode 508 are formed on the re-grown n ⁺ -GaN layer 505. Further, the surface of the element is protected by a silicon nitride layer 509.

In the HEMT, the gate resistance is reduced while the gate length is shortened by adopting the T-type gate electrode 506. In the source / drain contact region, the source electrode 507 and the drain electrode 508 are brought into contact with the two-dimensional electron gas 521 by the low-resistance n ⁺ -GaN layer 505 that has been removed by etching and then regrown, and accessed. The resistance is reduced.

O. Ambacher et al., "Two-dimensional electron gases induced by spontaneous and piezoelectric polarization charges in N- and Ga-face AlGaN / GaN heterostructures", Journal of Applied Physics, vol.85, No.6, pp.3222- 3233, 2006. K. Shinohara et al., "Scaling of GaN HEMTs and Schottky Diodes for Submillimeter-Wave MMIC Applications", IEEE Transactions on Electron Devices, vol.60, No.10, pp.2982-2996, 2013. K. Hiramatsu et al., "Fabrication and characterization of low defect density GaN using facet-controlled epitaxial lateral overgrowth (FACELO)", Journal of Crystal Growth, vol.221, pp.316-326, 2000.

  However, the HEMT described above has the following problems. Although the T-type gate electrode is a technology widely used in short gate transistors, the gate part of the T-shaped leg is very thin compared to the head, so that the gate electrode tends to fall down during the process, and the yield There is a problem of lowering. This problem becomes more prominent when the length of the foot is increased in order to reduce the gate parasitic capacitance and the area in contact with the semiconductor layer is decreased in order to extremely shorten the gate length.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to make it possible to shorten the gate length without reducing the process yield.

  The nitride semiconductor device according to the present invention includes an insulating layer made of a nitride semiconductor formed on a substrate and an undoped nitride semiconductor, and is formed by crystal growth only in a gate region on the insulating layer. A channel layer, a barrier layer formed by growing a crystal only on the channel layer, and an n-type nitride semiconductor, and insulating around the channel layer and the barrier layer. A contact layer formed by crystal growth on the layer; a gate electrode formed on the barrier layer; and a source electrode and a drain electrode formed on both sides of the gate electrode and connected to the contact layer .

  In the nitride semiconductor device, the contact layer may be formed thicker than the barrier layer, and the gate electrode may have a recessed gate structure.

In the nitride semiconductor device, the channel layer and the barrier layer have a main surface as a group III polar surface and a growth side surface as a (1-101) surface .

  The method for manufacturing a nitride semiconductor device according to the present invention includes a first step of crystal-growing an insulating layer made of a nitride semiconductor on a substrate, and a selective growth mask having an open gate region on the insulating layer. A second step of performing a crystal growth of an undoped nitride semiconductor selectively on the insulating layer in the opening of the selective growth mask to form a channel layer only in the gate region on the insulating layer; A fourth step of forming a barrier layer by crystal growth of a nitride semiconductor only on the channel layer; and removing the selective growth mask and then n-type nitride on the insulating layer around the channel layer and the barrier layer A fifth step of forming a contact layer by crystal growth of a semiconductor; a sixth step of forming a gate electrode on the barrier layer; and a fifth step of forming a source electrode and a drain electrode connected to the contact layer across the gate electrode. 7 steps Equipped with a.

  In the method for manufacturing a nitride semiconductor device, in the fourth step, the contact layer may be formed to be thicker than the barrier layer, and the gate electrode may have a recessed gate structure.

In the method for manufacturing a nitride semiconductor device, in the third step and the fourth step , the channel layer and the barrier layer are crystallized in a state where the main surface is a group III polar surface and the growth side surface is a (1-101) surface. you growth. In the fourth step, the selective growth mask may be removed by wet etching that selectively etches the selective growth mask with respect to the insulating layer, the channel layer, and the barrier layer.

  As described above, according to the present invention, an excellent effect that the gate length can be shortened without reducing the process yield can be obtained.

FIG. 1 is a cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view showing the state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2B is a cross-sectional view showing the state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2C is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2D is a cross sectional view showing a state of the intermediate step for describing the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2E is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2F is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2G is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 2H is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a configuration of the nitride semiconductor device according to the second embodiment of the present invention. FIG. 4A is a cross-sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4B is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4C is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4D is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4E is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4F is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4G is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4H is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 4I is a cross sectional view showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention. FIG. 5 shows FIG. It is a block diagram which shows the structure of HEMT shown by 4 (c).

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIGS. 1 and 2A to 2H. FIG. 1 is a cross-sectional view showing the configuration of the nitride semiconductor device according to the first embodiment of the present invention. 2A to 2H are cross-sectional views illustrating a state of an intermediate process for explaining the method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention.

  The nitride semiconductor device according to the first embodiment includes, for example, a buffer layer 102 made of a nitride semiconductor formed on a substrate 101 made of semi-insulating Si-face (0001) SiC. The buffer layer 102 may be made of, for example, AlN or AlGaN. In addition, an insulating layer 103 made of a nitride semiconductor is provided on the buffer layer 102. The insulating layer 103 may be made of GaN doped with Fe or C. Further, for the purpose of suppressing the short channel effect often observed in a field effect transistor having a short gate length, a back barrier structure may be formed using a material having a wider band gap than the material of the channel layer 104 described later. For example, when the channel layer 104 is made of GaN, the insulating layer 103 may be made of AlGaN or the like.

  In addition, this nitride semiconductor device is composed of an undoped nitride semiconductor, and is composed of a channel layer 104 formed by crystal growth only in the gate region 121 on the insulating layer 103 and a channel composed of a nitride semiconductor. And a barrier layer 105 formed by crystal growth only on the layer 104. The gate region 121 is, for example, a strip-shaped region that extends from the front of the sheet of FIG. The channel layer 104 may be composed of undoped GaN, and the barrier layer 105 may be composed of undoped AlGaN.

  Here, the channel layer 104 and the barrier layer 105 are formed by crystal growth (epitaxial growth) in a state where the main surface is a group III polar surface, in other words, by crystal growth in the (0001) plane direction of the group III polarity. Good to be. When a nitride semiconductor is crystal-grown by a commonly used metal organic chemical vapor deposition (MOVPE) method on a group III polar surface (C + plane), the nitride semiconductor grows with a group III polarity. In this case, when the crystal is grown under the condition that the growth side surface is (1-101), the surface area becomes smaller with the growth. As a result, the dimension of the interface between the channel layer 104 and the barrier layer 105 in the substrate plane direction (gate length direction) can be made smaller than the bottom surface of the channel layer 104.

  The nitride semiconductor device according to the first embodiment is made of an n-type nitride semiconductor, and is formed by crystal growth on the insulating layer 103 around the channel layer 104 and the barrier layer 105. A gate electrode 108 formed on the barrier layer 105 with an insulating layer 107 interposed therebetween, and a source electrode 109 and a drain electrode 110 which are formed with the gate electrode 108 interposed therebetween and connected to the contact layer 106. The contact layer 106 may be made of, for example, GaN doped with Si at a high concentration. The insulating layer 107 may be made of silicon nitride. Note that the gate electrode 108 may be configured to be Schottky connected to the barrier layer 105.

  Next, a method for manufacturing the nitride semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 2A to 2H.

  First, a substrate 101 made of semi-insulating Si-face (0001) SiC is prepared as shown in FIG. 2A, and AlN or AlGaN is deposited on the prepared substrate 101 as shown in FIG. Layer 102 is formed. Next, as shown in FIG. 2C, a nitride semiconductor such as Fe or C doped GaN is crystal-grown to form an insulating layer 103 (first step). In this crystal growth, a nitride semiconductor is grown in the (0001) plane direction of group III polarity by a MOVPE apparatus.

  Next, as shown in FIG. 2D, a selective growth mask 151 having an opening 151a in the gate region 121 is formed on the insulating layer 103 (second step). For example, the substrate 101 is taken out from the MOVPE apparatus used for the growth of the nitride semiconductor described above, and silicon nitride is deposited on the insulating layer 103 by a plasma-assisted chemical vapor deposition (PE-CVD) apparatus or a sputtering apparatus. A silicon nitride film is formed. Next, the formed silicon nitride film may be patterned by a known lithography technique and etching technique to form a selective growth mask 151 having an opening 151a.

  Next, as shown in FIG. 2E, an undoped nitride semiconductor is selectively grown on the insulating layer 103 in the opening 151a of the selective growth mask 151, and a channel is formed only in the gate region 121 on the insulating layer 103. The layer 104 is formed (third step). Subsequently, a barrier layer 105 is formed by crystal growth of a nitride semiconductor only on the channel layer 104 (fourth step). For example, the MOVPE apparatus used to form the insulating layer 103 may be used to grow undoped GaN to a predetermined thickness and subsequently grow undoped AlGaN.

  Here, the channel layer 104 and the barrier layer 105 are crystal-grown in the (0001) plane direction of group III polarity. Further, crystal growth is performed under the condition that the growth side surface becomes (1-101) (see Non-Patent Document 3). Under this condition, the channel layer 104 has a smaller dimension in the gate length direction as it grows. When the channel layer 104 thus grown is grown to a predetermined thickness, the upper surface of the formed channel layer 104 becomes smaller than the area of the opening 151a, and the cross section of the channel layer 104 in both gate directions is trapezoidal. It becomes.

  Further, when the barrier layer 105 is grown on the channel layer 104 grown as described above, the dimension in the gate length direction similarly decreases with the growth. As a result, the growth of the barrier layer 105 automatically stops when it grows to a point where the upper surface, which is the (0001) plane, cannot be further reduced. As a result, the barrier layer 105 has a triangular cross section in both gate directions.

  Since the interface between the channel layer 104 and the barrier layer 105 becomes the channel length, as can be seen from the above description, the channel length is defined by the gate length width of the opening 151a and smaller than the gate length width of the opening 151a. be able to. As described above, according to the first embodiment, it is possible to shorten the channel without depending on the gate length dimension of the gate electrode 108 formed as described later.

  Next, after removing the selective growth mask 151, an n-type nitride semiconductor is crystal-grown on the insulating layer 103 around the channel layer 104 and the barrier layer 105, as shown in FIG. Is formed (fifth step). For example, after the barrier layer 105 is formed, the substrate 101 is taken out from the MOVPE apparatus, and only the selective growth mask 151 is selectively removed by wet etching using hydrofluoric acid or the like. This is wet etching in which the selective growth mask 151 is selectively etched with respect to the insulating layer 103, the channel layer 104, and the barrier layer 105. Next, the substrate may be carried into the MOVPE apparatus again, and GaN doped with Si at a high concentration may be regrown on the exposed insulating layer 103.

  By the way, if the regrowth time of the contact layer 106 is too long, the channel layer 104 and the barrier layer 105 that have already been formed are completely covered with the contact layer 106. In order to prevent this, the reflectance of the substrate surface may be measured while growing using an optical method. While the channel layer 104 and the barrier layer 105 appear on the surface of the growth layer, the reflectivity decreases due to the unevenness, but the reflectivity increases when the surface is completely covered and the surface is flattened. By monitoring this change in reflectance during growth, the burying regrowth time of the contact layer 106 can be controlled.

  Next, as shown in FIG. 2G, an insulating layer 107 is formed so as to cover the contact layer 106 and the barrier layer 105 exposed thereon. For example, the insulating layer 107 can be formed by removing the substrate 101 from the MOVPE apparatus and depositing silicon nitride using a PE-CVD apparatus or a sputtering apparatus.

  Next, as shown in FIG. 2H, the gate electrode 108 is formed on the barrier layer 105 (sixth step), and the source electrode 109 and the drain electrode 110 that are ohmically connected to the contact layer 106 with the gate electrode 108 interposed therebetween are formed. (Seventh step). For example, each electrode may be formed by a well-known lift-off method. In forming the source electrode 109 and the drain electrode 110, an opening is formed in an electrode formation portion of the insulating layer 107 by selective etching using a lift-off mask, and then an electrode material is deposited and the lift-off mask is removed. Thus, the source electrode 109 connected to the contact layer 106 may be formed.

  As described above, according to the first embodiment, the channel length can be defined by the interface between the channel layer 104 grown only in the gate region 121 and the barrier layer 105, so that the damage of the foot portion is very small. Since it is not necessary to use a T-type gate electrode that is easy to process, the gate length can be further shortened without reducing the yield of the process.

  In addition, when the contact layer 106 is regrown, the selective growth mask 151 can be removed by wet etching, so that etching damage caused by removal by dry etching can be suppressed. As a result, the access resistance can be sufficiently lowered without increasing the contact parasitic resistance between the two-dimensional electron gas formed in the channel layer 104 and the contact layer 106.

[Embodiment 2]
Next, Embodiment 2 of the present invention will be described with reference to FIGS. 3 and 4A to 4I. FIG. 3 is a cross-sectional view showing a configuration of the nitride semiconductor device according to the second embodiment of the present invention. 4A to 4I are cross-sectional views showing a state of an intermediate step for explaining the method for manufacturing the nitride semiconductor device in the second embodiment of the present invention.

  The nitride semiconductor device according to the second embodiment includes, for example, a buffer layer 202 made of a nitride semiconductor formed on a substrate 201 made of semi-insulating Si-face (0001) SiC. The buffer layer 202 may be made of, for example, AlN or AlGaN. In addition, an insulating layer 203 made of a nitride semiconductor is formed on the buffer layer 202. The insulating layer 203 may be made of GaN doped with Fe or C. In order to suppress a short channel effect often observed in a field effect transistor having a short gate length, a back barrier structure may be formed using a material having a wider band gap than a material of a channel layer 204 described later. For example, when the channel layer 204 is made of GaN, the insulating layer 203 may be made of AlGaN or the like.

  The nitride semiconductor device is composed of an undoped nitride semiconductor, and is formed of a channel layer 204 formed by crystal growth only in the gate region 221 on the insulating layer 203, and a channel composed of a nitride semiconductor. A barrier layer 205 formed by crystal growth only on the layer 204. The gate region 221 is, for example, a strip-shaped region that extends from the front of the sheet of FIG. 3 toward the back. The channel layer 204 may be composed of undoped GaN, and the barrier layer 205 may be composed of undoped AlGaN. The above configuration is the same as that of the first embodiment.

  Here, the channel layer 204 and the barrier layer 205 are formed by crystal growth (epitaxial growth) in a state where the main surface is a group III polar surface, in other words, by crystal growth in the (0001) plane direction of the group III polarity. Good to be. When a nitride semiconductor is crystal-grown by a commonly used metal organic chemical vapor deposition (MOVPE) method on a group III polar surface (C + plane), the nitride semiconductor grows with a group III polarity. In this case, when the crystal is grown under the condition that the growth side surface is (1-101), the surface area becomes smaller with the growth. As a result, the dimension of the interface between the channel layer 204 and the barrier layer 205 in the substrate plane direction (gate length direction) can be made smaller than the bottom surface of the channel layer 204.

  The nitride semiconductor device according to the second embodiment is made of an n-type nitride semiconductor, and is formed by crystal growth on the insulating layer 203 around the channel layer 204 and the barrier layer 205. A gate electrode 208 formed on the barrier layer 205 with an insulating layer 207 interposed therebetween, and a source electrode 209 and a drain electrode 210 formed on the gate electrode 208 and connected to the contact layer 206. The contact layer 206 may be made of, for example, GaN doped with Si at a high concentration. The insulating layer 207 may be made of silicon nitride.

  Here, in the second embodiment, the contact layer 206 is formed thicker than the height to the barrier layer 205, and the gate electrode 208 has a recessed gate structure. The contact layer 206 is formed thick so as to fill the channel layer 204 and the barrier layer 205. In the thick gate region 221 of the contact layer 206, a groove 222 is formed that penetrates to the upper surface of the barrier layer 205 with a predetermined groove width in the gate length direction. In addition, a gate electrode 208 is formed so as to fill the inside of the groove 222 in which the insulating layer 207 is formed on the side surface and the bottom surface, thereby forming a recessed gate structure. Note that the gate electrode 208 may be configured to be in Schottky connection with the barrier layer 205.

  Next, a method for manufacturing the nitride semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 4A to 4I.

  First, a substrate 201 made of semi-insulating Si-face (0001) SiC is prepared as shown in FIG. 4A, and AlN or AlGaN is deposited on the prepared substrate 201 as shown in FIG. Layer 202 is formed. Next, as shown in FIG. 4C, GaN doped with, for example, Fe or C, which is a nitride semiconductor, is crystal-grown to form an insulating layer 203 (first step). In this crystal growth, a nitride semiconductor is grown in the (0001) plane direction of group III polarity by a MOVPE apparatus.

  Next, as shown in FIG. 4D, a selective growth mask 251 having an opening 251a in the gate region 221 is formed on the insulating layer 203 (second step). For example, the substrate 201 is taken out from the MOVPE apparatus used for the growth of the nitride semiconductor described above, and silicon nitride is deposited on the insulating layer 203 by a PE-CVD apparatus or a sputtering apparatus to form a silicon nitride film. Next, the formed silicon nitride film may be patterned by a known lithography technique and etching technique to form a selective growth mask 251 having an opening 251a.

  Next, as shown in FIG. 4E, an undoped nitride semiconductor is selectively grown on the insulating layer 203 in the opening 251a of the selective growth mask 251 and a channel is formed only in the gate region 221 on the insulating layer 203. The layer 204 is formed (third step). Subsequently, a barrier layer 205 is formed by crystal growth of a nitride semiconductor only on the channel layer 204 (fourth step). For example, the MOVPE apparatus used to form the insulating layer 203 may be used to grow undoped GaN to a predetermined thickness and subsequently grow undoped AlGaN.

  Here, the channel layer 204 and the barrier layer 205 are crystal-grown in the (0001) plane direction of group III polarity. Further, crystal growth is performed under the condition that the growth side surface becomes (1-101) (see Non-Patent Document 3). Under this condition, the channel layer 204 has a dimension in the gate length direction that decreases with growth. When the channel layer 204 grown in this way is grown to a predetermined thickness, the upper surface of the formed channel layer 204 becomes smaller than the area of the opening 251a, and the cross section of the channel layer 204 in both gate directions is trapezoidal. It becomes.

  Further, when the barrier layer 205 is grown on the channel layer 204 grown as described above, the dimension in the gate length direction similarly decreases with the growth. As a result, the growth of the barrier layer 205 automatically stops when it grows to a point where the upper surface, which is the (0001) plane, cannot be further reduced. As a result, the barrier layer 205 has a triangular cross section in both gate directions.

  Next, after removing the selective growth mask 251, an n-type nitride semiconductor is crystal-grown on the insulating layer 203 around the channel layer 204 and the barrier layer 205 as shown in FIGS. 4F and 4G. A contact layer 206 is formed (fifth step). In the regrowth of the contact layer 206, the channel layer 204 and the barrier layer 205 are completely embedded, and as shown in FIG.

  For example, after the barrier layer 205 is formed, the substrate 201 is unloaded from the MOVPE apparatus, and only the selective growth mask 251 is selectively removed by wet etching using hydrofluoric acid or the like. This is wet etching for selectively etching the selective growth mask 251 with respect to the insulating layer 203, the channel layer 204, and the barrier layer 205. Next, the substrate is carried into the MOVPE apparatus again, and GaN doped with Si at a high concentration may be regrown on the exposed insulating layer 203. As shown in FIG. 4G, the contact layer 206 regrown from the surface of the insulating layer 203 around the channel layer 204 is integrated in the upper part of the barrier layer 205 as shown in FIG. 4F and continues to grow as shown in FIG. 4G. It will eventually flatten.

  Dislocation occurs where the contact layer 206 meets from both sides across the channel layer 204 and the barrier layer 205, and defects such as dots are observed on the surface of the contact layer 206. This position is the center position of the gate region 221 in the gate length direction. After growing to a level, the gate forming portion is determined using the above dots as a mark, and after forming a mask pattern by a known lithographic process, the gate forming portion is etched, as shown in FIG. A groove 222 is formed. At this time, etching is performed until the barrier layer 205 is reached, so that the upper surface of the barrier layer 205 appears. Thus, according to the second embodiment, the center portion of the gate region 221 can be automatically determined, and the center position of the gate electrode 208 can be determined with high accuracy.

  In FIG. 4H, for the sake of simplification, the (0001) plane of the surface of the barrier layer 205 is shown. However, this plane orientation does not greatly affect the transistor operation regardless of which plane appears. Next, an insulating layer 207 is formed on the contact layer 206 including the side and bottom surfaces of the trench 222. For example, the insulating layer 207 can be formed by removing the substrate 201 from the MOVPE apparatus and depositing silicon nitride using a PE-CVD apparatus or a sputtering apparatus.

  Next, as shown in FIG. 4I, a gate electrode 208 is formed on the barrier layer 205 in a state of filling the trench 222 in which the insulating layer 207 is formed (sixth step), and the gate electrode 208 is sandwiched between them. Then, the source electrode 209 and the drain electrode 210 that are ohmically connected to the contact layer 206 are formed (seventh step). For example, each electrode may be formed by a well-known lift-off method. Further, in forming the source electrode 209 and the drain electrode 210, an opening is formed in an electrode formation portion of the insulating layer 207 by selective etching using a lift-off mask, and then an electrode material is deposited and the lift-off mask is removed. Thus, the source electrode 209 connected to the contact layer 206 may be formed.

  According to the second embodiment described above, the gate length is determined by the width of the trench 222 in the gate length direction. In Embodiment 2, the gate length can be made smaller than the length of the interface between the channel layer 204 and the barrier layer 205 in the gate length direction. Even if the gate length is very small, the thin legs of the gate length of the gate electrode 208 are supported by the contact layer 206 via the insulating layer 207 on both sides. For this reason, it does not fall down like a general T-type gate electrode structure. In addition, the gate electrode 208 in Embodiment 2 can be made to be a T-type with a larger head, and the gate resistance can be extremely reduced.

  Further, since the center position of the gate electrode 208 can be determined on the basis of dot-like defects caused by dislocations generated where the contact layers 206 meet from both sides across the channel layer 204 and the barrier layer 205, a very thin foot portion Can be positioned on the barrier layer 205 having a fine width by positioning with high accuracy.

  Thus, according to the second embodiment, it becomes easy to form a low-resistance gate electrode having sufficient mechanical strength while maintaining a short gate length necessary for high-frequency operation. On the other hand, with respect to the access region, as in the first embodiment, when the contact layer 206 is regrown, the selective growth mask 251 can be removed by wet etching, so that etching damage caused by removal by dry etching can be suppressed. become. As a result, the access resistance can be sufficiently lowered without increasing the contact parasitic resistance between the two-dimensional electron gas formed in the channel layer 204 and the contact layer 206.

  As described above, according to the present invention, the channel layer and the barrier layer made of the nitride semiconductor are grown by crystal growth only in the gate region, so that the gate yield can be reduced without reducing the process yield. The length can be shortened.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Buffer layer, 103 ... Insulating layer, 104 ... Channel layer, 105 ... Barrier layer, 106 ... Contact layer, 107 ... Insulating layer, 108 ... Gate electrode, 109 ... Source electrode, 110 ... Drain electrode, 121 ... gate area.

Claims (5)

An insulating layer made of a nitride semiconductor formed on the substrate;
A channel layer made of an undoped nitride semiconductor and formed by crystal growth only in the gate region on the insulating layer;
A barrier layer made of a nitride semiconductor and formed by crystal growth only on the channel layer;
a contact layer made of an n-type nitride semiconductor and formed by crystal growth on the insulating layer around the channel layer and the barrier layer;
A gate electrode formed on the barrier layer;
A source electrode and a drain electrode formed across the gate electrode and connected to the contact layer ;
It said channel layer and said barrier layer is a main surface and the group III-polar surface, and a nitride semiconductor device comprising grow sides that you have been the (1-101) plane. The nitride semiconductor device according to claim 1,
The contact layer is formed thicker than the height to the barrier layer,
The nitride semiconductor device, wherein the gate electrode has a recess gate structure. A first step of crystal growing an insulating layer made of a nitride semiconductor on a substrate;
Forming a selective growth mask having a gate region opened on the insulating layer;
A third step of selectively growing an undoped nitride semiconductor on the insulating layer in the opening of the selective growth mask to form a channel layer only in the gate region on the insulating layer;
A fourth step of crystal-growing a nitride semiconductor only on the channel layer to form a barrier layer;
A fifth step of forming a contact layer by growing an n-type nitride semiconductor on the insulating layer around the channel layer and the barrier layer after removing the selective growth mask;
A sixth step of forming a gate electrode on the barrier layer;
And a seventh step of forming a source electrode and a drain electrode connected to the contact layer across the gate electrode ,
Wherein in the third step and the fourth step, the channel layer and the barrier layer, you formed by crystal growth in a state the main surface and the group III-polar surface, and that the growth side and (1-101) plane A method for manufacturing a nitride semiconductor device. In the manufacturing method of the nitride semiconductor device according to claim 3 ,
In the fourth step, the contact layer is formed thicker than the height to the barrier layer,
The method of manufacturing a nitride semiconductor device, wherein the gate electrode has a recessed gate structure. In the manufacturing method of the nitride semiconductor device according to claim 3 or 4 ,
In the fourth step, the selective growth mask is removed by wet etching that selectively etches the selective growth mask with respect to the insulating layer, the channel layer, and the barrier layer. .

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