JPH01179458A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize the distance between a cap layer and a gate electrode precisely and with good reproducibility by a method wherein a patterning of the cap layer and the formation of the gate electrode are conducted by a self- matching system using a spacer layer as a mask. CONSTITUTION:A cap layer 4 and a spacer layer 5, which consist of a non-alloy and can come into ohmic contact, are formed on a channel layer 2 formed on a semiconductor substrate 1. Then, a spacer layer part at a position, where a gate electrode 7 is formed, is removed and the layer 4 at the position, where the electrode 7 is formed, is etched away using this layer 7 as a mask to form an aperture. Then, spacer layer parts at the position of source and drain electrodes 6 and 8, which are formed on both sides of the electrode 7, are removed and a metal is deposited on the whole surface from the vertical direction. This metal is removed leaving the parts of the electrodes 6, 7 and 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a plurality of gate electrodes and source and drain electrodes capable of non-alloy ohmic contact.

The purpose is to improve characteristics and cope with higher density.

a step of forming a channel layer (2) on the semiconductor substrate (1);

On the channel layer (2), a camp layer (2) capable of non-alloy ohmic contact with or without a semiconductor layer is provided.
4) and a step of forming a spacer layer (5) in this order.

a step of removing a portion of the spacer layer at a position where a gate electrode (7) is to be formed;

The gate electrode (7) using the spacer layer (5) as a mask.
a step of etching and removing the cap layer (4) at the position where the opening is to be formed;

Source electrodes (6) formed on both sides of the gate electrode (7)
and a step of removing a spacer portion at the position of the drain electrode (8).

A process in which metal is deposited vertically on the entire surface.

The metal is applied to the source electrode (6) and the gate electrode (7).
) and a step of removing the drain electrode (8) while leaving behind the drain electrode (8).

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly relates to a method of manufacturing a semiconductor device having a plurality of gate electrodes and source and drain electrodes capable of non-alloy ohmic contact.
The purpose is to improve characteristics and cope with higher density.

Conventionally, there has been a demand for semiconductor devices having a plurality of input sections used in logic circuits, etc., with no variation in characteristics, but there has been no satisfactory device, and development is required.

[Conventional technology]

Research and development of m-v group compound semiconductors is very active due to their physical characteristics. Recently, H
EMT has been studied, and it has been shown that non-alloy ohmic contacts can be formed in HEMTs with heterojunctions in the same way as in GaAsME SFETs (for example, 1962 Spring Applied Physics Society Proceedings 28a-x-1). .

As an example of a HEMTIC with non-alloy ohmic contacts, DCF L (Direct
There is a Coupled FET Logic) circuit. FIG. 5 shows a cross section of a conventional E/D configuration CFL circuit.

To create such a structure, first a channel layer 2. is formed on a GaAs semiconductor substrate 1. Electron supply layer of N-AlGaAs3. Fourth
Cap layer 44. Second stopper 92, n-GaA
s third cap layer 43. First stopper 91. n-Ga
A second cap layer 42 of As. n”-InGaAs
The first camp layer 41 is laminated in this order. Next, in order to remove the first camp layer in the portions where the E section gate section and the D section gate section are to be formed, the resist is patterned and the first camp layer is etched into a groove shape. After that, the resist is peeled off. After removing the second camp layer 42 on the side where the E section gate electrode 71 is formed, n''-1nGaA
E approximately in the center of the groove formed in the first camp layer 41 of s.
Resist is newly patterned at the positions where the 0-part gate electrode 71 and the 0-part gate electrode 72 are to be formed, and the lower layer of the portion corresponding to the respective gate electrodes 71 and 72 is etched. Although the details will not be described, by skillfully using the functions of the first stopper 91 and the second stopper 92, the etching of the groove in the gate part of the E part is carried out until the electron supply layer 3 is exposed, and the etching of the groove of the gate part of the D part is carried out until the etching of the groove in the gate part of the D part is carried out until the etching of the groove in the gate part of the D part is carried out until the etching of the groove in the gate part of the D part is carried out until the etching of the groove in the gate part of the D part is carried out until the etching of the groove in the gate part of the D part is carried out until the electron supply layer 3 is exposed. 4 until the cap layer 44 is exposed.

In this way, conventionally, the first
Patterning for etching the camp layer and patterning for the gate electrode forming area were performed separately. Therefore, considering the alignment margin for patterning, the gate electrode 71
The distance between 72 and the first cap layer 41 is about 1 μm (ε).

Furthermore, it is extremely difficult to accurately control the distance, and there is a large possibility that it will vary. When the distance between the low sheet resistance layer (first cap layer) and the gate becomes larger than a predetermined value, the source parasitic resistance (Rs) increases accordingly, degrading device characteristics.

[Problem that the invention seeks to solve]

Therefore, in the conventional manufacturing method, it is difficult to make the characteristics of the gates uniform in a circuit having a plurality of gates such as an E/D configuration, resulting in a problem that a satisfactory product cannot be obtained.

The present invention employs a self-alignment method in which the same mask is used for patterning the gate forming portion of the first cap layer 41 and forming the gate electrodes 71 and 72, so that the electrodes are formed in the center of the groove, and the cap layer is The purpose is to improve the accuracy of the positional relationship between the gate electrode and the source electrode, and to form the source and drain electrodes using a non-alloyohmic contact material.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

a step of forming a channel layer (2) on the semiconductor substrate (1);

On the channel layer (2), a cap layer (with or without a semiconductor layer) capable of non-alloy ohmic contact is provided.
4) and a step of forming a spacer layer (5) in this order.

a step of removing a portion of the spacer layer at a position where a gate electrode (7) is to be formed;

8. Gate electrode (
7) etching and removing the cap layer (4) at the position where the cap layer (4) is to be formed to form an opening;

Source electrodes (6) formed on both sides of the gate electrode (7)
and a step of removing a spacer portion at the position of the drain electrode (8).

A process in which metal is deposited vertically on the entire surface.

The metal is applied to the source electrode (6) and the gate electrode (7).
) and the step of removing the drain electrode (8) while leaving behind the above-mentioned problem.

[Effect]

In the present invention, since the cap layer is patterned and the gate electrode is formed in a self-aligned manner using the spacer layer as a mask, the distance between the cap layer and the gate electrode can be realized accurately and with good reproducibility. Furthermore, according to the method of the present invention, the source electrode, gate electrode, and drain electrode can be formed at the same time using the same metal.

〔Example〕

FIG. 2 shows a CFL having an E/D configuration according to the present invention as an example.
A cross section of the circuit is shown.

GaAs semiconductor substrate 1, 1-GaAs channel layer 2
．． nAlGaAs electron supply layer 3, n-GaAs
4th key +7 layer 44, n-AlGaAs second stopper 92, n-GaAs third cap layer 43.
n-GaAs first stopper 91゜n-GaAs second
Cap layer 42. A laminate in which the n''-GaAs first cap layer 41 and the 5i02 spacer layer 5 are laminated in this order,
Source electrode 6. E section gate electrode 71° 0 section gate electrode 7
2. Drain electrode8. An output part electrode 10 is formed.

The manufacturing process of the E/D configuration CFL circuit according to FIG. 3 is shown.

Refer to FIG. 3(a) (i) A channel layer 2 is formed on the semiconductor substrate 1. Electron supply layer 3.
Fourth cap layer 44. Second stopper 92° Third camp layer 43. First stopper 91. Second camp layer 42. n as a cap layer capable of non-alloy ohmic contact.
” -1nGaAs first cap layer 41 r 5i
The laminated plates stacked in the order of the spacers 5 of 5 oz are patterned with a resist, and the Si of the E part gate part and the D part gate part is patterned.
02 and n'' InGaAs are removed by dry etching.N'' InGaAs is overetched and Si
02 should be placed over the top like an eave.

Refer to FIG. 3(b). (ii) Using the spacer layer as a mask, wet etching is performed on the E section gate section until the first stopper 91 is removed, and the resist is peeled off.

See FIG. 3(c). (iii) Remove the spacer layers of the source electrode, drain electrode, and output electrode, and peel off the resist.

Refer to FIG. 3(d). (iv) Using the spacer layer as a mask, dry etching is performed to remove the second stopper 92 at the gate section E and the first stopper 91 at the gate section D.

See FIG. 3(e).(v) Metal is deposited vertically on the entire surface. Source electrode 6. E section gate electrode 71, 0 section gate electrode 72, drain electrode 8. The metal is milled and etched leaving the output part electrode 10.

In this way, the E/D configured FCL circuit shown in FIG. 2 can be formed.

The differences from the conventional example are as follows.

(2) The opening of the first cap layer etched in the gate portion formed at the beginning eventually becomes the gate opening.

■Electrode metal is formed by milling and etching after full-surface vapor deposition, rather than by lift-off.

(2) Dry etching of the gate part and ohmic part (first cap layer) is performed using the spacer layer as a mask.

As a result, the positional relationship between the gate part and the ohmic part is determined with high precision.

FIG. 4 shows another embodiment in which the input gate is a plurality of FBTs. Since the patterning of the cap layer 4 and the formation of the first gate electrode 711 and the second gate electrode 712 are performed in a self-aligned manner, there is little variation in characteristics between the gate electrodes. and second
Since the source parasitic resistance exists between the gates, the source parasitic resistance of the first gate and the source parasitic resistance of the second gate are almost equal.

It is clear that the method of the present invention can be applied not only to GaAs-based HEMTs but also to MESFETs and devices made of other materials.

〔Effect of the invention〕

As explained above, according to the manufacturing method according to the third invention, the formation of the gate part and the patterning of the cap layer are performed in a self-aligned manner, so the positional relationship between the gate part and the camp layer is determined with high precision, and the device characteristics are improved. improves.

When a two-manufactured FET is used, the source parasitic resistances between the two gates can be made equal, so there are advantages such as improved flexibility in designing the logic circuit.

Note that in the manufacturing method of the present invention, there is no need for a mask alignment margin of about 1 μm, which is usually provided in conventional manufacturing methods.
The size of the basic FET can be reduced.

It is effective for increasing the density and speed of ICs, etc.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a cross section of an FCL circuit with an E/D configuration according to the present invention. Figure 3 shows the manufacturing process of an FCL circuit with an E/D configuration. Figure 4 shows another embodiment. FIG. 5 is a cross section of a conventional E/D configured FCL circuit. In fig. 1 is a semiconductor substrate. 2 is the channel layer. 3 is the electron supply layer. 4 is the cap layer. 4th grade is the first cap layer. 42 is a second cap layer. 43 is the third cap layer. 44 is the fourth cap layer. 5 is a spacer layer. 6 is the source electrode. 7 is the gate electrode. 71 is the E section gate electrode. 72 is the 0 part gate electrode. 711 is a first gate electrode. 712 is a second gate electrode. 8 is the drain electrode. 91 is the first stop. 92 is the second stopper. IO is the output electrode according to the present invention. 7<'t Force I) Electrode bond hole (j (C) (d) E/D#A D F-CL e Ylhtn % l
TIZA 3 Figures (various/)2) Cold-blooded metal steaming, (C) E/D construction DFCL, trouble ■ Kakutata making process Figure 3
(n3) Relaxation Award 0″1 4th m

Claims (1)

[Claims] A step of forming a channel layer (2) on a semiconductor substrate (1), and a cap layer (on which non-alloy ohmic contact is possible) on the channel layer (2) with or without a semiconductor layer.
4) and a spacer layer (5) in this order; a step of removing a portion of the spacer layer at a position where the gate electrode (7) is to be formed; and a step of removing the spacer layer (7) using the spacer layer (5) as a mask. A step of etching and removing the cap layer (4) at the position where it is to be formed to form an opening, and a step of forming the source electrode (6) on both sides of the gate electrode (7).
and a step of removing a spacer portion at the position of the drain electrode (8), a step of vapor depositing metal on the entire surface from a vertical direction, and a step of depositing the metal on the source electrode (6) portion and the gate electrode (7) portion. A method for manufacturing a semiconductor device, comprising the step of removing the drain electrode (8) while leaving a portion thereof.