JPH03155169A - Semiconductor device - Google Patents

Abstract

PURPOSE:To sufficiently increase the input impedance of a gate and to separate input/output by varying a real space transition amount of electrons from a first channel layer to a second channel region by a gate voltage, and generating differentiated negative resistance due to the difference of electron speeds between the channel layers. CONSTITUTION:A second channel layer 107 formed on the upper part of a first channel layer 106 is so formed with a discontinuous conduction band as to be a potential barrier to the layer 106, formed of conductor having smaller electron speed than that of the layer 106, formed with a gate barrier layer 108 made of semiconductor or insulator to form a potential barrier to the layer 107, a gate electrode 109 is provided thereon, and ohmic electrodes 110, 111 of a source, a drain are provided at the side. Thus, real space transition amount of electrons from the layer 106 to the layer 107 is varied to generate a differentiated negative resistance due to the difference of electron speed between the channel layers.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device having an erodible differential resistance that can be controlled at high speed.

(Prior art and problems to be solved by the invention) First, the fourth
An example of a conventionally known structure of a semiconductor device having controllable negative differential resistance will be explained using FIGS.
For example, F., Capasso, G.

Hargaritondoed, Heterojun
cation Band discontinuity
s+ 9.513. North-Holland
(Refer to Physics Publishing+ 1987) Figure 4 is a cross-sectional view of the device, and in the figure 1 is semi-insulating Ga.
As substrate, 2 is GaAs second conductive layer (8600 layers) containing n-type impurities, 3 is Al with no impurities added,
aGao, 6As lower barrier layer (1400 people), 4
is a GaAs channel layer (17
00), 5.6.7 are the ohmic electrodes of the substrate, source, and drain, respectively.

FIG. 5 is a zero-line diagram showing the energy band structure of the first example of the conventional structure shown in FIG. 4 in an equilibrium state (dashed line) and in a state in which electrons are accumulated in the semiconductor channel layer (solid line). 8 indicates the Fermi energy position of the electron. By grounding the source electrode and applying a positive voltage to the substrate electrode, the lower end of the conduction band at the bottom of the channel layer is located below the Fermi energy, and this part Two-dimensional electron gas is accumulated. When a positive voltage is applied to the drain electrode in this state, a drain current flows.

At this time, if the substrate voltage is high to some extent, negative differential resistance appears in the drain current as shown in FIG.

This is because electrons accelerated by the drain voltage gain energy, become hot, and overflow into the AlGaAs layer 3. Since the overflowing electrons are injected into the second conductive layer by the positive voltage applied to the substrate electrode, they do not contribute to the drain current. Therefore, when the drain voltage is increased, the drain current decreases. The magnitude of this negative differential resistance can be changed by changing the voltage applied to the substrate electrode (control electrode). This element is NERFET
(Negative Resistance FET).

The operating speed of this device is, in principle, determined by the time it takes for electrons to gain energy and become hot, so very high-speed operation can be expected. However, in this structure, a decrease in drain current is inevitably accompanied by an increase in substrate current, and therefore input and output cannot be separated, making it very difficult to apply to circuits.

In addition, as shown in Figure 6, an NEL structure with a structure in which the top and bottom of Figure 4 are reversed and the overlaps between the substrate (gate) electrode and the source electrode and between the substrate (gate) electrode and the drain electrode are eliminated to reduce parasitic capacitance. ? FETs are known (M, S
, 5 hours at, TREE Elect
ronDevice Lett,, VOL, EDL
-7, p, 78.1986). In this case as well, the above drawback of not being able to separate input and output remains unsolved.

The present invention was proposed in order to improve the above-mentioned drawbacks, and its purpose is to provide a negative differential resistance three-terminal element that has separate input and output, is suitable for integration, and can be controlled at high speed. be.

(Means for Solving the Problems) The present invention has a conduction band discontinuity on the first channel layer that acts as a potential barrier to the channel layer,
A second channel layer made of a semiconductor material having a lower electron velocity than the channel layer is provided, and a barrier layer made of a semiconductor or an insulator is provided on top of the second channel layer to act as a potential barrier to the second channel layer. It is characterized by having a gate electrode, with source and drain ohmic electrodes provided on its sides.

(Function) Therefore, the semiconductor device according to the present invention changes the real space transition amount of electrons from the first to the second channel layer depending on the gate voltage, and generates negative differential resistance due to the difference in electron velocity between each channel layer. It has the effect of causing Unlike the conventional example, negative differential resistance is not caused by electrons in the channel flowing into the gate electrode. Therefore, the human input impedance of the gate can be made sufficiently large, and the input and output can be separated, reducing the impact on the circuit. It has significant advantages in application.

(Example) Next, an example of the present invention will be described. Note that the embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the present invention.

These features will be explained below based on specific examples shown in the attached drawings.

In FIG. 1, which shows a first embodiment of the present invention, 1
01 is a semi-insulating GaAs substrate, 102 is an undoped GaAs buffer layer of 6000 layers, and 103 is an undoped A
lxGa+-x^S grading layer (500 people) whose composition was linearly changed from χ = 0 to x -0,3, 104 is 300 people Si-doped^lo, 3G
ao, Js The doping concentration in the electron supply layer is, for example, 2
XIO"c+w-'., 105 is undoped^
106 is a first channel layer made of undoped GaAs (150 people), 107 is a second channel layer made of 500 people undoped AlAs, 108 is undoped Ale, 4sGa* , a 5sAs barrier layer with a thickness of, for example, 300 layers. 109 is a gate electrode made of, for example, WSi, and 110 and 111 are source and drain ohmic electrodes formed by AuGe/Ni vapor deposition and heat treatment. Here, the source electrode 110 is the barrier layer 108 on the surface, or the barrier layer 108 and the second channel layer 1.
07 is removed by etching, and is formed so as not to make direct ohmic contact with the AlAs second channel layer immediately below the gate.

First, consider the case where the gate voltage is sufficiently low. Source electrode 1
10 is grounded and a positive voltage is applied to the drain electrode 111, a drain current flows. In this case, the current flows to the zero-order gate carried by the electrons in the first channel layer, as shown by the broken line in FIG. When a positive voltage is applied, the amount of electrons accumulated in the first channel layer initially increases, so the drain current increases. Thereafter, as the voltage is further applied, the lower end of the conduction band becomes as shown by the solid line in FIG. 2, and the real space transition from the first channel layer to the second channel layer becomes more likely to occur. Therefore, if the drain voltage is increased under these conditions, the electrons that have gained energy will transition to the second channel layer, and the drain current will be mainly carried by the second channel layer. Here, since the second channel layer is made of ^IAs, the lower end of the conduction band is the X valley, and its effective trade is 0.
．． It is heavy, 5 me (m is the electron mass), so the electron velocity is small, the drain current decreases, and it exhibits negative differential resistance and negative transconductance. The drain current-drain voltage characteristics are shown in FIG. 3, which shows that the negative differential resistance of the drain current can be controlled by the gate voltage. The factor that determines the maximum operating speed of this element, as in the conventional example, is the time during which the electrons gain energy and become hot, allowing extremely high-speed operation.

As can be seen from the above description, the semiconductor device of the present invention, unlike the conventional example, generates negative differential resistance due to the difference in electron velocity between the first and second channels. Therefore, the gate current is not essential as in the conventional example, and input and output can be separated. This is very advantageous in terms of circuit configuration.

In this embodiment, a grating layer 103. is provided below the first channel layer for supplying electrons. Electron supply layer 104. Each layer of the spacer layer 105 is provided, but this is an FET.
The purpose is to lower the threshold value of the source and drain and to obtain conduction between the source and drain and the first channel layer directly under the gate, and is not essential to the present invention.For example, the source and drain formed by ion implantation and annealing are It can also be omitted by providing an n'' layer.

Furthermore, in this embodiment, the surface of the source electrode portion is partially etched to prevent direct ohmic contact between the source and the second channel layer. This is to prevent electrons from being directly injected from the source into the second channel layer and increase the drain current when a high positive voltage is applied to the gate, and to obtain a large negative differential resistance. However, if the electron velocity in the second channel layer is sufficiently low, this effect can be reduced, and this etching can also be omitted.

A second embodiment of the present invention includes the first embodiment in which the first channel layer 106 is made of 1nxGaI-xAs. Here, In&]1ttx is set to approximately O<x≦0.2, and is set to an extent that misfit dislocation does not occur.

By doing this, the electron mass of the channel layer is reduced,
It becomes possible to facilitate the real space transition of electrons and to reduce the leakage current flowing through the second channel layer when the gate voltage is increased.

Further, as the difference in effective mass becomes larger, the difference in electron velocity between the first and second channel layers becomes larger, and there is also the advantage that the negative differential resistance becomes larger.

A third embodiment includes the first and second embodiments in which impurities are added to the second channel layer 107 to reduce the mobility. In other words, part or all of the second channel layer is doped with p-type and n-type impurities to the same extent, for example, 5XI.
O'' cm is added to compensate for each other and lower the mobility. In this case, the second channel layer is made of GaAs or ^l&
The gate barrier layer 1 is made of AlGaAs with a small ll structure.
By increasing the barrier height of 08, gate leakage current can be controlled. Here, the second channel layer does not need to be completely compensated, and the threshold value can be adjusted by changing the amount of impurities that remain uncompensated.

As a fourth embodiment, in the first, second, and third embodiments, the second channel layer is grown at a low temperature to become a layer containing a large number of defects.

A fifth embodiment has a structure in which a GaAs cap layer is provided on 108 to protect the AlGaAs layer that is easily oxidized.

Up to this point, we have described an example in which the present invention was implemented on a GaAs1 board, but it goes without saying that the present invention can be applied to other material systems.For example, InP is used for the substrate, Ino is used for the first channel layer, 5sGao1Js A in the two-channel layer
lxGa+-++5byAS1-y+Inn in barrier layer
, 5xAIo, and a@As are used.

In other words, the second channel layer formed on top of the first channel layer forms a conduction band discontinuity that acts as a potential barrier with respect to the first channel layer, and has a higher electron velocity than the first channel layer. A gate barrier layer made of a small semiconductor and made of a semiconductor or an insulator is formed on the second channel layer to form a potential barrier with respect to the second channel layer.

Further, a lower barrier layer made of a semiconductor material that forms a conduction band discontinuity that acts as a potential barrier with respect to electrons in the first channel layer is formed below the first channel layer.

Furthermore, n-type impurities are added to part or all of the lower barrier layer.

(Effects of the Invention) The present invention has a conduction band discontinuity on the first channel layer that acts as a potential barrier with respect to the channel layer, and has a lower electron velocity than the channel layer. A second channel layer made of a semiconductor material is formed, a barrier layer made of a semiconductor or an insulator is provided on top of the second channel layer to serve as a potential barrier to the second channel layer, a gate electrode is provided on top of the barrier layer, and a gate electrode is provided on the top of the second channel layer. By providing source and drain ohmic electrodes, the amount of real space transition of electrons from the first channel layer to the second channel layer is changed, and negative differential resistance is generated due to the difference in electron velocity between each channel layer. Therefore, unlike the conventional example, electrons in the channel flow into the gate electrode to generate negative differential resistance, so the input impedance of the gate can be made sufficiently large, and the human output can be separated. Its application in circuits has wide effects.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the semiconductor device of the present invention, FIG. 2 shows the energy band structure of the semiconductor device of FIG. 1, and FIG. 3 shows drain current-drain voltage characteristics. Figure 4 shows the conventional example, No. 51! l indicates the energy band structure of the semiconductor device shown in FIG. l...Semi-insulating GaAs substrate 2...n''-GaAa second conductive layer 3...And-pull lGaAs89 layer 4...Undoped Ga
As channel layer 5...Substrate electrode 6...Source electrode 7...Drain electrode 8...Fermi level 9...Source n0 region 10...Drain voltage characteristics 11. ...Gate electrode 101...Semi-insulating GaAs substrate...Undoped GaAs type 221 layer...Undoped A111Ga+-yAs spacer layer...n' Alo, sGa@, Js electron supply layer...
Undoped A1°, 3Ga6. , As spacer layer...Undoped GaAs first channel layer...Undoped^IAs second channel layer...Undoped AI6.
n5Gao, 5SAs barrier layer...-8I Gate electrode...Source electrode...Drain electrode 1st Figure 09 W5i Goo 11 and Jin Indication: 1999 Patent No. 294599 2゜Name of the invention Semiconductor device 3゜Relationship with the amended person case

Claims (1)

[Scope of Claims] A semiconductor that forms a conduction band discontinuity that acts as a potential barrier with respect to the semiconductor channel layer above the first channel layer made of a semiconductor, and that has a lower electron velocity than the semiconductor channel layer. A gate electrode is provided on the stacked body having a gate barrier layer made of a semiconductor or an insulator that forms a potential barrier on the second channel layer with respect to the second channel layer. A semiconductor device comprising: source and drain electrodes in ohmic contact with the first channel layer and the second channel layer, and both electrodes are arranged to sandwich a gate electrode.