JPH1146136A5 - - Google Patents

Info

Publication number
JPH1146136A5
JPH1146136A5 JP1997200223A JP20022397A JPH1146136A5 JP H1146136 A5 JPH1146136 A5 JP H1146136A5 JP 1997200223 A JP1997200223 A JP 1997200223A JP 20022397 A JP20022397 A JP 20022397A JP H1146136 A5 JPH1146136 A5 JP H1146136A5
Authority
JP
Japan
Prior art keywords
signal
frequency
counter
outputs
dividing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997200223A
Other languages
English (en)
Japanese (ja)
Other versions
JP4015232B2 (ja
JPH1146136A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP20022397A priority Critical patent/JP4015232B2/ja
Priority claimed from JP20022397A external-priority patent/JP4015232B2/ja
Priority to US09/014,250 priority patent/US6031425A/en
Publication of JPH1146136A publication Critical patent/JPH1146136A/ja
Publication of JPH1146136A5 publication Critical patent/JPH1146136A5/ja
Application granted granted Critical
Publication of JP4015232B2 publication Critical patent/JP4015232B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP20022397A 1997-07-25 1997-07-25 プリスケーラ、分周器及びｐｌｌ回路 Expired - Fee Related JP4015232B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP20022397A JP4015232B2 (ja) 1997-07-25 1997-07-25 プリスケーラ、分周器及びｐｌｌ回路
US09/014,250 US6031425A (en) 1997-07-25 1998-01-27 Low power prescaler for a PLL circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20022397A JP4015232B2 (ja) 1997-07-25 1997-07-25 プリスケーラ、分周器及びｐｌｌ回路

Publications (3)

Publication Number Publication Date
JPH1146136A JPH1146136A (ja) 1999-02-16
JPH1146136A5 true JPH1146136A5 (enExample) 2005-05-26
JP4015232B2 JP4015232B2 (ja) 2007-11-28

Family

ID=16420864

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20022397A Expired - Fee Related JP4015232B2 (ja) 1997-07-25 1997-07-25 プリスケーラ、分周器及びｐｌｌ回路

Country Status (2)

Country Link
US (1) US6031425A (enExample)
JP (1) JP4015232B2 (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3313318B2 (ja) * 1998-01-09 2002-08-12 富士通株式会社 Ｐｌｌ回路
US6108393A (en) * 1999-02-25 2000-08-22 Rockwell Collins, Inc. Enhanced prescaler phase interface
JP2000357966A (ja) * 1999-06-14 2000-12-26 Toshiba Corp 周波数シンセサイザ
US7012984B2 (en) * 1999-07-29 2006-03-14 Tropian, Inc. PLL noise smoothing using dual-modulus interleaving
JP2001136059A (ja) * 1999-11-01 2001-05-18 Fujitsu Ltd プリスケーラ及びｐｌｌ回路
KR100329590B1 (ko) * 2000-05-25 2002-03-21 대표이사 서승모 고주파 주파수합성기용 듀얼 모듈러스 프리스케일러
KR100595316B1 (ko) * 2000-09-19 2006-07-03 매그나칩 반도체 유한회사 위상 동기 루프의 프리스케일러
US6437669B1 (en) 2000-09-29 2002-08-20 Applied Micro Circuits Corporation Microwave to millimeter wave frequency substrate interface
US6597246B2 (en) * 2001-05-14 2003-07-22 Dsp Group, Inc. Methods and apparatus for alteration of terminal counts of phase-locked loops
US7171170B2 (en) 2001-07-23 2007-01-30 Sequoia Communications Envelope limiting for polar modulators
KR100492690B1 (ko) * 2002-11-04 2005-06-07 매그나칩 반도체 유한회사 프리스케일러를 포함하는 위상 제어 루프 회로
US6822491B1 (en) * 2003-06-27 2004-11-23 Intel Corporation Frequency prescaler apparatus, method, and system
US7609118B1 (en) 2003-12-29 2009-10-27 Sequoia Communications Phase-locked loop calibration system
US7522017B1 (en) 2004-04-21 2009-04-21 Sequoia Communications High-Q integrated RF filters
US7672648B1 (en) 2004-06-26 2010-03-02 Quintics Holdings System for linear amplitude modulation
US7190756B1 (en) * 2004-09-29 2007-03-13 Xilinx, Inc. Hybrid counter with an asynchronous front end
US7268597B2 (en) * 2005-02-16 2007-09-11 Avago Technologies General Ip (Singapore) Pte. Ltd. Self-initializing frequency divider
US7548122B1 (en) 2005-03-01 2009-06-16 Sequoia Communications PLL with switched parameters
US7479815B1 (en) * 2005-03-01 2009-01-20 Sequoia Communications PLL with dual edge sensitivity
US7595626B1 (en) 2005-05-05 2009-09-29 Sequoia Communications System for matched and isolated references
US7259602B2 (en) * 2005-07-21 2007-08-21 International Business Machines Corporation Method and apparatus for implementing fault tolerant phase locked loop (PLL)
US7379522B2 (en) * 2006-01-11 2008-05-27 Qualcomm Incorporated Configurable multi-modulus frequency divider for multi-mode mobile communication devices
JP4653000B2 (ja) 2006-03-27 2011-03-16 富士通セミコンダクター株式会社 プリスケーラ及びバッファ
US7974374B2 (en) 2006-05-16 2011-07-05 Quintic Holdings Multi-mode VCO for direct FM systems
US7522005B1 (en) 2006-07-28 2009-04-21 Sequoia Communications KFM frequency tracking system using an analog correlator
US7894545B1 (en) 2006-08-14 2011-02-22 Quintic Holdings Time alignment of polar transmitter
US7920033B1 (en) 2006-09-28 2011-04-05 Groe John B Systems and methods for frequency modulation adjustment
US7652517B2 (en) * 2007-04-13 2010-01-26 Atmel Corporation Method and apparatus for generating synchronous clock signals from a common clock signal
TW201009586A (en) * 2008-08-27 2010-03-01 Macroblock Inc Coordinated operation circuit
KR101795438B1 (ko) 2011-06-29 2017-11-09 삼성전자주식회사 주파수 분주기 및 이를 포함하는 위상 고정 루프
TWI499217B (zh) * 2012-12-18 2015-09-01 Univ Nat Cheng Kung 高除數除７預除器及使用該高除數除７預除器之鎖相迴路系統
KR101634674B1 (ko) * 2014-07-07 2016-07-08 (주)에프씨아이 분주 신호 생성 방법과 이를 위한 주파수 분주기

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06276095A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd Ｐｌｌ回路
JP3468964B2 (ja) * 1996-01-29 2003-11-25 富士通株式会社 Ｐｌｌ周波数シンセサイザ回路、比較分周器、及び、スワロウカウンタ
JPH09312567A (ja) * 1996-05-20 1997-12-02 Sony Corp Ｐｌｌ周波数シンセサイザの制御回路

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