JPH11312731A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make feasible the reduction of the yield decline due to the white blemishes, etc., of photodiodes in a complementary metal oxide semiconductor(CMOS) sensor made of a CMOS logic part and the cell part of a photodiode mix-loaded on the same substrate. SOLUTION: Field oxide films 16 are formed on element isolating regions of a CMOS logic part 12, e.g. on an N-type silicon substrate 11 by conventional selective oxidation from conventional technology. Moreover, partial field oxide films 17 thinner than the field oxide films 16 of the CMOS logic part 12 are formed by oxidizing the polycrystalline sicicon films, only used for the selective oxidation on the element separating region of the cell part 13 of photodiode. Through these procedures, the residual stress imposed on the edge parts of the partial field oxide films 17 is reduced so as to erect a structure for avoiding transitional defects.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a CMOS (Compound Device).
lementary Metal Oxide Semiconductor) This is used for a CMOS sensor in which a logic part and a cell part of a photodiode are mounted on the same substrate.

[0002]

2. Description of the Related Art Conventionally, as a method of element isolation in a semiconductor device, a selective oxidation method (LOCOS (LOCal Oxidatio
n of Silicon)) is generally well known. this is,
By oxidizing a polycrystalline silicon film or a silicon substrate while the element region is covered with a nitride (Si ₃ N ₄ ) film,
A field oxide film (selective oxide film) is formed in the element isolation region.

However, in the case of the above-described selective oxidation method, dislocation defects or the like due to the stress of the nitride film are easily generated at the edge portion of the field oxide film, and in particular, crystal defects are likely to be induced during the subsequent device formation due to residual stress. There was a problem.

FIG. 3 shows an example of element isolation by a conventional selective oxidation method using a CMOS sensor as an example. For example, on the surface of the N-type silicon substrate 101, a CMOS
Except for the formation region of the P-channel MOS transistor in the logic portion, the formation region of the N-channel MOS transistor and the cell portion of the photodiode correspond to
P-type well regions 102 and 103 are formed.

The P-type well regions 102, 103
N-type silicon substrate 1 corresponding to the interface with
01 is provided with a field oxide film 104 on the surface thereof. Immediately below each field oxide film 104, a channel stopper layer 105 is provided.

The N channel M of the CMOS logic section
In the formation region of the OS transistor, a gate electrode 102b made of polycrystalline silicon or WSi (tungsten silicide) is provided on the surface of the P-type well region 102 via a gate oxide film 102a.
Then, using the gate electrode 102b as a mask, the N-type source / drain is formed on the surface of the P-type well region 102.
⁺ Type impurity diffusion layers 102c, 102c are formed respectively.

In the region where the P-channel MOS transistor of the CMOS logic section is formed, the N
A gate oxide film 101 is formed on the surface of
A gate electrode 101b made of polycrystalline silicon or WSi is provided via a. Then, using the gate electrode 101b as a mask, the N-type silicon substrate 101 is used.
P ⁺ -type impurity diffusion layers 101c, 101c serving as a source / drain are formed on the surface of the substrate.

On the other hand, in the cell portion, a gate electrode 103b made of polycrystalline silicon or WSi is provided on the surface of the P-type well region 103 via a gate oxide film 103a. And this gate electrode 1
Using the mask 03b as a mask, an N ⁺ -type impurity diffusion layer 103c serving as a drain and an N-layer 103d of a photodiode are formed on the surface of the P-type well region 103, respectively.

In the CMOS sensor having such a configuration, as described above, dislocation defects or the like due to the stress of the nitride film used for forming the field oxide film 104 are likely to occur at the edge of the field oxide film 104. Especially,
If the residual stress induces a crystal defect at the time of forming the cell portion of the photodiode later, the device characteristics are significantly impaired.

As a method for solving such a problem, for example, as shown in FIG.
There is a so-called field CVD method in which an oxide film deposited by our deposition method is etched by a dry etching method or the like to form a field oxide film 204.

However, in the case of this field CVD method, the process is complicated, it is difficult to control the etching rate and the etching angle of the oxide film, and moreover, the etching damages the surface of the N-type silicon substrate 101 greatly. Had been a problem.

[0012]

As described above, conventionally, in the case of the selective oxidation method, as in the case of the field CVD method, the steps are complicated, the control is difficult, and the problems such as damage to the silicon substrate are not solved. However, there has been a problem that residual stress tends to induce crystal defects during the formation of the cell portion of the photodiode, thereby significantly deteriorating device characteristics.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device capable of suppressing generation of dislocation defects at an end of a selective oxide film and improving device characteristics, and a method of manufacturing the same.

[0014]

In order to achieve the above object, in a semiconductor device according to the present invention, a silicon substrate and a silicon substrate selectively provided on a surface portion of the silicon substrate are provided.
A first selective oxide film for element isolation having a first thickness,
A second selective oxide film for element isolation, which is selectively provided on the surface of the silicon substrate and has a second thickness, which is thinner than the first selective oxide film.

Further, in the semiconductor device of the present invention,
In the case where a logic part and a cell part are mixedly mounted on a silicon substrate, the logic part and the cell part are used for element isolation of the logic part,
A first selective oxide film for element isolation having a first thickness,
A second selective oxide film for device isolation having a second thickness, which is used for element isolation of the cell portion and is thinner than the first selective oxide film.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a thermal oxide film on a silicon substrate; a step of forming a polycrystalline silicon film on the thermal oxide film; Forming a nitride film only partially on the polycrystalline silicon film only in the region where the logic portion is to be formed, of the logic portion and the cell portion formed thereon; Selectively removing the nitride film, performing selective oxidation while exposing the polycrystalline silicon film corresponding to the device isolation region of the logic portion, and removing the nitride film in the device isolation region of the cell portion. Selectively removing the corresponding nitride film and exposing the polycrystalline silicon film, and selecting under conditions that only the polycrystalline silicon film corresponding to the element isolation region of the cell portion is oxidized. The first selective oxide film having a first thickness in the element isolation region of the logic portion, and thinner than the first selective oxide film in the element isolation region of the cell portion, Forming a second selective oxide film having a second thickness.

According to the semiconductor device and the method of manufacturing the same of the present invention, a second selective oxide film having a second thickness smaller than the first selective oxide film is selectively formed on the surface of the silicon substrate. become able to. Thereby, it is possible to reduce the residual stress applied to the end of the second selective oxide film.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a CMOS sensor according to an embodiment of the present invention.

For example, on the surface of the N-type silicon substrate 11, an N-channel MOS transistor except for a P-channel MOS transistor forming region 12a of the CMOS logic portion 12 is provided.
P-type well regions 14 and 15 are formed corresponding to the S transistor formation region 12b and the photodiode cell portion 13, respectively.

The surface of the N-type silicon substrate 11 corresponding to the interface with the P-type well region 14 has
A-Co by selective oxidation method (LOCOS method)
A field oxide film (first selective oxide film) 16 having a planar III structure is provided.

On the surface of the N-type silicon substrate 11 corresponding to the interface with the P-type well region 15, only the polycrystalline silicon film used for forming the field oxide film 16 is oxidized. A partial field oxide film (second selective oxide film) 17 having the above structure is provided.

A channel stopper layer 18 is provided directly below the field oxide film 16 and the partial field oxide film 17, respectively. In the formation region 12a of the P-channel MOS transistor of the CMOS logic portion 12, the N-type silicon substrate 11
Is provided with a gate electrode 11b made of polycrystalline silicon or WSi (tungsten silicide) via a gate oxide film 11a. Using the gate electrode 11b as a mask, P ⁺ -type impurity diffusion layers 11c, 11c serving as a source / drain are formed on the surface of the N-type silicon substrate 11, respectively.

In the formation region 12b of the N-channel MOS transistor of the CMOS logic section 12, on the surface of the P-type well region 14, a polysilicon or WSi is formed via a gate oxide film 14a. A gate electrode 14b is provided. Then, using the gate electrode 14b as a mask, the P-type well region 1 is formed.
N ⁺ -type impurity diffusion layers 14c, 14c serving as a source / drain are formed on the surface of the substrate 4, respectively.

On the other hand, in the cell section 13, the P
On the surface of the mold well region 15, a gate electrode 15b made of polycrystalline silicon or WSi is provided via a gate oxide film 15a. And, this gate electrode 15
Using b as a mask, an N ⁺ -type impurity diffusion layer 15c serving as a drain and an N-layer 15d of a photodiode are formed on the surface of the P-type well region 15 respectively.

According to the CMOS sensor having such a configuration, at least the occurrence of dislocation defects at the edge of the partial field oxide film 17 can be suppressed. This prevents crystal defects from being induced during the formation of the N layer 15d of the photodiode, thereby reducing a decrease in yield due to white scratches or the like.

Next, a brief description will be given of a manufacturing process of the CMOS sensor having the above configuration. FIG. 2 schematically shows a method of element isolation in the CMOS logic section 12 and the photodiode cell section 13 in the CMOS sensor described above.

First, for example, as shown in FIG.
The surface of the N-type silicon substrate 11 is oxidized to form a thermal oxide film 21 on the entire surface. Then, diffusion regions (not shown) to be the P-type well regions 14 and 15 are selectively formed on the surface of the N-type silicon substrate 11 via the thermal oxide film 21 and then the thermal oxidation is performed. A polycrystalline silicon film 22 is deposited on the film 21.

Further, Si is formed on the polycrystalline silicon film 22.
After depositing the ₃ N ₄ film 23, the Si ₃ N ₄ film 23 is
EP (Photo Engraving Process) and RIE (Reac
tiveIon Etching) patterning and the above C
Only the MOS logic unit 12 is left.

Furthermore, comprise upper above the Si ₃ N ₄ film 23, the on the polycrystalline silicon film 22 is deposited the Si ₃ N ₄ film 24, thickened only partially in the formation region of the logic unit 12 (the The Si ₃ N ₄ films 23 and 24 are formed only partially in the region where the cell portion 13 is to be formed).

Then, for example, as shown in FIG. 2B, the resist film 25 is used as a photomask, and the Si film corresponding to the formation portion of the field oxide film 16 (element isolation region of the logic portion) is formed by RIE. ₃ N ₄ film 23,2
4 is selectively removed.

Then, the channel stopper layer 18 is formed by ion-implanting N-type impurities into the surface of the N-type silicon substrate 11 from which the Si ₃ N ₄ films 23 and 24 have been removed.

Next, as shown in FIG. 3C, after removing the resist film 25, selective oxidation is performed under predetermined conditions to remove the N-type silicon substrate 11 and the polycrystalline silicon film 22. By oxidizing, a selective oxide film 16a is grown in the element isolation region of the logic section 12.

Next, as shown in FIG. 3D, the resist film 26 is used as a photomask, and the above-mentioned portion corresponding to the formation portion (element isolation region of the cell portion) of the partial field oxide film 17 is formed by RIE. The Si ₃ N ₄ film 24 is selectively removed.

Then, N-type impurities are ion-implanted into the surface of the N-type silicon substrate 11 from which the Si ₃ N ₄ film 24 has been removed, thereby forming the channel stopper layer 18.
To form

Next, as shown in FIG. 2E, after removing the resist film 26, selective oxidation is performed under the condition that only the polycrystalline silicon film 22 is oxidized, and the element of the cell portion 13 is removed. The partial field oxide film 17 is formed in the isolation region.

In this case, the conditions for oxidizing only the polycrystalline silicon film 22 are adjusted by controlling an oxidation rate such as a gas flow rate in an oxidizing atmosphere, an oxidation time, or an oxidation temperature.

At this time, the partial field oxide film 17
The selective oxide film 16a also grows with the formation of the field oxide film 16a, and the field oxide film 16 is formed in the element isolation region of the logic portion 12.

Next, as shown in FIG. 2F, for example, the Si ₃ N ₄ films 23 and 24 and the polycrystalline silicon film not used for forming the field oxide films 16 and the partial field oxide films 17 are formed. 22 and CDE
(Chemical Dry Etching) method.

After removing the thermal oxide film 21,
By forming the P-channel MOS transistor, the N-channel MOS silane transistor, and the photodiode as described above, the CMOS sensor having the configuration shown in FIG. 1 is completed.

As described above, the partial field oxide film thinner than the field oxide film can be selectively formed on the surface of the silicon substrate. In other words, by oxidizing only the polycrystalline silicon film used for forming the field oxide film in the field oxide film used for element isolation in the photodiode cell unit, the field oxide film used for element isolation in the CMOS logic unit is smaller than the field oxide film used for element isolation in the CMOS logic unit. It is made to be thin. As a result, it is possible to reduce the residual stress applied to the edge portion of the field oxide film used for element isolation in the cell portion, and it is possible to suppress the occurrence of dislocation defects.

Moreover, since the thin Si ₃ N ₄ film is formed only in the region where the cell portion is formed, the stress of the Si ₃ N ₄ film at the edge of the field oxide film can be reduced. Become.

Accordingly, it is possible to prevent the occurrence of crystal defects at the edge portion of the field oxide film during the formation of the photodiode and to reduce the decrease in yield due to white flaws and the like, thereby improving the device characteristics. It is what becomes.

When the operating voltage of the cell section is high,
By adjusting the thickness of the polycrystalline silicon film, the withstand voltage can be easily obtained, which is advantageous in the process.

In the above-described embodiment,
Although a CMOS sensor has been described as an example, the present invention is not limited to this, and may be applied to a solid-state imaging device such as a CCD (Charge Coupled Device). Of course, various modifications can be made without departing from the scope of the present invention.

[0045]

As described above, according to the present invention, the occurrence of dislocation defects at the end of the selective oxide film can be suppressed,
A semiconductor device capable of improving device characteristics and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a configuration of a CMOS sensor according to an embodiment of the present invention.

FIG. 2 is also a schematic cross-sectional view for explaining a method of element isolation in the CMOS sensor.

FIG. 3 is shown to explain the prior art and its problems;
FIG. 2 is a schematic sectional view of a CMOS sensor.

FIG. 4 is a schematic sectional view showing another example of the configuration of the conventional CMOS sensor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... N-type silicon substrate 11a ... Gate oxide film 11b ... Gate electrode 11c ... P ⁺ type impurity diffusion layer 12 ... CMOS logic part 12a ... P-channel MOS transistor formation area 12b ... N-channel MOS transistor formation area 13 ... Photo cell portion 14 ... P-type well region 14a ... gate oxide film 14b ... gate electrode 14c ... N ⁺ -type impurity diffusion layer 15 ... P-type well region 15a ... gate oxide film 15b ... gate electrode 15c of the diode ... N ⁺ -type impurity Diffusion layer 15d N-layer of photodiode 16 Field oxide film 16a Selective oxide film 17 Partial field oxide film 18 Channel stopper layer 21 Thermal oxide film 22 Polycrystalline silicon film 23, 24 Si ₃ N ₄ film 25, 26 ... resist film

Claims (12)

[Claims] 1. A silicon substrate, a first selective oxide film selectively provided on a surface portion of the silicon substrate for element isolation having a first thickness, and a selective oxide film on a surface of the silicon substrate. And a second selective oxide film for element isolation having a second film thickness, which is thinner than the first selective oxide film, is provided. 2. The semiconductor according to claim 1, wherein the first selective oxide film is formed by oxidizing the silicon substrate and a polycrystalline silicon film provided on the silicon substrate. apparatus. 3. The semiconductor device according to claim 1, wherein said first selective oxide film is used for element isolation of a logic part. 4. The semiconductor device according to claim 1, wherein said second selective oxide film is formed by oxidizing only a polycrystalline silicon film provided on said silicon substrate. 5. The semiconductor device according to claim 1, wherein said second selective oxide film is used for element isolation of a cell portion. 6. A semiconductor device comprising a logic part and a cell part mounted on a silicon substrate in a mixed manner, wherein said first selective oxidation for element isolation having a first thickness is used for element isolation of said logic part. And a second selective oxide film for element isolation having a second thickness, which is used for element isolation of the cell portion and is thinner than the first selective oxide film. Semiconductor device. 7. The semiconductor according to claim 6, wherein the first selective oxide film is formed by oxidizing the silicon substrate and a polycrystalline silicon film provided on the substrate. apparatus. 8. The semiconductor device according to claim 6, wherein said second selective oxide film is formed by oxidizing only a polycrystalline silicon film provided on said silicon substrate. 9. A step of forming a thermal oxide film on a silicon substrate, a step of forming a polycrystalline silicon film on the thermal oxide film, and a logic part and a cell part formed on the silicon substrate Forming a nitride film only partially on the polycrystalline silicon film only in the formation region of the logic portion; and selectively removing the nitride film corresponding to an element isolation region of the logic portion; A step of performing selective oxidation corresponding to an element isolation region of the logic part while exposing the polycrystalline silicon film; and selectively removing the nitride film corresponding to an element isolation region of the cell part, Exposing a polycrystalline silicon film; and performing selective oxidation under the condition of oxidizing only the polycrystalline silicon film corresponding to the element isolation region of the cell part, A first selective oxide film having one thickness, and in the element isolation region of the cell portion,
Forming a second selective oxide film having a second thickness smaller than the first selective oxide film. 10. The method according to claim 1, further comprising: after selectively removing the nitride film corresponding to the element isolation region of the logic portion, forming a channel stopper layer on the surface of the corresponding silicon substrate. Item 10. The method for manufacturing a semiconductor device according to item 9. 11. The method according to claim 11, further comprising the step of: after selectively removing the nitride film corresponding to the element isolation region of the cell portion, forming a channel stopper layer on the surface of the corresponding silicon substrate. Item 10. The method for manufacturing a semiconductor device according to item 9. 12. The method according to claim 9, wherein the condition for oxidizing only the polycrystalline silicon film is to control an oxidation rate.