KR19980037036A - Structure of CDD solid state image pickup device and its manufacturing method ` - Google Patents
Structure of CDD solid state image pickup device and its manufacturing method ` Download PDFInfo
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- KR19980037036A KR19980037036A KR1019960055724A KR19960055724A KR19980037036A KR 19980037036 A KR19980037036 A KR 19980037036A KR 1019960055724 A KR1019960055724 A KR 1019960055724A KR 19960055724 A KR19960055724 A KR 19960055724A KR 19980037036 A KR19980037036 A KR 19980037036A
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- 239000007787 solid Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 150000004767 nitrides Chemical class 0.000 claims abstract description 22
- 238000003384 imaging method Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000001590 oxidative effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- 229910052814 silicon oxide Inorganic materials 0.000 description 15
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42396—Gate electrodes for field effect devices for charge coupled devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
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- Condensed Matter Physics & Semiconductors (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
본 발명은 고체촬상소자의 게이트 구조 및 그 형성방법에 관한 것으로서, 고체촬상소자의 전하전송부에 형성되는 다중 게이트구조에 있어서, 제 1 게이트의 게이트절연막은 산화막-질화막으로 이루어지며 상기 제 1 게이트를 제외한 다른 게이트의 게이트절연막은 산화막으로 이루어진 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate structure of a solid state image pickup device and a method of forming the same. In a multi-gate structure formed in a charge transfer unit of a solid state image pickup device, a gate insulating film of a first gate is formed of an oxide film-nitride film and the first gate. The gate insulating film of the other gate except for is made of an oxide film.
또한, 본 발명은 다중 폴리실리콘 구조를 형성하여 이루어지는 고체촬상소자의 게이트 형성방법에 있어서, 반도체기판 표면에 제 1 산화막을 형성하는 단계와, 상기 제 1 산화막 상부에 질화막을 형성하는 단계와, 상기 질화막 상부에 제 2 산화막을 형성하는 단계와, 상기 제 2 산화막 상부에 제 1 게이트전극을 선택적으로 형성하는 단계와, 상기 제 1 게이트전극 하부영역 외의 상기 제 2 산화막 및 상기 질화막을 선택적으로 제거하는 단계와, 상기 결과물의 표면에 제 3 산화막을 형성하는 단계와, 상기 제 3 산화막 상부에 상기 제 1 게이트전극과 일부가 오버랩된 제 2 게이트전극을 선택적으로 형성하는 단계를 구비함을 특징으로 한다.In addition, the present invention provides a method of forming a gate of a solid-state imaging device formed by forming a polysilicon structure, the method comprising: forming a first oxide film on the surface of a semiconductor substrate, forming a nitride film on the first oxide film, Forming a second oxide film over the nitride film, selectively forming a first gate electrode over the second oxide film, and selectively removing the second oxide film and the nitride film other than the lower region of the first gate electrode And forming a third oxide film on the surface of the resultant, and selectively forming a second gate electrode partially overlapping with the first gate electrode on the third oxide film. .
Description
본 발명은 씨씨디 고체촬상소자의 구조 및 그 제조방법에 관한 것으로서, 특히 고체촬상소자를 구성하는 전하전송부의 게이트 절연구조 및 그 형성공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a CD solid state image pickup device and a method of manufacturing the same, and more particularly, to a gate insulating structure of a charge transfer unit constituting a solid state image pickup device and a forming process thereof.
씨씨디 고체촬상소자의 감도는 씨씨디의 크기와 게이트절연막의 두께와 밀접한 관계가 있으며, 고체촬상소자의 안정적인 특성 확보를 위해서는 안정적인 게이트절연막의 두께를 확보하는 것이 필수적이다.The sensitivity of the CD solid-state imaging device is closely related to the size of the CD and the thickness of the gate insulating film. In order to secure stable characteristics of the solid state imaging device, it is essential to secure a stable gate insulating film thickness.
도 2 를 참조하면, 종래의 고체촬상소자의 게이트 형성공정은 먼저 실리콘기판(30) 표면에 실리콘산화막(32), 실리콘질화막(34)을 형성하고 그 상부에 게이트산화막(36)을 형성한 후 게이트산화막(36) 상부에 폴리실리콘막을 침적한다. 이어서 사진 및 식각공정으로 상기 폴리실리콘막을 선택적으로 제거하여 제 1 폴리실리콘 게이트(38)를 형성한 후 열산화공정을 실시하여 제 1 폴리실리콘 게이트(38) 표면에 실리콘산화막(40)을 형성한다. 이어서 게이트영역을 제외한 영역에 형성된 상기 게이트산화막과 게이트질화막을 선택적으로 제거하여 도 2a 와 같은 구조를 형성한다.Referring to FIG. 2, in the gate forming process of the conventional solid state imaging device, first, a silicon oxide film 32 and a silicon nitride film 34 are formed on a surface of a silicon substrate 30, and a gate oxide film 36 is formed thereon. A polysilicon film is deposited on the gate oxide film 36. Subsequently, the polysilicon film is selectively removed by a photo and etching process to form a first polysilicon gate 38, and then a thermal oxidation process is performed to form a silicon oxide film 40 on the surface of the first polysilicon gate 38. . Subsequently, the gate oxide film and the gate nitride film formed in a region other than the gate region are selectively removed to form a structure as shown in FIG. 2A.
그 다음, 도 2b 에 도시된 바와 같이, 기판 전면에 게이트질화막(42)과 게이트산화막(44)을 침적한다. 이어서 상기 게이트산화막(44) 상부에 폴리실리콘막을 침적하고 사진 및 식각공정으로 상기 폴리실리콘막을 선택적으로 제거하여, 도 2c 에 도시된 바와 같이, 산화막-질화막-산화막(Oxide-Nitride-Oxide: 이하 ONO 로 약칭함) 구조의 게이트절연막 상부에 제 2 폴리실리콘 게이트(46)를 형성한다.Next, as illustrated in FIG. 2B, the gate nitride film 42 and the gate oxide film 44 are deposited on the entire surface of the substrate. Subsequently, a polysilicon layer is deposited on the gate oxide layer 44 and the polysilicon layer is selectively removed by a photolithography and etching process, and as shown in FIG. 2C, an oxide-nitride-oxide (hereinafter referred to as ONO). A second polysilicon gate 46 is formed on the gate insulating film of the structure.
상기의 공정에 있어서, 제 1 폴리실리콘 게이트의 게이트절연막으로 형성된 게이트질화막의 식각공정시 게이트질화막의 하부에 형성된 게이트산화막(32)이 일부 식각되어 그 두께가 감소하게 되므로 3 중 폴리실리콘 게이트 구조를 사용할 경우 제 1 게이트와 제 3 게이트 간의 게이트절연막 두께차이가 약 70-80Å 정도가 되기 때문에 출력단의 각 게이트의 문턱전압 차이가 생기며 이로 인하여 안정적인 출력 특성확보가 어렵고 각 채널의 게이트 셧오프 전압도 차이가 나므로 전송동작도 불안정하게 된다. 또한 게이트질화막 산화공정시 수직전송단의 확산으로 전송단의 용량이 줄어드는 문제가 발생하여 칩크기가 줄어드는 고집적공정에서는 공정 및 구조적 한계를 나타내는 문제점이 있다.In the above process, during the etching process of the gate nitride film formed of the gate insulating film of the first polysilicon gate, the gate oxide film 32 formed under the gate nitride film is partially etched to reduce the thickness thereof, thereby reducing the triple polysilicon gate structure. When used, the gate insulation film thickness difference between the first gate and the third gate is about 70-80Å, resulting in a difference in threshold voltages of the gates of the output stage, which makes it difficult to obtain stable output characteristics and also a difference in gate shutoff voltage of each channel. Therefore, the transmission operation becomes unstable. In addition, there is a problem in that the capacity of the transfer stage is reduced due to the diffusion of the vertical transfer stage during the gate nitride film oxidation process, and thus the process and structural limitations are exhibited in the highly integrated process in which the chip size is reduced.
또한, 고체촬상소자의 게이트절연막 구조로서 사용되어 왔던 종래의 산화막-질화막-산화막(Oxide-Nitride-Oxide: 이하 ONO 로 약칭함) 구조 또는 산화막-질화막(Oxide-Nitride: 이하 ON 으로 약칭함) 구조는 그 형성공정이 복잡할 뿐만 아니라 각 게이트 형성시 열처리 및 식각공정이 진행되므로 게이트 수가 많아짐에 따라 나중에 형성된 게이트절연막의 두께 차이가 발생하므로 각 게이트의 셧오프 전압이 변화하고 씨씨디의 특성이 변화하여 고체촬상소자의 동작특성 및 감도가 칩에 따라 변화하는 문제점이 있다.In addition, a conventional oxide-nitride-oxide (hereinafter referred to as ONO) structure or an oxide-nitride (hereinafter referred to as ON) structure has been used as a gate insulating film structure of a solid state image pickup device. Since the formation process is not only complicated, but also the heat treatment and etching processes are performed during each gate formation, the thickness of the gate insulation film formed later increases as the number of gates increases, so the shutoff voltage of each gate changes and the characteristics of the CD change. Therefore, there is a problem in that the operation characteristics and the sensitivity of the solid state image pickup device change from chip to chip.
본 발명의 목적은 상기 문제점을 해결하기 위한 것으로 안정적인 게이트절연막의 두께를 확보하여 안정적인 동작특성을 확보할 수 있는 고체촬상소자의 게이트구조 및 그 형성방법을 제공하는 데 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a gate structure of a solid state image pickup device capable of securing stable operating characteristics by securing a stable thickness of a gate insulating film and a method of forming the same.
상기 목적을 달성하기 위한 본 발명의 고체촬상소자의 게이트구조는, 고체촬상소자의 전하전송부에 형성되는 다중 게이트구조에 있어서, 제 1 게이트의 게이트절연막은 산화막-질화막으로 이루어지며 상기 제 1 게이트를 제외한 다른 게이트의 게이트절연막은 산화막으로 이루어진 것을 특징으로 한다.The gate structure of the solid-state imaging device of the present invention for achieving the above object is a multi-gate structure formed in the charge transfer portion of the solid-state imaging device, wherein the gate insulating film of the first gate is made of an oxide film-nitride film and the first gate The gate insulating film of the other gate except for is made of an oxide film.
상기 제 1 게이트의 게이트절연막은 산화막-질화막-질화산화막 구조를 갖는 것도 바람직하다.It is also preferable that the gate insulating film of the first gate has an oxide film-nitride film-nitride oxide film structure.
한편, 본 발명의 고체촬상소자의 게이트 형성방법은, 다중 폴리실리콘 구조를 형성하여 이루어지는 고체촬상소자의 게이트 형성방법에 있어서, 반도체기판 표면에 제 1 산화막을 형성하는 단계와, 상기 제 1 산화막 상부에 질화막을 형성하는 단계와, 상기 질화막 상부에 제 2 산화막을 형성하는 단계와, 상기 제 2 산화막 상부에 제 1 게이트전극을 선택적으로 형성하는 단계와, 상기 제 1 게이트전극 하부영역 외의 상기 제 2 산화막 및 상기 질화막을 선택적으로 제거하는 단계와, 상기 결과물의 표면에 제 3 산화막을 형성하는 단계와, 상기 제 3 산화막 상부에 상기 제 1 게이트전극과 일부가 오버랩된 제 2 게이트전극을 선택적으로 형성하는 단계를 구비함을 특징으로 한다.On the other hand, the gate forming method of the solid state image pickup device of the present invention comprises the steps of: forming a first oxide film on the surface of a semiconductor substrate in the gate formation method of the solid state image pickup device formed by forming a multi-polysilicon structure; Forming a nitride film on the nitride film, forming a second oxide film on the nitride film, selectively forming a first gate electrode on the second oxide film, and forming the second gate electrode other than the lower region of the first gate electrode. Selectively removing an oxide film and the nitride film, forming a third oxide film on a surface of the resultant, and selectively forming a second gate electrode partially overlapping the first gate electrode on the third oxide film Characterized in that it comprises a step.
상기 공정에 있어서, 상기 제 1 게이트전극 하부에 형성된 제 1 산화막, 질화막 및 제 2산화막으로 이루어진 게이트절연막과, 상기 제 2 게이트전극 하부에 형성된 제 1 산화막 및 제 3 산화막으로 이루어진 게이트절연막의 유효 유전막 두께는 동일한 것이 바람직하다.In the above process, an effective dielectric film of a gate insulating film including a first oxide film, a nitride film, and a second oxide film formed under the first gate electrode, and a first oxide film and a third oxide film formed under the second gate electrode. It is preferable that the thickness is the same.
도 1a 내지 도 1c 는 본 발명의 고체촬상소자의 게이트 구조 및 그 형성방법을 설명하기 위한 도면.1A to 1C are views for explaining the gate structure of the solid state image pickup device of the present invention and a method of forming the same.
도 2a 내지 도 2c 는 종래의 고체촬상소자의 게이트 구조 및 그 형성방법을 설명하기 위한 도면.2A to 2C are diagrams for explaining a gate structure of a conventional solid state image pickup device and a method of forming the same.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of the drawings
10,30 : 실리콘기판12,16,20,22,32,36,40,44 : 실리콘산화막10,30: silicon substrate 12,16,20,22,32,36,40,44: silicon oxide film
14,34,42 : 실리콘질화막18,38 : 제 1 폴리실리콘 게이트14,34,42 silicon nitride film 18,38 first polysilicon gate
24,46 : 제 2 폴리실리콘 게이트24,46: second polysilicon gate
이하, 본 발명의 구체적인 실시예를 나타내는 첨부된 도면을 참조하여 더욱 상세히 설명한다.Hereinafter, with reference to the accompanying drawings showing a specific embodiment of the present invention will be described in more detail.
이중 폴리실리콘 게이트 형성공정을 나타내는 도 1a 내지 도 1d 를 참조하여 본 발명의 고체촬상소자의 게이트 형성방법을 설명하면, 먼저 실리콘기판(10)에 열산화공정을 실시하여 기판(10) 표면에 실리콘산화막(12)을 성장시킨 후 상기 실리콘산화막(12) 상부에 LPCVD 방식으로 실리콘질화막(14)을 침적하고 상기 실리콘질화막(14) 표면을 산화시켜 실리콘산화막(16)을 형성한다. 그 다음, 상기 실리콘산화막(16) 상부에 LPCVD 방식으로 제 1 폴리실리콘막을 침적한 후 통상의 게이트 사진 및 식각공정을 실시하여 제 1 폴리실리콘 게이트(18)를 형성하게 되는데, 이때 제 1 폴리실리콘막 하부의 상기 실리콘산화막도 제거된다. 이어서, 상기 제 1 폴리실리콘 게이트(18)의 표면을 산화시켜 제 1 폴리실리콘 게이트(18) 표면에 실리콘산화막(20)을 형성하고 습식식각 방식으로 상기 실리콘질화막을 선택적으로 식각하여 상기 실리콘산화막(12)을 노출시킨다.Referring to FIGS. 1A to 1D illustrating the polysilicon gate forming process, the gate forming method of the solid state image pickup device according to the present invention will be described first. After the oxide film 12 is grown, the silicon nitride film 14 is deposited on the silicon oxide film 12 by LPCVD, and the surface of the silicon nitride film 14 is oxidized to form a silicon oxide film 16. Thereafter, the first polysilicon film is deposited on the silicon oxide film 16 by LPCVD, and then the first polysilicon gate 18 is formed by performing a normal gate photograph and etching process, wherein the first polysilicon is formed. The silicon oxide film under the film is also removed. Subsequently, the surface of the first polysilicon gate 18 is oxidized to form a silicon oxide film 20 on the surface of the first polysilicon gate 18, and the silicon nitride film is selectively etched by a wet etching method. 12).
그 다음, 도 1b 와 같이 기판 전면에 LPCVD 방식으로 실리콘산화막(22)을 침적하고, 상기 실리콘산화막(22) 상부에 LPCVD 방식으로 제 2 폴리실리콘막을 침적한 후 통상의 게이트 사진 및 식각공정으로 상기 제 2 폴리실리콘막을 선택적으로 제거하여, 도 1c 에 도시된 바와 같이, 제 1 폴리실리콘 게이트(18)와 오버랩된 제 2 폴리실리콘 게이트(24)를 형성한다. 이때 상기 실리콘산화막(22)은 제 1 폴리실리콘 게이트(18)의 하부에 형성된 실리콘산화막(12), 실리콘질화막(14) 및 실리콘산화막(16)으로 이루어진 게이트절연막과, 제 2 폴리실리콘 게이트(24)의 하부에 형성된 실리콘산화막(12) 및 실리콘산화막(22)으로 이루어진 게이트절연막의 유효 유전막 두께가 동일하도록 그 두께를 조절하여 전하전송부의 안정적인 전송 동작특성을 확보하는 것이 중요하다.Subsequently, as shown in FIG. 1B, the silicon oxide film 22 is deposited on the entire surface of the substrate by LPCVD, and the second polysilicon film is deposited on the silicon oxide film 22 by LPCVD. The second polysilicon film is selectively removed to form a second polysilicon gate 24 overlapping the first polysilicon gate 18, as shown in FIG. 1C. In this case, the silicon oxide layer 22 may include a gate insulating layer including the silicon oxide layer 12, the silicon nitride layer 14, and the silicon oxide layer 16 formed under the first polysilicon gate 18, and the second polysilicon gate 24. It is important to ensure stable transfer operation characteristics of the charge transfer part by adjusting the thickness of the gate dielectric film formed of the silicon oxide film 12 and the silicon oxide film 22 formed under the C.sub.
상기와 같이 이루어지는 본 발명에 있어서는 제 2 게이트의 게이트절연막 형성시에 질화막 침적공정이 생략되어 공정이 단순화되며 질화막 산화공정을 거치지 않으므로 채널을 확산을 줄여 채널의 용량을 증가시킬 수 있고 감도 특성을 안정적으로 확보, 조절할 수 있다.In the present invention as described above, the nitride deposition process is omitted when forming the gate insulating film of the second gate, which simplifies the process and does not undergo the nitride film oxidation process, thereby reducing the diffusion of the channel to increase the capacity of the channel and stable sensitivity characteristics. Can be secured and adjusted.
따라서, 본 발명은 각 채널의 셧오프 전압을 안정적으로 확보하여 전송효율도 향상시킬 수 있으며 공정이 단축되어 소자의 신뢰성은 물론 생산성을 향상시킬 수 있는 효과가 있다.Therefore, the present invention can secure the shut-off voltage of each channel to improve the transmission efficiency, the process is shortened, there is an effect that can improve the reliability and productivity of the device.
Claims (7)
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| KR100899546B1 (en) * | 2007-09-04 | 2009-05-27 | (주) 넥스트칩 | Charged Coupled Device and method for manufacturing thereof |
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