JPH08222739A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

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Publication number
JPH08222739A
JPH08222739A JP4929395A JP4929395A JPH08222739A JP H08222739 A JPH08222739 A JP H08222739A JP 4929395 A JP4929395 A JP 4929395A JP 4929395 A JP4929395 A JP 4929395A JP H08222739 A JPH08222739 A JP H08222739A
Authority
JP
Japan
Prior art keywords
film
oxide film
furnace
heat treatment
oxidation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4929395A
Other languages
Japanese (ja)
Other versions
JP3093600B2 (en
Inventor
Tatsuya Usami
達矢 宇佐美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP07049293A priority Critical patent/JP3093600B2/en
Publication of JPH08222739A publication Critical patent/JPH08222739A/en
Application granted granted Critical
Publication of JP3093600B2 publication Critical patent/JP3093600B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: To prevent formation of low quality oxide film due to abnormal oxidation when forming oxide film by a heat treatment step on the surface of a silicide layer. CONSTITUTION: When a WSi layer (silicide layer) 15 is formed on a semiconductor substrate 11 to form an oxide film 18 on the surface of the WSi layer 15 by thermal oxidizing process, the oxygen contamination in a heat treatment furnace in the case of feeding semiconductor device in the furnace is checked later to be slowly oxidized at high temperature. Through these procedures, the rapid oxidation of the WSi layer can be checked by checking the oxygen contamination in the furnace, thereby checking the abnormal oxidation of the WSi layer. Furthermore, a high quality oxide film can be formed by forming the oxide film at high temperature.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は多結晶シリコンで構成さ
れる配線層にシリサイド層を形成して動作の高速化を図
った半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a silicide layer is formed on a wiring layer made of polycrystalline silicon to speed up the operation.

【0002】[0002]

【従来の技術】従来から半導体装置の配線層として多結
晶シリコンを用いたものが提案され、かつその配線抵抗
を低減して動作速度を高めるために配線層にシリサイド
層を形成したものが提案されている。例えば、図3はそ
の一例を製造工程順に示す図である。先ず、図3(a)
に示すように、シリコン基板21を酸化して素子分離酸
化膜22とゲート酸化膜23を形成し、その上にCVD
法により100nm〜200nm程度の多結晶シリコン
膜24を堆積し、さらにスパッタ法により100nm〜
300nm程度のWSi膜(タングステンシリサイド
膜)25を形成する。
2. Description of the Related Art Conventionally, there has been proposed one using polycrystalline silicon as a wiring layer of a semiconductor device, and one having a silicide layer formed on the wiring layer in order to reduce the wiring resistance and increase the operation speed. ing. For example, FIG. 3 is a diagram showing an example thereof in the order of manufacturing steps. First, FIG. 3 (a)
As shown in FIG. 3, the silicon substrate 21 is oxidized to form an element isolation oxide film 22 and a gate oxide film 23, and CVD is performed thereon.
A polycrystalline silicon film 24 having a thickness of about 100 nm to 200 nm is deposited by a sputtering method,
A WSi film (tungsten silicide film) 25 having a thickness of about 300 nm is formed.

【0003】次いで、フォトリソグラフィ法ににより、
これらのWSi膜25と多結晶シリコン膜24をパター
ニングし、図3(b)に示すようにゲート電極26を形
成する。その後、ゲート電極26をマスクとして不純物
のイオン注入を行って低濃度の浅いソース・ドレイン拡
散層29を形成する。この後、不純物活性化を含めLD
D構造を形成するために約800℃の高温減圧CVD法
により鎖線で示すようにSiO2 膜27を約200nm
程度堆積し、これを反応性イオンエッチングによってエ
ッチングして図3(c)に示すようにゲート電極26の
側面にSiO2膜27を残して側壁を形成する。
Then, by the photolithography method,
The WSi film 25 and the polycrystalline silicon film 24 are patterned to form a gate electrode 26 as shown in FIG. After that, ion implantation of impurities is performed using the gate electrode 26 as a mask to form a shallow source / drain diffusion layer 29 of low concentration. After this, LD including impurity activation
In order to form the D structure, a SiO 2 film 27 is formed to a thickness of about 200 nm by a high temperature low pressure CVD method at about 800 ° C. as shown by a chain line.
3C is deposited, and this is etched by reactive ion etching to form a side wall while leaving the SiO 2 film 27 on the side surface of the gate electrode 26 as shown in FIG. 3C.

【0004】この側壁27を形成することにより、WS
i膜25の上面が露出されるため、その後のイオン注入
の際のマスクとして、全面に約800℃の高温減圧CV
D膜28を20nm程度成長する。しかしながら、この
WSi膜25の熱処理工程で大気の酸素の巻き込みがあ
ると、WSi膜25が深く酸化され、図3(d)に示す
ようにWSi膜25の上面に異常酸化膜28Aが形成さ
れる。この異常酸化膜28AはSiO2 とWO3 からな
るものと考えられ体積膨張は約2.7倍に達し、この異
常酸化膜28Aによってゲート電極26の抵抗は大幅に
増大し、またしばしば膜が剥がれるといった問題が生じ
る。
By forming the side wall 27, WS
Since the upper surface of the i film 25 is exposed, a high temperature depressurized CV of about 800 ° C. is formed on the entire surface as a mask for the subsequent ion implantation.
The D film 28 is grown to about 20 nm. However, if oxygen in the atmosphere is trapped in the heat treatment step of the WSi film 25, the WSi film 25 is deeply oxidized and an abnormal oxide film 28A is formed on the upper surface of the WSi film 25 as shown in FIG. 3D. . It is considered that the abnormal oxide film 28A is composed of SiO 2 and WO 3, and the volume expansion reaches about 2.7 times, and the resistance of the gate electrode 26 is greatly increased by the abnormal oxide film 28A, and the film is often peeled off. Such a problem occurs.

【0005】この異常酸化膜が形成される原因について
検討すると、このWSi膜25の異常酸化は図3(b)
後の酸化膜27の形成工程では生じていないことから、
WSiが結晶化されていることが前提となっている。こ
の異常酸化に対して特開平4−266031号公報に記
載されている説明では、この現象はWSix 膜がアモル
ファス状態では酸素混入雰囲気に晒したときにWSix
中のSiが主として酸化されて酸化膜(SiO2 )が形
成され、これが表面を覆ってその後の酸化が抑えられ
る。これに対して、WSix 膜が結晶化されてWSi2
結晶粒が表面を覆っていると酸素混入雰囲気に晒したと
き酸化によるSiの消費に対してSiの供給が不十分と
なりWが直接酸化される事態になるものと思われる。
Examining the cause of the formation of the abnormal oxide film, the abnormal oxidation of the WSi film 25 is shown in FIG.
Since it did not occur in the subsequent step of forming the oxide film 27,
It is premised that WSi is crystallized. The abnormality in the description disclosed in Japanese Patent Laid-Open No. 4-266031 is to oxidation, WSi x when this phenomenon WSi x film is exposed to oxygen contamination atmosphere in an amorphous state
The Si inside is mainly oxidized to form an oxide film (SiO 2 ), which covers the surface and suppresses the subsequent oxidation. On the other hand, the WSi x film is crystallized and WSi 2
When the crystal grains cover the surface, it is considered that when exposed to an oxygen-containing atmosphere, the supply of Si is insufficient with respect to the consumption of Si due to oxidation and W is directly oxidized.

【0006】このため、前記公報では、1度目の熱処理
により、金属シリサイドが結晶化した後に、酸素混入の
熱処理に先立って露出している金属シリサイド膜表面を
再度シリコン膜で覆い、その後に酸化熱処理してシリコ
ン膜を酸化膜に変換することで金属シリサイド膜の異常
酸化を防止するようにしている。
Therefore, in the above publication, after the metal silicide is crystallized by the first heat treatment, the exposed metal silicide film surface is again covered with the silicon film before the heat treatment of oxygen mixture, and then the oxidation heat treatment is performed. Then, the silicon film is converted into an oxide film to prevent abnormal oxidation of the metal silicide film.

【0007】また、他の対策として、特開平2−740
31号公報では、シリサイドが結晶化した後、露出シリ
サイド表面を500℃以下で処理して酸化膜を被膜を形
成している。このため、低温での処理のため、結晶化さ
れたWSi2 表面が酸化されることがなく、WSiの酸
化が防止される。
As another countermeasure, Japanese Patent Laid-Open No. 2-740
In Japanese Patent Laid-Open No. 31-31, after the silicide is crystallized, the exposed silicide surface is treated at 500 ° C. or lower to form an oxide film. Therefore, since the crystallized WSi 2 surface is not oxidized due to the low temperature treatment, the oxidation of WSi is prevented.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、これら
公報に記載の対策では、1度目の熱処理によってシリサ
イドが結晶化された後の熱処理前にシリコン膜で表面を
被覆するという、特開平4−266031号公報の対策
では、シリコン膜を形成した後の酸化処理の工程数が余
分にかかり、工程数が増えるという問題がある。
However, in the measures described in these publications, the surface is covered with a silicon film before the heat treatment after the silicide is crystallized by the first heat treatment, which is disclosed in JP-A-4-266031. The countermeasure of the publication has a problem that the number of steps of the oxidation treatment after forming the silicon film is extra and the number of steps is increased.

【0009】また、500℃以下でSiO2 堆積すると
いう、特開平2−74031号公報の対策では、膜中不
純物の増加や薄膜の均一性の悪化等の膜品質の低下によ
り特性の不安定を招き、またイオン注入の拡散のための
熱処理工程と異常酸化防止用の膜を堆積する工程が2工
程かかり、工程数が増えるという問題が生じる。
In addition, in the countermeasure of Japanese Patent Laid-Open No. 2-74031, in which SiO 2 is deposited at 500 ° C. or lower, instability of characteristics is caused by deterioration of film quality such as increase of impurities in the film and deterioration of uniformity of thin film. In addition, there is a problem that the heat treatment step for diffusion of ion implantation and the step of depositing a film for preventing abnormal oxidation take two steps, and the number of steps increases.

【0010】[0010]

【発明の目的】本発明は、製造工程を増やすことなく、
しかも特性の安定化を図る一方で、シリサイド層の異常
酸化を防止することを可能にした半導体装置の製造方法
を提供することにある。
The object of the present invention is to increase the number of manufacturing steps without increasing
Moreover, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which can prevent abnormal oxidation of a silicide layer while stabilizing the characteristics.

【0011】[0011]

【課題を解決するための手段】本発明の製造方法は、半
導体基板上にシリサイド層を形成し、そのシリサイド層
の表面に熱酸化処理により酸化膜を形成するに際し、半
導体基板を熱処理炉に入れる際に炉内の酸素混入を防止
し、その後高温で緩やかな酸化処理を行うことを特徴と
する。
According to the manufacturing method of the present invention, when a silicide layer is formed on a semiconductor substrate and an oxide film is formed on the surface of the silicide layer by thermal oxidation, the semiconductor substrate is placed in a heat treatment furnace. At that time, it is characterized in that oxygen is prevented from being mixed in the furnace, and then a gentle oxidation treatment is performed at a high temperature.

【0012】例えば、半導体基板を熱処理炉に入れる際
に、炉内に窒素を充満させておき、炉内への酸素の混入
を防止する。また、シリサイド層がタングステンシリサ
イド層であり、その表面に熱処理によりシリコン酸化膜
を形成する場合には、半導体基板を熱処理炉に入れる際
の温度を500℃以下とし、その後500℃以上の高温
処理中で緩やかな酸化を行うことが好ましい。
For example, when the semiconductor substrate is put into the heat treatment furnace, the furnace is filled with nitrogen to prevent oxygen from being mixed into the furnace. When the silicide layer is a tungsten silicide layer and a silicon oxide film is formed on its surface by heat treatment, the temperature when the semiconductor substrate is put in the heat treatment furnace is set to 500 ° C. or lower, and then high temperature treatment of 500 ° C. or higher is performed. Therefore, it is preferable to perform mild oxidation.

【0013】[0013]

【作用】シリサイド層上に酸化膜を成長する際に、炉内
への酸素の混入を防ぐことで、シリサイド層が急激に酸
化されることが防止でき、シリサイド層における異常酸
化が防止される。また、その後に高温で酸化膜を形成す
ることで、高品質の酸化膜の形成が可能となる。
When the oxide film is grown on the silicide layer, oxygen is prevented from being mixed into the furnace, whereby the silicide layer can be prevented from being rapidly oxidized and abnormal oxidation in the silicide layer can be prevented. Further, by forming the oxide film at a high temperature thereafter, it becomes possible to form a high quality oxide film.

【0014】[0014]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明をMOS型半導体装置に適用した一実
施例を製造工程順に示す断面図である。先ず、図1
(a)に示すように、シリコン基板11の表面に酸化処
理を施し、SiO2 膜(シリコン酸化膜)からなる素子
分離酸化膜12とゲート酸化膜13を形成する。そし
て、その上にCVD法によって100nm〜200nm
程度の厚さの多結晶シリコン膜14を堆積し、続いてス
パッタ法によって100nm〜300nm程度のWSi
膜(タングステンシリサイド膜)15を形成する。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing an embodiment in which the present invention is applied to a MOS semiconductor device in the order of manufacturing steps. First, Fig. 1
As shown in (a), the surface of the silicon substrate 11 is oxidized to form an element isolation oxide film 12 and a gate oxide film 13 made of a SiO 2 film (silicon oxide film). Then, 100 nm to 200 nm is formed thereon by the CVD method.
A polycrystalline silicon film 14 having a thickness of about 100 nm to 300 nm is deposited by a sputtering method.
A film (tungsten silicide film) 15 is formed.

【0015】次いで、図1(b)のように、フォトレジ
ストを用いたフォトリソグラフィ法により、これらのW
Si膜15と多結晶シリコン膜14をパターニングし、
ゲート電極16及び図外の配線を形成する。その後、ゲ
ート電極をマスクとして不純物のイオン注入を行って低
濃度の浅いソース・ドレイン拡散層19を形成する。
Next, as shown in FIG. 1B, these W's are formed by a photolithography method using a photoresist.
Patterning the Si film 15 and the polycrystalline silicon film 14,
The gate electrode 16 and the wiring not shown are formed. After that, ion implantation of impurities is performed using the gate electrode as a mask to form a low concentration shallow source / drain diffusion layer 19.

【0016】その後、図1(c)に鎖線で示すように、
不純物活性化を含め、LDD構造を形成するために約8
00℃の高温減圧CVD法によりSiO2 膜(シリコン
酸化膜)17を約200nm程度堆積し、続いてこれを
反応性イオンエッチングによってエッチングすることで
ゲート電極側面にSiO2 膜17を残し、側壁とする。
このエッチングによりWSi膜15の上面は露出され
る。
After that, as shown by the chain line in FIG.
Approximately 8 to form LDD structure including impurity activation
A SiO 2 film (silicon oxide film) 17 having a thickness of about 200 nm is deposited by a high-temperature low-pressure CVD method at 00 ° C., and then this is etched by reactive ion etching to leave the SiO 2 film 17 on the side surface of the gate electrode and form a sidewall. To do.
The upper surface of the WSi film 15 is exposed by this etching.

【0017】しかる後、図1(d)のように、全面に約
800℃の高温減圧CVD法によりSiO2 膜18を2
0nm程度成長する。このSiO2 膜18は、後工程で
のLDD構造を形成する際のイオン注入に際して、ゲー
ト電極をマスクするためのものである。このとき、入炉
時に炉内と炉下にN2 を充満させ、大気の酸素混入を遮
断して急激な酸化を防ぐようにする。これにより、高温
熱処理によって形成される良質の薄い酸化膜によってW
Si膜の表面が覆われることになり、この場合、WSi
膜15の異常酸化が生じることなくSiO2 膜18が成
長できる。
Thereafter, as shown in FIG. 1D, a SiO 2 film 18 is formed on the entire surface by high temperature decompression CVD at about 800 ° C.
It grows to about 0 nm. This SiO 2 film 18 is for masking the gate electrode at the time of ion implantation for forming an LDD structure in a later step. At this time, N 2 is filled in the furnace and at the bottom of the furnace at the time of entering the furnace to prevent oxygen from being mixed into the atmosphere to prevent rapid oxidation. As a result, the high-quality thin oxide film formed by the high-temperature heat treatment causes the W
The surface of the Si film is covered, and in this case WSi
The SiO 2 film 18 can grow without abnormal oxidation of the film 15.

【0018】ここで、本発明においては、図2に示すよ
うに、前記したイオン注入のマスク用の高温減圧CVD
酸化膜の入炉時に500℃以下で入炉を行い、炉内を真
空引きし、かつ炉内をN2 で充満状態にした後、約80
0℃に温度を上げCVD膜を成長させると、WSi膜1
5の異常酸化を防止できる。この理由は、500℃以下
で入炉すると、入炉時の急激な酸化を防いで、その後N
2 中での800℃熱処理でWSi膜15上に薄い酸化膜
を形成でき、その後の酸化膜成長を行ってもWSi膜1
5上の薄い酸化膜によりWSi膜15の異常酸化が防止
できる。
Here, in the present invention, as shown in FIG. 2, high-temperature low-pressure CVD for the above-mentioned ion implantation mask is used.
Approximately 80 after the furnace was evacuated at a temperature of 500 ° C. or less, the furnace was evacuated, and the furnace was filled with N 2 when the oxide film was blasted.
When the temperature is raised to 0 ° C. and the CVD film is grown, the WSi film 1
The abnormal oxidation of No. 5 can be prevented. The reason for this is that if you enter the furnace below 500 ° C, you can prevent the rapid oxidation at the time of entering the furnace and
A thin oxide film can be formed on the WSi film 15 by heat treatment at 800 ° C. in 2
The thin oxide film on 5 can prevent abnormal oxidation of the WSi film 15.

【0019】因みに、本発明の製造方法により形成した
酸化膜と、前記した特開平2−74031号公報のよう
に500℃以下で成長した酸化膜とを比較した場合、公
報記載の技術では20nm以下の膜厚均一性(R/2
X)が5〜10%であったのに対し、本発明方法では高
温減圧CVD酸化膜を使用しているために1〜6%程度
と膜厚均一性の向上が図れ、さらにはトランジスタの特
性安定を得ることが可能とされた。
Incidentally, when comparing the oxide film formed by the manufacturing method of the present invention with the oxide film grown at 500 ° C. or lower as in the above-mentioned Japanese Patent Application Laid-Open No. 2-74031, it is 20 nm or less in the technique disclosed in the publication. Thickness uniformity (R / 2
X) was 5 to 10%, whereas in the method of the present invention, the high temperature decompression CVD oxide film was used, so that the film thickness uniformity could be improved to about 1 to 6%, and the transistor characteristics were further improved. It was possible to obtain stability.

【0020】ここで、前記実施例では本発明のシリサイ
ド層としてWSiの場合を例として説明しているが、M
o(モリブデン)、Ti(チタン)等の金属を用いたシ
リサイド層においても同様に本発明を適用することがで
きる。ただし、この場合は使用する金属の種類によって
前記した温度を多少相違させることが必要となることも
ある。
In the above embodiments, the case where WSi is used as the silicide layer of the present invention has been described as an example.
The present invention can be similarly applied to a silicide layer using a metal such as o (molybdenum) or Ti (titanium). However, in this case, it may be necessary to make the temperature slightly different depending on the type of metal used.

【0021】[0021]

【発明の効果】以上説明したように本発明は、シリサイ
ド層の表面に熱酸化処理により酸化膜を形成するに際
し、半導体基板を熱処理炉に入れる際に炉内の酸素混入
を防止し、その後高温で緩やかな酸化処理を行うので、
シリサイド層における急激な酸化を防止して異常酸化を
防止でき、かつ一方では高温の酸化により高品質の酸化
膜を形成することができる。
As described above, according to the present invention, when the oxide film is formed on the surface of the silicide layer by the thermal oxidation treatment, oxygen is prevented from being mixed in the furnace when the semiconductor substrate is put into the heat treatment furnace, and then the high temperature Since a gentle oxidation process is performed with
Abrupt oxidation in the silicide layer can be prevented to prevent abnormal oxidation, and on the other hand, high-temperature oxidation can form a high-quality oxide film.

【0022】例えば、半導体基板を熱処理炉に入れる際
に、炉内に窒素を充満させておくことで、炉内への酸素
の混入を防止することができる。また、シリサイド層が
タングステンシリサイド層の場合には、半導体基板を熱
処理炉に入れる際の温度を500℃以下とし、その後5
00℃以上の高温、例えば800℃の処理中で緩やかな
酸化を行うことで、シリサイド層の異常酸化を防ぎ、高
品質の酸化膜が形成される。
For example, when the semiconductor substrate is put into the heat treatment furnace, by filling the furnace with nitrogen, oxygen can be prevented from entering the furnace. When the silicide layer is a tungsten silicide layer, the temperature when the semiconductor substrate is put in the heat treatment furnace is set to 500 ° C. or lower, and then 5
By performing gentle oxidation in a high temperature of 00 ° C. or higher, for example, 800 ° C., abnormal oxidation of the silicide layer is prevented and a high quality oxide film is formed.

【0023】また、本発明の方法では、特開平4−26
6031号公報の技術に比較して、シリコン膜の形成や
その後の酸化工程が削減でき、製造工程が簡略化でき
る。また、特開平2−74031号公報の技術に比較し
て、高温での酸化膜成長を行うことができ、膜厚均一性
が向上され、高品質化が可能となる。また、不純物の活
性化のための高温熱処理と酸化膜成長を1工程で行うこ
とができるという効果がある。
Further, according to the method of the present invention, Japanese Patent Laid-Open No. 4-26 is used.
Compared with the technique of the 6031 publication, the silicon film formation and the subsequent oxidation process can be reduced, and the manufacturing process can be simplified. Further, as compared with the technique disclosed in Japanese Patent Application Laid-Open No. 2-74031, the oxide film can be grown at a high temperature, the film thickness uniformity can be improved, and the quality can be improved. Further, there is an effect that the high temperature heat treatment for activating the impurities and the oxide film growth can be performed in one step.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を製造工程順に示す断面図で
ある。
FIG. 1 is a sectional view showing an embodiment of the present invention in the order of manufacturing steps.

【図2】本発明における工程の一部の温度管理の状態を
説明するための図である。
FIG. 2 is a diagram for explaining a temperature control state of a part of the process in the present invention.

【図3】従来の製造方法の一例を工程順に示す断面図で
ある。
FIG. 3 is a cross-sectional view showing an example of a conventional manufacturing method in the order of steps.

【符号の説明】[Explanation of symbols]

11 シリコン基板 14 多結晶シリコン膜 15 WSi膜 16 ゲート電極 17 SiO2 膜 18 SiO2 11 silicon substrate 14 polycrystalline silicon film 15 WSi film 16 gate electrode 17 SiO 2 film 18 SiO 2 film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上にシリサイド層を形成し、
そのシリサイド層の表面に熱酸化処理により酸化膜を形
成する工程を含む半導体装置の製造方法において、前記
半導体基板を熱処理炉に入れる際に、炉内の酸素混入を
防止し、その後高温で緩やかな酸化処理を行うことを特
徴とする半導体装置の製造方法。
1. A silicide layer is formed on a semiconductor substrate,
In a method for manufacturing a semiconductor device including a step of forming an oxide film on the surface of the silicide layer by thermal oxidation, when the semiconductor substrate is put in a heat treatment furnace, oxygen in the furnace is prevented from being mixed, and thereafter the temperature is moderated at a high temperature. A method for manufacturing a semiconductor device, which comprises performing an oxidation treatment.
【請求項2】 半導体基板を熱処理炉に入れる際に、炉
内に窒素を充満させておく請求項1の半導体装置の製造
方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the furnace is filled with nitrogen when the semiconductor substrate is put into the heat treatment furnace.
【請求項3】 シリサイド層がタングステンシリサイド
層であり、その表面に熱処理によりシリコン酸化膜を形
成する請求項1または2の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide layer is a tungsten silicide layer, and a silicon oxide film is formed on the surface thereof by heat treatment.
【請求項4】 半導体基板を熱処理炉に入れる際の温度
を500℃以下とし、その後500℃以上の高温処理中
で緩やかな酸化を行う請求項3の半導体装置の製造方
法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the temperature at which the semiconductor substrate is put in the heat treatment furnace is set to 500 ° C. or lower, and then the mild oxidation is performed during a high temperature treatment of 500 ° C. or higher.
JP07049293A 1995-02-15 1995-02-15 Method for manufacturing semiconductor device Expired - Fee Related JP3093600B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP07049293A JP3093600B2 (en) 1995-02-15 1995-02-15 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07049293A JP3093600B2 (en) 1995-02-15 1995-02-15 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH08222739A true JPH08222739A (en) 1996-08-30
JP3093600B2 JP3093600B2 (en) 2000-10-03

Family

ID=12826875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP07049293A Expired - Fee Related JP3093600B2 (en) 1995-02-15 1995-02-15 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3093600B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006303404A (en) * 2005-04-22 2006-11-02 Hynix Semiconductor Inc Manufacturing method of semiconductor element
US7732272B2 (en) 2002-11-19 2010-06-08 Oki Semiconductor Co., Ltd. Method of manufacturing semiconductor element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274031A (en) * 1988-09-09 1990-03-14 Matsushita Electron Corp Manufacture of semiconductor device
JPH04155967A (en) * 1990-10-19 1992-05-28 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274031A (en) * 1988-09-09 1990-03-14 Matsushita Electron Corp Manufacture of semiconductor device
JPH04155967A (en) * 1990-10-19 1992-05-28 Fujitsu Ltd Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732272B2 (en) 2002-11-19 2010-06-08 Oki Semiconductor Co., Ltd. Method of manufacturing semiconductor element
JP2006303404A (en) * 2005-04-22 2006-11-02 Hynix Semiconductor Inc Manufacturing method of semiconductor element

Also Published As

Publication number Publication date
JP3093600B2 (en) 2000-10-03

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