JPH11219302A5 - - Google Patents

Info

Publication number
JPH11219302A5
JPH11219302A5 JP1998310268A JP31026898A JPH11219302A5 JP H11219302 A5 JPH11219302 A5 JP H11219302A5 JP 1998310268 A JP1998310268 A JP 1998310268A JP 31026898 A JP31026898 A JP 31026898A JP H11219302 A5 JPH11219302 A5 JP H11219302A5
Authority
JP
Japan
Prior art keywords
data processor
instruction
predetermined
instructions
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1998310268A
Other languages
English (en)
Japanese (ja)
Other versions
JP4883824B2 (ja
JPH11219302A (ja
Filing date
Publication date
Priority claimed from US08/963,321 external-priority patent/US6000029A/en
Application filed filed Critical
Publication of JPH11219302A publication Critical patent/JPH11219302A/ja
Publication of JPH11219302A5 publication Critical patent/JPH11219302A5/ja
Application granted granted Critical
Publication of JP4883824B2 publication Critical patent/JP4883824B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP31026898A 1997-11-03 1998-10-30 デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置 Expired - Fee Related JP4883824B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/963,321 US6000029A (en) 1997-11-03 1997-11-03 Method and apparatus for affecting subsequent instruction processing in a data processor
US963321 1997-11-03

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2009035190A Division JP4750865B2 (ja) 1997-11-03 2009-02-18 デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置

Publications (3)

Publication Number Publication Date
JPH11219302A JPH11219302A (ja) 1999-08-10
JPH11219302A5 true JPH11219302A5 (enExample) 2005-11-17
JP4883824B2 JP4883824B2 (ja) 2012-02-22

Family

ID=25507071

Family Applications (2)

Application Number Title Priority Date Filing Date
JP31026898A Expired - Fee Related JP4883824B2 (ja) 1997-11-03 1998-10-30 デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置
JP2009035190A Expired - Fee Related JP4750865B2 (ja) 1997-11-03 2009-02-18 デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2009035190A Expired - Fee Related JP4750865B2 (ja) 1997-11-03 2009-02-18 デ―タ・プロセッサにおいて後続の命令処理に影響を及ぼす方法および装置

Country Status (8)

Country Link
US (2) US6000029A (enExample)
EP (1) EP0913767B1 (enExample)
JP (2) JP4883824B2 (enExample)
KR (1) KR100588790B1 (enExample)
CN (1) CN1098487C (enExample)
DE (1) DE69810064T2 (enExample)
SG (2) SG101487A1 (enExample)
TW (1) TW494363B (enExample)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7805724B1 (en) * 1998-05-27 2010-09-28 Arc International I.P., Inc. Apparatus, method and computer program for dynamic slip control in real-time scheduling
JP2000330785A (ja) * 1999-05-18 2000-11-30 Sharp Corp 実時間プロセッサおよび命令実行方法
US6618800B1 (en) * 2000-01-18 2003-09-09 Systemonic Ag Procedure and processor arrangement for parallel data processing
GB2369464B (en) 2000-11-27 2005-01-05 Advanced Risc Mach Ltd A data processing apparatus and method for saving return state
US6857036B2 (en) * 2001-07-17 2005-02-15 Hewlett Packard Development Company, L.P. Hardware method for implementing atomic semaphore operations using code macros
US20030154347A1 (en) * 2002-02-12 2003-08-14 Wei Ma Methods and apparatus for reducing processor power consumption
US7542566B2 (en) 2003-04-18 2009-06-02 Ip-First, Llc Apparatus and method for performing transparent cipher block chaining mode cryptographic functions
US7536560B2 (en) 2003-04-18 2009-05-19 Via Technologies, Inc. Microprocessor apparatus and method for providing configurable cryptographic key size
US7532722B2 (en) * 2003-04-18 2009-05-12 Ip-First, Llc Apparatus and method for performing transparent block cipher cryptographic functions
US7519833B2 (en) 2003-04-18 2009-04-14 Via Technologies, Inc. Microprocessor apparatus and method for enabling configurable data block size in a cryptographic engine
US7502943B2 (en) 2003-04-18 2009-03-10 Via Technologies, Inc. Microprocessor apparatus and method for providing configurable cryptographic block cipher round results
US7925891B2 (en) 2003-04-18 2011-04-12 Via Technologies, Inc. Apparatus and method for employing cryptographic functions to generate a message digest
US7900055B2 (en) 2003-04-18 2011-03-01 Via Technologies, Inc. Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms
US7392400B2 (en) 2003-04-18 2008-06-24 Via Technologies, Inc. Microprocessor apparatus and method for optimizing block cipher cryptographic functions
US7321910B2 (en) 2003-04-18 2008-01-22 Ip-First, Llc Microprocessor apparatus and method for performing block cipher cryptographic functions
US7844053B2 (en) 2003-04-18 2010-11-30 Ip-First, Llc Microprocessor apparatus and method for performing block cipher cryptographic functions
US7529367B2 (en) 2003-04-18 2009-05-05 Via Technologies, Inc. Apparatus and method for performing transparent cipher feedback mode cryptographic functions
US7529368B2 (en) 2003-04-18 2009-05-05 Via Technologies, Inc. Apparatus and method for performing transparent output feedback mode cryptographic functions
US7539876B2 (en) 2003-04-18 2009-05-26 Via Technologies, Inc. Apparatus and method for generating a cryptographic key schedule in a microprocessor
CN100495324C (zh) * 2006-07-27 2009-06-03 中国科学院计算技术研究所 复杂指令集体系结构中的深度优先异常处理方法
US9317460B2 (en) 2012-06-15 2016-04-19 International Business Machines Corporation Program event recording within a transactional environment
US9336046B2 (en) 2012-06-15 2016-05-10 International Business Machines Corporation Transaction abort processing
US10437602B2 (en) 2012-06-15 2019-10-08 International Business Machines Corporation Program interruption filtering in transactional execution
US20130339680A1 (en) 2012-06-15 2013-12-19 International Business Machines Corporation Nontransactional store instruction
US8880959B2 (en) 2012-06-15 2014-11-04 International Business Machines Corporation Transaction diagnostic block
US8688661B2 (en) 2012-06-15 2014-04-01 International Business Machines Corporation Transactional processing
US9384004B2 (en) 2012-06-15 2016-07-05 International Business Machines Corporation Randomized testing within transactional execution
US8966324B2 (en) 2012-06-15 2015-02-24 International Business Machines Corporation Transactional execution branch indications
US9361115B2 (en) 2012-06-15 2016-06-07 International Business Machines Corporation Saving/restoring selected registers in transactional processing
US9448796B2 (en) 2012-06-15 2016-09-20 International Business Machines Corporation Restricted instructions in transactional execution
US9367323B2 (en) 2012-06-15 2016-06-14 International Business Machines Corporation Processor assist facility
US9348642B2 (en) 2012-06-15 2016-05-24 International Business Machines Corporation Transaction begin/end instructions
US9436477B2 (en) 2012-06-15 2016-09-06 International Business Machines Corporation Transaction abort instruction
US9740549B2 (en) 2012-06-15 2017-08-22 International Business Machines Corporation Facilitating transaction completion subsequent to repeated aborts of the transaction
US9442737B2 (en) 2012-06-15 2016-09-13 International Business Machines Corporation Restricting processing within a processor to facilitate transaction completion
US9772854B2 (en) 2012-06-15 2017-09-26 International Business Machines Corporation Selectively controlling instruction execution in transactional processing
US8682877B2 (en) 2012-06-15 2014-03-25 International Business Machines Corporation Constrained transaction execution
CN110535790B (zh) * 2019-08-23 2022-03-18 天津芯海创科技有限公司 基于semaphore的交换芯片异常报文处理方法
US12039363B2 (en) * 2022-06-29 2024-07-16 Red Hat, Inc. Synchronizing concurrent tasks using interrupt deferral instructions
US20240370261A1 (en) * 2023-05-03 2024-11-07 Texas Instruments Incorporated Systems and Methods Providing Pause for Interrupts and Shared Memory Access

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5440049A (en) * 1977-09-06 1979-03-28 Toshiba Corp Information process system
US4236204A (en) 1978-03-13 1980-11-25 Motorola, Inc. Instruction set modifier register
US4435766A (en) * 1981-06-16 1984-03-06 International Business Machines Corporation Nested resource control using locking and unlocking routines with use counter for plural processes
CN1004234B (zh) * 1985-04-01 1989-05-17 坦德姆计算机有限公司 增强的中央处理器(cpu)微转移结构
US4764893A (en) * 1985-04-26 1988-08-16 International Business Machines Corporation Noise-immune interrupt level sharing
CN1009399B (zh) * 1987-06-02 1990-08-29 德国Itt工业股份公司 中央处理器
US5499356A (en) * 1989-12-29 1996-03-12 Cray Research, Inc. Method and apparatus for a multiprocessor resource lockout instruction
JPH03210649A (ja) * 1990-01-12 1991-09-13 Fujitsu Ltd マイクロコンピュータおよびそのバスサイクル制御方法
JP2665813B2 (ja) * 1990-02-23 1997-10-22 三菱電機株式会社 記憶制御装置
JPH05508496A (ja) * 1990-06-11 1993-11-25 クレイ、リサーチ、インコーポレーテッド 命令をロードおよびフラグする方法および装置
JPH0467229A (ja) * 1990-07-06 1992-03-03 Hitachi Ltd マイクロプロセッサおよびメモリシステム
JPH0474229A (ja) * 1990-07-17 1992-03-09 Toshiba Corp 情報処理装置
JPH04306735A (ja) * 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
US5301312A (en) * 1991-08-21 1994-04-05 International Business Machines Corporation Method and system for utilizing benign fault occurrence to measure interrupt-blocking times
US5283870A (en) * 1991-10-04 1994-02-01 Bull Hn Information Systems Inc. Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
JPH05143322A (ja) * 1991-11-15 1993-06-11 Sanyo Electric Co Ltd マイクロコンピユータ
EP0555680B1 (en) * 1992-02-14 1999-10-13 Motorola, Inc. A method and apparatus for determining instruction execution ordering in a data processing system
US5590380A (en) * 1992-04-22 1996-12-31 Kabushiki Kaisha Toshiba Multiprocessor system with processor arbitration and priority level setting by the selected processor
JPH06110846A (ja) * 1992-09-25 1994-04-22 Fujitsu Ltd 排他制御方式
US5768619A (en) * 1996-02-16 1998-06-16 Advanced Micro Devices, Inc. Method and system for enabling and disabling functions in a peripheral device for a processor system

Similar Documents

Publication Publication Date Title
JPH11219302A5 (enExample)
WO2002008893A8 (en) A microprocessor having an instruction format containing explicit timing information
EP1096386A3 (en) Interrupt control apparatuses and methods
AU7371700A (en) Hardware and software co-simulation including executing an analyzed user program
EP1367837A4 (en) IMAGE PROCESSING, PICTURE PROCESSING PROGRAM AND IMAGE PROCESSOR
HK1054102A1 (en) Method and apparatus for maintaining the temperature of a microprocessor using a firmware assisted interrupt mechanism
EP1206951A3 (en) Information processing method
WO2005001686A3 (en) Data packet arithmetic logic devices and methods
WO2006107581A3 (en) System for speculative branch prediction optimization and method thereof
WO2002067118A3 (en) Method and system for passing objects in a distributed system using serialization contexts
WO2002046920A3 (en) Multi-cycle instructions
WO2002037271A3 (en) Method and apparatus for processing program loops
WO2002050666A3 (en) Method and apparatus for processing program loops in parallel
WO2003055247A3 (en) Communications device, method and program for receiving process execution, and computer-readable recording medium having same program recorded thereon
WO2002042905A8 (en) Method and apparatus for processing program loops
WO2007076190A3 (en) Efficient task scheduling by assigning fixed registers to scheduler
WO2002037270A3 (en) Hardware loops
JPS55162155A (en) Interrupting circuit of microcomputer
JPS5537663A (en) Start system of option hardware
JPH11267355A5 (enExample)
JPS5583951A (en) Information processing system
JPH1168495A5 (enExample)
JPS5362946A (en) Data processor
WO2002042897A3 (en) Data processing apparatus
WO2002010916A3 (en) Datapath control circuit with adjustable delay elements