JPH10232818A5 - - Google Patents

Info

Publication number
JPH10232818A5
JPH10232818A5 JP1998004583A JP458398A JPH10232818A5 JP H10232818 A5 JPH10232818 A5 JP H10232818A5 JP 1998004583 A JP1998004583 A JP 1998004583A JP 458398 A JP458398 A JP 458398A JP H10232818 A5 JPH10232818 A5 JP H10232818A5
Authority
JP
Japan
Prior art keywords
programming
memory controller
memory
data
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1998004583A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10232818A (ja
Filing date
Publication date
Priority claimed from EP97410009A external-priority patent/EP0855653B1/en
Application filed filed Critical
Publication of JPH10232818A publication Critical patent/JPH10232818A/ja
Publication of JPH10232818A5 publication Critical patent/JPH10232818A5/ja
Pending legal-status Critical Current

Links

JP10004583A 1997-01-23 1998-01-13 メモリ・コントローラ Pending JPH10232818A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97410009.1 1997-01-23
EP97410009A EP0855653B1 (en) 1997-01-23 1997-01-23 Memory controller with a programmable strobe delay

Publications (2)

Publication Number Publication Date
JPH10232818A JPH10232818A (ja) 1998-09-02
JPH10232818A5 true JPH10232818A5 (enExample) 2005-08-04

Family

ID=8229944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10004583A Pending JPH10232818A (ja) 1997-01-23 1998-01-13 メモリ・コントローラ

Country Status (3)

Country Link
EP (1) EP0855653B1 (enExample)
JP (1) JPH10232818A (enExample)
DE (1) DE69731066T2 (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067594A (en) 1997-09-26 2000-05-23 Rambus, Inc. High frequency bus system
US7050959B1 (en) 1999-12-23 2006-05-23 Intel Corporation Dynamic thermal management for integrated circuits
US6578125B2 (en) * 2000-02-14 2003-06-10 Sanyo Electric Co., Ltd. Memory access circuit and memory access control circuit
JP2001337862A (ja) * 2000-05-29 2001-12-07 Fujitsu Ltd メモリシステム及びそのセットアップ方法
WO2002001363A1 (en) * 2000-06-27 2002-01-03 Matsushita Electric Industrial, Co., Ltd. Memory control device, and memory control method
KR100389916B1 (ko) * 2000-08-28 2003-07-04 삼성전자주식회사 메모리 모듈 및 메모리 컨트롤러
US6553472B2 (en) 2001-01-12 2003-04-22 Sun Microsystems, Inc. Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
EP1253521B1 (en) * 2001-04-24 2011-01-26 Rambus Inc. Method and apparatus for signaling between devices of a memory system
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US6697926B2 (en) * 2001-06-06 2004-02-24 Micron Technology, Inc. Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device
JP2002366421A (ja) * 2001-06-07 2002-12-20 Oki Electric Ind Co Ltd メモリ制御回路とメモリ制御方法
US6918048B2 (en) * 2001-06-28 2005-07-12 Intel Corporation System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment
US20040215912A1 (en) * 2003-04-24 2004-10-28 George Vergis Method and apparatus to establish, report and adjust system memory usage
EP1479883A1 (de) 2003-05-10 2004-11-24 Universität Stuttgart Verfahren und Vorrichtung zur Reinigung von Abgasen
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals
US7966439B1 (en) * 2004-11-24 2011-06-21 Nvidia Corporation Apparatus, system, and method for a fast data return memory controller
CN101401165B (zh) * 2006-03-13 2012-08-29 Nxp股份有限公司 电子电路、双倍数据率接口和处理器以及双倍数据率传输的方法
US20100312981A1 (en) * 2008-01-29 2010-12-09 Panasonic Corporation Memory access timing adjustment device and memory access timing adjustment method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5335337A (en) * 1989-01-27 1994-08-02 Digital Equipment Corporation Programmable data transfer timing
US5615358A (en) * 1992-05-28 1997-03-25 Texas Instruments Incorporated Time skewing arrangement for operating memory in synchronism with a data processor
US5509138A (en) * 1993-03-22 1996-04-16 Compaq Computer Corporation Method for determining speeds of memory modules
US5557782A (en) * 1994-07-12 1996-09-17 Zenith Data Systems Corporation Flexible deterministic state machine
EP0800684A4 (en) * 1995-10-26 1998-03-25 Motorola Inc METHOD AND DEVICE FOR CODING AND DECODING A MOVED FRAME DIFFERENCE

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