JPH10189806A - Semiconductor device and junction structure of semiconductor device and substrate - Google Patents
Semiconductor device and junction structure of semiconductor device and substrateInfo
- Publication number
- JPH10189806A JPH10189806A JP34192096A JP34192096A JPH10189806A JP H10189806 A JPH10189806 A JP H10189806A JP 34192096 A JP34192096 A JP 34192096A JP 34192096 A JP34192096 A JP 34192096A JP H10189806 A JPH10189806 A JP H10189806A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- solder balls
- solder
- ball
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ボールグリッドア
レイパッケージを有する半導体装置およびその半導体装
置と基板の接合構造に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a ball grid array package and a bonding structure between the semiconductor device and a substrate.
【０００２】[0002]
【従来の技術】多ピンの半導体装置を基板に実装する技
術として、外部の基板と接合するための半田や金からな
るボールバンプをパッケージの下面に格子状に配置した
ボールグリッドアレイパッケージが従来から用いられて
いる。2. Description of the Related Art As a technique for mounting a multi-pin semiconductor device on a substrate, a ball grid array package in which ball bumps made of solder or gold for bonding to an external substrate are arranged in a lattice pattern on the lower surface of the package has been used. Used.
【０００３】図６および図７は、従来のボールグリッド
アレイパッケージと基板の構成を示すものである。ボー
ルグリッドアレイパッケージでは、図６に示すように、
配線（図示略）が施された基板１上に導電性樹脂により
半導体素子２が接着され、その半導体素子２と基板１の
端子同士が金線３により接続された上、樹脂４で封止さ
れている。そして、基板１の裏面には表面側から引き回
された配線パターン上に半田ボール５が格子状に配置さ
れている。実装時においては、図７に示すように、熱風
等により半田ボール５を溶解すると、ボールグリッドア
レイが半田ボール５の溶解した分だけ沈み込んだ状態で
基板６に固定される。FIGS. 6 and 7 show the configuration of a conventional ball grid array package and a substrate. In the ball grid array package, as shown in FIG.
A semiconductor element 2 is adhered by a conductive resin onto a substrate 1 on which wiring (not shown) is provided, and the terminals of the semiconductor element 2 and the substrate 1 are connected by a gold wire 3 and sealed with a resin 4. ing. On the back surface of the substrate 1, solder balls 5 are arranged in a grid on a wiring pattern routed from the front surface side. At the time of mounting, as shown in FIG. 7, when the solder balls 5 are melted by hot air or the like, the ball grid array is fixed to the substrate 6 in a state where the ball grid array sinks by the amount of the melted solder balls 5.
【０００４】ところが、ボールグリッドアレイパッケー
ジの場合、多ピンの半導体装置を対象とすることから、
半田ボール５が比較的狭いピッチでパッケージ下面の全
面にわたって設けられている。そのため、半田ボール５
が溶解した際に、場合によっては半田ボール５同士が繋
がってしまう（この状態を半田ブリッジという）恐れが
あった。However, in the case of a ball grid array package, since it is intended for a multi-pin semiconductor device,
Solder balls 5 are provided over the entire lower surface of the package at a relatively narrow pitch. Therefore, solder balls 5
In some cases, the solder balls 5 may be connected to each other when this is melted (this state is called a solder bridge).
【０００５】そこで、これを回避する手段が特開平６−
２１６３３号公報（以下、公知例１という）に開示され
ている。公知例１では、図８に示すように、基板８上に
配置したチップ部品（図示略）と基板８を接続するため
のランド９ａ、９ｂ間にフォト式ソルダーレジスト工法
を用いて絶縁凸部１０を設けることにより、ランド９
ａ、９ｂ間の半田ブリッジを防止している。In order to avoid this, Japanese Patent Laid-Open No.
No. 21633 (hereinafter referred to as known example 1). In the known example 1, as shown in FIG. 8, an insulating convex portion 10 is formed between a chip component (not shown) arranged on the substrate 8 and lands 9a and 9b for connecting the substrate 8 by using a photo-type solder resist method. Lands 9
Solder bridges between a and 9b are prevented.
【０００６】また、特開昭５８−１４８４３４号公報
（以下、公知例２という）、および特開昭６１−２０３
６４８号公報（以下、公知例３という）には、主にフリ
ップチップＩＣに関する半導体装置と基板の構成が開示
されている。Further, JP-A-58-148434 (hereinafter referred to as known example 2) and JP-A-61-203
Japanese Patent Application Laid-Open No. 648 (hereinafter referred to as Known Example 3) discloses a configuration of a semiconductor device and a substrate mainly related to a flip-chip IC.
【０００７】公知例２では、図９に示すように、基板１
１上にパターン形成された電極導体１２を覆う感光性樹
脂からなる半田ダム１３が形成され、さらに電極導体１
２上のフリップチップＩＣ１４との接続部（半田ダム１
３の開口部）には予備半田１５と半田ボール１６が形成
されている。そして、この半田ボール１６がフリップチ
ップＩＣ１４上の半田バンプ１７と接合されている。こ
のように、フリップチップＩＣ等の電気部品を半田ボー
ルを介して基板に接続することにより、高密度で微小な
電気部品の生産性向上を図っている。In the known example 2, as shown in FIG.
A solder dam 13 made of a photosensitive resin is formed on the electrode conductor 12 so as to cover the patterned electrode conductor 12.
2 (the solder dam 1)
In the (opening 3), a preliminary solder 15 and a solder ball 16 are formed. The solder balls 16 are joined to the solder bumps 17 on the flip chip IC 14. As described above, the productivity of high-density and minute electric components is improved by connecting the electric components such as flip-chip ICs to the substrate via the solder balls.
【０００８】また、公知例３では、図１０に示すよう
に、フリップチップＩＣ１８上の半田バンプ１９の周辺
に感光性樹脂等からなる半田ダム２０が設けられてお
り、この半田ダム２０が、半田バンプ１９と基板２１上
の電極導体２２を接合する際の半田ショート（ブリッ
ジ）を防止するとともに、高密度実装を可能にしてい
る。In the prior art 3, as shown in FIG. 10, a solder dam 20 made of a photosensitive resin or the like is provided around the solder bump 19 on the flip chip IC 18, and the solder dam 20 This prevents solder shorts (bridges) when joining the bumps 19 and the electrode conductors 22 on the substrate 21 and enables high-density mounting.
【０００９】[0009]
【発明が解決しようとする課題】ところで、上記公知例
１は、チップ部品が実装される基板側に絶縁凸部を設け
た構成であり、実装時には印刷法によってランド上に半
田を載せるというものである。そこで、仮にこの基板構
成をボールグリッドアレイパッケージに適用したとして
も、ボールグリッドアレイパッケージでは半田ボールの
ピッチが例えば１．２７ｍｍ、１．０ｍｍと極めて狭
く、かつ、各半田ボールの位置精度が悪い場合、実装時
に絶縁凸部が半田ボール間に位置せず、接触することが
考えられる。その場合、実装作業に支障をきたすことで
生産性が低下したり、実装の信頼性が低下する恐れがあ
る。The above-mentioned known example 1 has a configuration in which an insulating convex portion is provided on a substrate side on which a chip component is mounted. At the time of mounting, solder is placed on a land by a printing method. is there. Therefore, even if this substrate configuration is applied to a ball grid array package, in the ball grid array package, the pitch of the solder balls is extremely narrow, for example, 1.27 mm and 1.0 mm, and the positional accuracy of each solder ball is poor. In addition, it is conceivable that the insulating protrusions are not located between the solder balls at the time of mounting and come into contact with each other. In that case, there is a possibility that productivity may be reduced due to hindrance to the mounting work, or mounting reliability may be reduced.
【００１０】一方、公知例２、３においては、基板側ま
たはフリップチップＩＣ側に感光性樹脂等の絶縁材料か
らなる半田ダムが形成されているものの、実装後の状態
での半田ダム厚が半田ボールの高さより低いため、半田
ショートが発生する恐れが充分にある。On the other hand, in the known examples 2 and 3, although a solder dam made of an insulating material such as a photosensitive resin is formed on the substrate side or the flip chip IC side, the thickness of the solder dam after mounting is reduced. Since the height is lower than the height of the ball, there is a possibility that a solder short may occur.
【００１１】本発明は、上記の課題を解決するためにな
されたものであって、ボールグリッドアレイパッケージ
実装時の半田ショート（ブリッジ）発生を確実に防止し
て、生産性の向上ならびに実装信頼性の向上を図り得る
半導体装置および半導体装置と基板の接合構造を提供す
ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is possible to reliably prevent the occurrence of solder shorts (bridges) when mounting a ball grid array package, thereby improving productivity and mounting reliability. It is an object of the present invention to provide a semiconductor device and a bonding structure between a semiconductor device and a substrate that can improve the semiconductor device.
【００１２】[0012]
【課題を解決するための手段】上記の目的を達成するた
めに、本発明の請求項１に記載の半導体装置は、外部の
基板と接合するための複数の半田ボールが下面に配置さ
れたボールグリッドアレイパッケージを有する半導体装
置において、全ての隣接する半田ボールの間に絶縁性材
料からなる壁部が設けられたことを特徴とするものであ
る。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a plurality of solder balls for bonding to an external substrate; In a semiconductor device having a grid array package, a wall portion made of an insulating material is provided between all adjacent solder balls.
【００１３】また、請求項２に記載の半導体装置は、前
記壁部が複数の分割された壁部で構成され、これら複数
の壁部の間には間隙が設けられていることを特徴とする
ものである。Further, the semiconductor device according to the present invention is characterized in that the wall is constituted by a plurality of divided walls, and a gap is provided between the plurality of walls. Things.
【００１４】そして、本発明の請求項３に記載の半導体
装置と基板の接合構造は、外部の基板と接合するための
複数の半田ボールが下面に配置されたボールグリッドア
レイパッケージを有する半導体装置において、全ての隣
接する半田ボールの間に、絶縁性材料からなりその高さ
が半田ボールの高さよりも低い壁部が設けられ、半田ボ
ールが溶解して外部の基板と接合された状態で、壁部の
先端が基板表面に当接していることを特徴とするもので
ある。According to a third aspect of the present invention, there is provided a semiconductor device having a ball grid array package in which a plurality of solder balls for bonding to an external substrate are arranged on a lower surface. A wall portion made of an insulating material and having a height lower than the height of the solder ball is provided between all adjacent solder balls, and the wall is formed in a state where the solder ball is melted and joined to an external substrate. The tip of the portion is in contact with the substrate surface.
【００１５】また、請求項４に記載の半導体装置と基板
の接合構造は、前記壁部が複数の分割された壁部で構成
され、これら複数の壁部の間には間隙が設けられている
ことを特徴とするものである。Further, in the bonding structure of the semiconductor device and the substrate according to a fourth aspect, the wall portion is constituted by a plurality of divided wall portions, and a gap is provided between the plurality of wall portions. It is characterized by the following.
【００１６】そして、本発明の請求項５に記載の半導体
装置と基板の接合構造は、外部の基板と接合するための
複数の半田ボールが下面に配置されたボールグリッドア
レイパッケージを有する半導体装置において、全ての隣
接する半田ボールの間に、絶縁性材料からなりその高さ
が半田ボールの高さよりも高い壁部が設けられ、半田ボ
ールが溶解して外部の基板と接合された状態で、壁部の
先端が基板に設けられた溝の内部に挿入されていること
を特徴とするものである。According to a fifth aspect of the present invention, there is provided a semiconductor device having a ball grid array package in which a plurality of solder balls for bonding to an external substrate are arranged on a lower surface. A wall portion made of an insulating material and having a height higher than the height of the solder ball is provided between all adjacent solder balls, and the wall is formed in a state where the solder ball is melted and joined to an external substrate. The distal end of the portion is inserted into a groove provided in the substrate.
【００１７】また、請求項６に記載の半導体装置と基板
の接合構造は、前記壁部が複数の分割された壁部で構成
され、これら複数の壁部の間には間隙が設けられている
ことを特徴とするものである。Further, in the bonding structure of the semiconductor device and the substrate according to the present invention, the wall portion is constituted by a plurality of divided wall portions, and a gap is provided between the plurality of wall portions. It is characterized by the following.
【００１８】本発明の半導体装置によれば、外部の基板
に接合する際に半田ボールを溶解させても、各半田ボー
ルが絶縁性材料からなる壁部で隔離されるため、半田ボ
ール同士でショート（ブリッジ）が発生することがな
い。また、間隙を設けた複数の壁部を用いた場合、実装
時の熱により発生するガスやフラックス洗浄液等がその
間隙から通り抜ける。According to the semiconductor device of the present invention, even when the solder balls are melted at the time of bonding to the external substrate, each solder ball is isolated by the wall portion made of the insulating material, so that the solder balls are short-circuited. (Bridge) does not occur. When a plurality of walls having a gap are used, gas generated by heat during mounting, a flux cleaning liquid, and the like pass through the gap.
【００１９】また、本発明の半導体装置と基板の接合構
造によれば、壁部の高さが半田ボールの高さよりも低い
場合、高い場合のいずれにおいても、半田ボールが溶解
した時に壁部の先端が基板に当接する構成となってい
る。そのため、半田ボールが壁部により（高さ方向に
は）完全に隔離され、半田ボールのショート（ブリッ
ジ）発生をより確実に防止すると同時に、壁部が半導体
装置と基板間の間隔を一定に保持するスペーサの役目を
果たし、半導体装置が基板上に安定して固定される。Further, according to the joint structure of the semiconductor device and the substrate of the present invention, when the height of the wall portion is lower than the height of the solder ball, and when the height of the wall portion is higher, when the solder ball is melted, The tip is in contact with the substrate. As a result, the solder balls are completely isolated (in the height direction) by the walls, thereby more reliably preventing short-circuiting (bridging) of the solder balls, and at the same time, the walls keep the distance between the semiconductor device and the substrate constant. The semiconductor device functions as a spacer, and the semiconductor device is stably fixed on the substrate.
【００２０】[0020]
【発明の実施の形態】以下、本発明の第１の実施の形態
を図１〜図３を参照して説明する。図１は本実施の形態
のボールグリッドアレイパッケージを有する半導体装置
２４と基板２５（実装側）を示す図、図２は半導体装置
２４と基板２５を接合した状態を示す図、図３は半導体
装置２４の裏面を示す図、である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a semiconductor device 24 having a ball grid array package of the present embodiment and a substrate 25 (on the mounting side), FIG. 2 is a diagram showing a state where the semiconductor device 24 and the substrate 25 are joined, and FIG. FIG. 24 is a diagram showing the back surface of No. 24.
【００２１】本半導体装置２４は、図１に示すように、
配線（図示略）が施された基板２６上に導電性樹脂によ
り半導体素子２７が接着され、その半導体素子２７と基
板２６の端子同士が金線２８により接続された上、樹脂
２９で封止されている。また、図３に示すように、基板
２６の裏面には表面側から引き回された配線パターン
（図示せず）上に半田ボール３０が格子状に配置されて
いる。As shown in FIG. 1, the present semiconductor device 24
A semiconductor element 27 is adhered by a conductive resin onto a substrate 26 on which wiring (not shown) is provided, and the terminals of the semiconductor element 27 and the substrate 26 are connected by a gold wire 28 and sealed with a resin 29. ing. Also, as shown in FIG. 3, on the back surface of the substrate 26, solder balls 30 are arranged in a grid pattern on a wiring pattern (not shown) routed from the front surface side.
【００２２】そして、基板２６の裏面には、全ての隣接
する半田ボール３０の間に絶縁性材料からなる壁部３１
が設けられている。この壁部３１は全てが連続した格子
状のものではなく、分割された複数の壁部で構成されて
いる。そして、各壁部３１の間には間隙が設けられてお
り、個々の半田ボール３０は壁部３１によってその四方
を完全には囲まれていない。また、壁部３１の高さは半
田ボール３０の高さより低くなっている。なお、壁部３
１を構成する絶縁性材料には種々のものを適用すること
ができるが、例えば熱特性、強度に優れたポリイミド等
を用いることができる。On the back surface of the substrate 26, a wall 31 made of an insulating material is interposed between all adjacent solder balls 30.
Is provided. The wall portion 31 is not a continuous lattice, but is composed of a plurality of divided wall portions. A gap is provided between the walls 31, and the individual solder balls 30 are not completely surrounded on all four sides by the walls 31. The height of the wall 31 is lower than the height of the solder ball 30. The wall 3
Various materials can be applied to the insulating material that constitutes No. 1; for example, polyimide or the like having excellent thermal characteristics and strength can be used.
【００２３】上記構成の半導体装置２４を基板２５に実
装する際には、図２に示すように、半導体装置２４を基
板２５上の所定の位置に載置した後、半田ボール３０に
熱風等を当てて半田ボール３０を溶解することにより、
ボールグリッドアレイが半田ボール３０の溶解した分だ
け沈み込み、壁部３１の先端が基板２５に当接した状態
で基板２５に固定される。When mounting the semiconductor device 24 having the above configuration on the substrate 25, as shown in FIG. 2, the semiconductor device 24 is placed at a predetermined position on the substrate 25, and then hot air or the like is applied to the solder balls 30. By melting the solder balls 30 by applying
The ball grid array sinks by the amount of the melted solder balls 30, and is fixed to the substrate 25 in a state where the tip of the wall portion 31 contacts the substrate 25.
【００２４】本実施の形態の半導体装置２４によれば、
基板２５に実装する際に半田ボール３０を溶解させて
も、各半田ボール３０が壁部３１で隔離されるため、隣
接する半田ボール３０間でショート（ブリッジ）が発生
するのを防止することができる。また、壁部３１が半田
ボール３０の四方を完全に囲まない構成となっているた
め、実装時の熱により発生するガスやフラックス洗浄液
等を壁部３１の間隙から逃がすことができ、それらによ
る不具合が生じることがない。According to the semiconductor device 24 of the present embodiment,
Even when the solder balls 30 are melted when mounted on the substrate 25, each solder ball 30 is isolated by the wall portion 31, so that a short circuit (bridge) between the adjacent solder balls 30 can be prevented. it can. Further, since the wall portion 31 does not completely surround the four sides of the solder ball 30, gas generated by heat at the time of mounting, a flux cleaning liquid, and the like can escape from the gap of the wall portion 31. Does not occur.
【００２５】また、この半導体装置２４と基板２５の接
合構造によれば、半田ボール３０が溶解した時に壁部３
１の先端が基板２５に当接する構成となっているため、
高さが低い半田ダムを用いた従来のものと異なり、半田
ボール３０が溶解した状態で半田ボール３０が壁部３１
によって高さ方向に完全に隔離され、半田ボール３０の
ショート（ブリッジ）発生をより確実に防止することが
できる。さらに、壁部３１が半導体装置２４と基板２５
間の間隔を一定に保持するスペーサの役目を果たし、半
導体装置２４を基板２５上に安定して固定することがで
きる。According to the bonding structure of the semiconductor device 24 and the substrate 25, when the solder ball 30 is melted,
1 is configured to abut on the substrate 25,
Unlike the conventional one using a low solder dam, the solder ball 30 is melted in the wall portion 31 in a state where the solder ball 30 is melted.
Accordingly, the solder balls 30 are completely isolated in the height direction, and the occurrence of short-circuit (bridge) of the solder balls 30 can be more reliably prevented. Further, the wall 31 is formed between the semiconductor device 24 and the substrate 25.
The semiconductor device 24 can stably be fixed on the substrate 25 by serving as a spacer for maintaining a constant interval between them.
【００２６】以下、本発明の第２の実施の形態を図４、
図５を参照して説明する。図４は本実施の形態の半導体
装置３３と基板３２（実装側）を示す図、図５は半導体
装置３３と基板３２を接合した状態を示す図、である。Hereinafter, a second embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 4 is a diagram showing the semiconductor device 33 of this embodiment and the substrate 32 (on the mounting side), and FIG. 5 is a diagram showing a state where the semiconductor device 33 and the substrate 32 are joined.
【００２７】本実施の形態の場合、図４に示すように、
半導体装置３３本体は第１の実施の形態と同様である
が、壁部３２の高さだけが第１の実施の形態と異なり、
半田ボール３０の高さより高いものとなっている。一
方、実装側の基板２５は、第１の実施の形態では表面が
平坦なものを用いたのに対して、本実施の形態では半導
体装置３３の壁部３２に対応する位置に溝２５ａを形成
したものを用いる。In the case of this embodiment, as shown in FIG.
The semiconductor device 33 body is the same as that of the first embodiment, but only the height of the wall 32 is different from that of the first embodiment.
It is higher than the height of the solder ball 30. On the other hand, the substrate 25 on the mounting side has a flat surface in the first embodiment, whereas a groove 25a is formed at a position corresponding to the wall 32 of the semiconductor device 33 in the present embodiment. Use what was done.
【００２８】上記構成の半導体装置３３を基板２５に実
装する際には、図５に示すように、半導体装置３３を基
板２５上に載置した後、半田ボール３０に熱風等を当て
て半田ボール３０を溶解すると、ボールグリッドアレイ
が半田ボール３０の溶解した分だけ沈み込み、壁部３２
の先端が基板２５の溝２５ａ内に入り込んだ状態で基板
２５に固定される。When mounting the semiconductor device 33 having the above configuration on the substrate 25, as shown in FIG. 5, the semiconductor device 33 is placed on the substrate 25, and then the solder balls 30 are exposed to hot air or the like. When the solder balls 30 are melted, the ball grid array sinks by the amount of the melted solder balls 30, and
Is fixed to the substrate 25 in a state where the tip of the substrate enters the groove 25a of the substrate 25.
【００２９】本実施の形態の半導体装置３３およびその
接合構造においても、第１の実施の形態と同様の効果を
奏することができる。The same effects as in the first embodiment can be obtained also in the semiconductor device 33 of the present embodiment and its junction structure.
【００３０】さらに、本実施の形態の場合、半導体装置
３３下面の壁部３２の高さが半田ボール３０の高さより
高いため、半導体装置３３を搬送したり、取り扱う際
に、壁部３２によって半田ボール３０が保護され、半田
ボール３０に傷等が生じることがない。Further, in the case of the present embodiment, since the height of the wall portion 32 on the lower surface of the semiconductor device 33 is higher than the height of the solder ball 30, when the semiconductor device 33 is transported or handled, The balls 30 are protected, and the solder balls 30 are not damaged.
【００３１】なお、本発明の技術範囲は上記実施の形態
に限定されるものではなく、本発明の趣旨を逸脱しない
範囲において種々の変更を加えることが可能である。例
えば半田ボールの数や配置、半田ボールと壁部の高さの
具体的な値等に関しては適宜設計することができる。The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, the number and arrangement of the solder balls, the specific values of the heights of the solder balls and the wall, and the like can be appropriately designed.
【００３２】[0032]
【発明の効果】以上、詳細に説明したように、本発明の
半導体装置によれば、各半田ボールが壁部で隔離される
ため、隣接する半田ボール間でショート（ブリッジ）が
発生するのを防止することができる。また、間隙を設け
た複数の壁部を用いた場合、実装時の熱により発生する
ガスやフラックス洗浄液を間隙から逃がすことができ、
それらによる不具合が生じることがない。これにより、
従来に比べて実装作業の生産性向上、実装信頼性の向上
を図ることができる。As described above in detail, according to the semiconductor device of the present invention, since each solder ball is isolated by the wall, short-circuiting (bridge) between adjacent solder balls is prevented. Can be prevented. In addition, when using a plurality of walls provided with a gap, a gas or a flux cleaning liquid generated by heat during mounting can escape from the gap,
There is no problem caused by them. This allows
It is possible to improve the productivity of the mounting work and the reliability of the mounting as compared with the related art.
【００３３】また、本発明の半導体装置と基板の接合構
造によれば、半田ボールが溶解した時に壁部の先端が基
板に当接するため、半田ボールが溶解した状態で半田ボ
ールが壁部によって高さ方向には完全に隔離され、半田
ボールのショート発生をより確実に防止することができ
る。さらに、壁部が半導体装置と基板間の間隔を一定に
保持するスペーサの役目を果たし、半導体装置を基板上
に安定して固定することができる。Further, according to the bonding structure of the semiconductor device and the substrate of the present invention, when the solder ball is melted, the tip of the wall comes into contact with the substrate, so that the solder ball is raised by the wall in a state where the solder ball is melted. In the vertical direction, it is completely isolated, and the occurrence of short-circuit of the solder ball can be more reliably prevented. Further, the wall portion serves as a spacer for maintaining a constant distance between the semiconductor device and the substrate, and the semiconductor device can be stably fixed on the substrate.
【図１】 本発明の第１の実施の形態である半導体装置
と基板（実装側）を示す断面図である。FIG. 1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the present invention and a substrate (mounting side).
【図２】 同、半導体装置と基板を接合した状態を示す
断面図である。FIG. 2 is a cross-sectional view showing a state where the semiconductor device and the substrate are joined together.
【図３】 同、半導体装置の裏面図である。FIG. 3 is a rear view of the same semiconductor device.
【図４】 本発明の第２の実施の形態である半導体装置
と基板（実装側）を示す断面図である。FIG. 4 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the present invention and a substrate (mounting side).
【図５】 同、半導体装置と基板を接合した状態を示す
断面図である。FIG. 5 is a cross-sectional view showing a state where the semiconductor device and the substrate are joined together.
【図６】 従来の半導体装置と基板（実装側）を示す断
面図である。FIG. 6 is a cross-sectional view showing a conventional semiconductor device and a substrate (mounting side).
【図７】 同、半導体装置と基板を接合した状態を示す
断面図である。FIG. 7 is a cross-sectional view showing a state where the semiconductor device and the substrate are joined together.
【図８】 公知例１のプリント回路基板を示す平面図で
ある。FIG. 8 is a plan view showing a printed circuit board according to a known example 1.
【図９】 公知例２のフリップチップＩＣと基板を接合
した状態を示す断面図である。FIG. 9 is a cross-sectional view showing a state where the flip-chip IC according to the known example 2 and the substrate are joined.
【図１０】 公知例３のフリップチップＩＣと基板を接
合した状態を示す断面図である。FIG. 10 is a cross-sectional view showing a state in which a flip-chip IC according to a known example 3 and a substrate are joined.
２４，３３ 半導体装置 ２５ 基板（実装側） ２５ａ 溝 ２６ 基板（半導体装置側） ２７ 半導体素子 ２８ 金線 ２９ 樹脂 ３０ 半田ボール ３１，３２ 壁部 24, 33 Semiconductor device 25 Substrate (mounting side) 25a Groove 26 Substrate (semiconductor device side) 27 Semiconductor element 28 Gold wire 29 Resin 30 Solder ball 31, 32 Wall portion
Claims (6)
ボールが下面に配置されたボールグリッドアレイパッケ
ージを有する半導体装置において、 全ての隣接する半田ボールの間に絶縁性材料からなる壁
部が設けられたことを特徴とする半導体装置。In a semiconductor device having a ball grid array package in which a plurality of solder balls for bonding to an external substrate are arranged on a lower surface, a wall made of an insulating material is provided between all adjacent solder balls. A semiconductor device, which is provided.
数の壁部の間には間隙が設けられていることを特徴とす
る半導体装置。2. The semiconductor device according to claim 1, wherein said wall is composed of a plurality of divided walls, and a gap is provided between said plurality of walls. Semiconductor device.
ボールが下面に配置されたボールグリッドアレイパッケ
ージを有する半導体装置において、全ての隣接する半田
ボールの間に、絶縁性材料からなりその高さが前記半田
ボールの高さよりも低い壁部が設けられ、 前記半田ボールが溶解して外部の基板と接合された状態
で、前記壁部の先端が前記基板表面に当接していること
を特徴とする半導体装置と基板の接合構造。3. In a semiconductor device having a ball grid array package in which a plurality of solder balls for bonding to an external substrate are arranged on a lower surface, an insulating material is formed between all adjacent solder balls. A wall portion lower than the height of the solder ball is provided, and in a state where the solder ball is melted and joined to an external substrate, the tip of the wall portion is in contact with the surface of the substrate. Bonding structure of a semiconductor device and a substrate.
合構造において、 前記壁部が分割された複数の壁部で構成され、これら複
数の壁部の間には間隙が設けられていることを特徴とす
る半導体装置と基板の接合構造。4. The bonding structure of a semiconductor device and a substrate according to claim 3, wherein the wall is composed of a plurality of divided walls, and a gap is provided between the plurality of walls. A bonding structure of a semiconductor device and a substrate, characterized in that:
ボールが下面に配置されたボールグリッドアレイパッケ
ージを有する半導体装置において、全ての隣接する半田
ボールの間に、絶縁性材料からなりその高さが前記半田
ボールの高さよりも高い壁部が設けられ、 前記半田ボールが溶解して外部の基板と接合された状態
で、前記壁部の先端が前記基板に設けられた溝の内部に
挿入されていることを特徴とする半導体装置と基板の接
合構造。5. In a semiconductor device having a ball grid array package in which a plurality of solder balls for bonding to an external substrate are arranged on a lower surface, an insulating material is formed between all adjacent solder balls. A wall portion that is higher than the height of the solder ball is provided, and in a state where the solder ball is melted and joined to an external substrate, the tip of the wall portion is inserted into a groove provided in the substrate. A bonding structure of a semiconductor device and a substrate, wherein the bonding structure is performed.
合構造において、 前記壁部が分割された複数の壁部で構成され、これら複
数の壁部の間には間隙が設けられていることを特徴とす
る半導体装置と基板の接合構造。6. The bonding structure of a semiconductor device and a substrate according to claim 5, wherein the wall is composed of a plurality of divided walls, and a gap is provided between the plurality of walls. A bonding structure of a semiconductor device and a substrate, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34192096A JP2907168B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor device and bonding structure of semiconductor device and substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34192096A JP2907168B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor device and bonding structure of semiconductor device and substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10189806A true JPH10189806A (en) | 1998-07-21 |
| JP2907168B2 JP2907168B2 (en) | 1999-06-21 |
Family
ID=18349782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34192096A Expired - Fee Related JP2907168B2 (en) | 1996-12-20 | 1996-12-20 | Semiconductor device and bonding structure of semiconductor device and substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2907168B2 (en) |
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| JP2007324418A (en) * | 2006-06-01 | 2007-12-13 | Fujitsu Ltd | Semiconductor device, manufacturing method for solder bump connection board, and manufacturing method for semiconductor device |
| JP2008147811A (en) * | 2006-12-07 | 2008-06-26 | Ngk Insulators Ltd | Sealed electronic component |
| JP2009076569A (en) * | 2007-09-19 | 2009-04-09 | Nec Electronics Corp | Semiconductor package and mounting substrate, and semiconductor device including same |
| JP2009130362A (en) * | 2007-11-20 | 2009-06-11 | Fujitsu Ltd | Low-profile semiconductor assembly |
| JP2009212228A (en) * | 2008-03-03 | 2009-09-17 | Shinko Electric Ind Co Ltd | Wiring substrate and method of manufacturing the same |
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