JPH08181239A - Circuit board for mounting flip-chip - Google Patents
Circuit board for mounting flip-chipInfo
- Publication number
- JPH08181239A JPH08181239A JP31986194A JP31986194A JPH08181239A JP H08181239 A JPH08181239 A JP H08181239A JP 31986194 A JP31986194 A JP 31986194A JP 31986194 A JP31986194 A JP 31986194A JP H08181239 A JPH08181239 A JP H08181239A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- semiconductor
- resist
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置をフリップ
チップ実装する半導体実装用回路基板に関し、特にその
基板上に設けるレジストパターンに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor mounting circuit board on which a semiconductor device is flip-chip mounted, and more particularly to a resist pattern provided on the board.
【0002】[0002]
【従来の技術】近年、電子機器の小型化要求に伴い、回
路モジュールの高密度実装が望まれており、回路基板は
両面配線から多層配線化へ、能動素子も小型化へと進ん
でいる。更に半導体装置も従来のプラスチックモールド
品からベアチップ化へと進み、開発が盛んに行われてい
るが、最近特に半導体装置のベアチップ実装の一手法と
してフリップチップ実装が注目されてきている。2. Description of the Related Art In recent years, with the demand for miniaturization of electronic equipment, high-density mounting of circuit modules has been desired, and circuit boards are progressing from double-sided wiring to multi-layer wiring, and active elements are also downsized. Further, semiconductor devices have been actively developed from conventional plastic molded products to bare chips, and recently flip chip mounting has been attracting attention as a method of bare chip mounting of semiconductor devices.
【0003】以下、フリップチップ実装を行う従来の回
路基板について説明する。図4は従来の半導体実装用回
路基板の平面図であり、図5は図4に示す従来の半導体
実装用回路基板上に半導体素子をフリップチップ実装し
たときの図4のB−B線に沿う一部断面図である。図4
において、回路基板1の基板表面上には導体回路パター
ン2と半導体素子との接続用電極部3が形成されてお
り、これら導体回路パターン2と接続用電極部3とは電
気的に接続されている。更に、これらを覆うように接続
用電極部3のエリアを除く基板表面全面にレジスト4が
塗布されている。なお、5は半導体素子実装エリアを示
している。A conventional circuit board for flip-chip mounting will be described below. FIG. 4 is a plan view of a conventional semiconductor mounting circuit board, and FIG. 5 is taken along line BB of FIG. 4 when a semiconductor element is flip-chip mounted on the conventional semiconductor mounting circuit board shown in FIG. FIG. FIG.
In the above, the conductor circuit pattern 2 and the connecting electrode portion 3 for connecting the semiconductor element are formed on the substrate surface of the circuit board 1, and the conductor circuit pattern 2 and the connecting electrode portion 3 are electrically connected to each other. There is. Further, a resist 4 is applied on the entire surface of the substrate excluding the area of the connecting electrode portion 3 so as to cover them. In addition, 5 has shown the semiconductor element mounting area.
【0004】フリップチップ実装に際しては、図5に示
すように、半導体素子6のバンプ用電極7上に予めマス
クを使って印刷された半田バンプ8と、回路基板1上の
接続用電極部3との位置合わせをして、半導体素子6を
回路基板1上に載置する。その後、リフロー等による加
熱処理により半田バンプ8を溶融させて両者を接続し、
更に半導体素子6と回路基板1との隙間に層間封止樹脂
9を注入する。この状態で、一応実装されることになる
が、もし層間封止樹脂9が所定の場所に封止されていな
いと、温度サイクル試験において半導体素子6(通常、
LSIチップ)と回路基板1との熱膨張係数の差によ
り、そのフリップチップ実装された半導体素子6の接続
不良が起こる等、信頼性が大きく劣化するおそれがあ
る。これを防止するためには、前記層間封止樹脂9を密
に封入して熱膨張係数差を解消させるのが一般的であ
り、その方法として、層間封止樹脂9の注入は斜めに傾
けたホットプレート上で行い、層間封止樹脂9が半導体
素子6の周囲に滲出してくるまで待ってから、これをホ
ットプレートより下ろし静置させて層間封止樹脂9を硬
化することにより行われる。At the time of flip-chip mounting, as shown in FIG. 5, solder bumps 8 preliminarily printed using a mask on the bump electrodes 7 of the semiconductor element 6 and the connecting electrode portions 3 on the circuit board 1 are connected. Then, the semiconductor element 6 is placed on the circuit board 1. After that, the solder bumps 8 are melted by a heat treatment such as reflow to connect them,
Further, the interlayer sealing resin 9 is injected into the gap between the semiconductor element 6 and the circuit board 1. In this state, the semiconductor chip 6 (usually, normally) is mounted, but if the interlayer sealing resin 9 is not sealed in a predetermined place, the semiconductor element 6 (usually,
Due to the difference in coefficient of thermal expansion between the LSI chip) and the circuit board 1, the semiconductor element 6 mounted on the flip chip may have a bad connection, and the reliability may be significantly deteriorated. In order to prevent this, it is general that the interlayer sealing resin 9 is tightly sealed to eliminate the difference in thermal expansion coefficient. As a method, the injection of the interlayer sealing resin 9 is inclined. It is performed on a hot plate by waiting until the interlayer sealing resin 9 oozes out around the semiconductor element 6, then lowering it from the hot plate and allowing it to stand to cure the interlayer sealing resin 9.
【0005】[0005]
【発明が解決しようとする課題】しかしながら、上記の
従来の構成では、フリップチップ実装を行う際に、半田
バンプの半田を溶融させるため、接続前の半田バンプ径
が約150μmであるのと比べて、半導体素子6と回路基板
1との隙間が約80μm程度と狭くなっている。しかも、
回路基板1の表面層上の半導体素子6の下部の部位にも
約20μmのレジストが塗布されているため、結局のとこ
ろ、半導体素子6と回路基板1との隙間は約60μm程度
しか開いていない。そのため、半導体素子6と回路基板
1とを接続したのち層間封止樹脂9をその隙間に入れる
際には、層間封止樹脂9の気泡が絡む等の注入不良が生
じ、実装体の信頼性が著しく劣化するという問題があっ
た。However, in the above-described conventional configuration, when the flip-chip mounting is performed, the solder bump solder is melted, so that the solder bump diameter before connection is about 150 μm. The gap between the semiconductor element 6 and the circuit board 1 is as narrow as about 80 μm. Moreover,
Since the resist of about 20 μm is also applied to the lower part of the semiconductor element 6 on the surface layer of the circuit board 1, after all, the gap between the semiconductor element 6 and the circuit board 1 is only about 60 μm. . Therefore, when the semiconductor element 6 and the circuit board 1 are connected and then the interlayer sealing resin 9 is put into the gap, an injection failure such as air bubbles of the interlayer sealing resin 9 is entangled, and the reliability of the mounting body is reduced. There was a problem of remarkable deterioration.
【0006】本発明は上記従来の問題点を解決するもの
であり、樹脂注入不良のない回路基板を提供することを
目的とする。The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a circuit board free from defective resin injection.
【0007】[0007]
【課題を解決するための手段】上記課題を達成するため
に、本発明は、前記回路基板表面層上の半導体素子実装
エリアの略全域にわたり、レジストパターンを形成しな
い部分を設けたものである。In order to achieve the above object, the present invention provides a portion where a resist pattern is not formed over substantially the entire semiconductor element mounting area on the surface layer of the circuit board.
【0008】[0008]
【作用】上記構成によれば、半導体素子と回路基板とを
接続したのち、層間封止樹脂をその隙間に注入する際に
は、半導体素子と回路基板との隙間がレジストがない分
だけ広いため、封止用の層間封止樹脂が入りやすくな
り、また隙間が広い分、注入速度も速くなり作業性も向
上する。According to the above structure, when the interlayer sealing resin is injected into the gap after connecting the semiconductor element and the circuit board, the gap between the semiconductor element and the circuit board is wide because there is no resist. In addition, the interlayer sealing resin for sealing becomes easy to enter, and since the gap is wide, the injection speed is increased and the workability is improved.
【0009】[0009]
【実施例】以下、本発明の回路基板を用いたフリップチ
ップ実装の第1実施例について図面を参照しながら説明
する。図1は本発明の半導体実装用回路基板の平面図を
示すものであり、図2は本発明の半導体実装用回路基板
上に半導体素子をフリップチップ実装したときの図1の
A−A線に沿う一部断面図である。なお、前記従来の半
導体実装用回路基板と同一の部分は同一の符号を付すも
のとする。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of flip-chip mounting using the circuit board of the present invention will be described below with reference to the drawings. 1 is a plan view of a semiconductor mounting circuit board of the present invention, and FIG. 2 is a line AA of FIG. 1 when a semiconductor element is flip-chip mounted on the semiconductor mounting circuit board of the present invention. FIG. The same parts as those of the conventional semiconductor mounting circuit board are designated by the same reference numerals.
【0010】図1及び図2において、アルミナを主成分
とした回路基板1の基板表面上には、導体回路パターン
2と半導体素子6との接続用電極部3が形成されてお
り、これら導体回路パターン2と接続用電極部3とは電
気的に接続されている。また、回路基板1の基板表面上
にはレジスト4がスクリーン印刷にて印刷され、膜厚約
20μm程度の厚みで硬化している。従来の基板では接続
用電極部3のみを露出させて他の部分すべてにレジスト
4を塗布していたが、本発明では図1に示すように、回
路基板1の表面層上の半導体素子実装エリア5の略全域
にはレジスト4を塗布していないのが特徴である。In FIGS. 1 and 2, an electrode portion 3 for connecting the conductor circuit pattern 2 and the semiconductor element 6 is formed on the substrate surface of the circuit board 1 containing alumina as a main component. The pattern 2 and the connecting electrode portion 3 are electrically connected. Also, a resist 4 is printed on the surface of the circuit board 1 by screen printing to reduce the film thickness.
Hardened to a thickness of about 20 μm. In the conventional substrate, only the connecting electrode portion 3 is exposed and the resist 4 is applied to all other portions, but in the present invention, as shown in FIG. 1, the semiconductor element mounting area on the surface layer of the circuit board 1 is mounted. The feature is that the resist 4 is not applied to substantially the entire area of 5.
【0011】以上のように構成された回路基板1に対し
フリップチップ実装の工程を説明する。半導体素子6の
バンプ用電極7上に予めマスクを使って印刷された半田
バンプ8と、回路基板1上の接続用電極部3との位置合
わせをして、半導体素子6を回路基板上に載置する。そ
の後、半田バンプ8と接続用電極部3を当接させたまま
リフロー炉に通すと、半田バンプ8が溶融することによ
って半導体素子6と接続用電極部3とが接続される。こ
のとき、接続前の半田バンプ径が約150μmであったのと
比べて、半田バンプ8の半田が溶融し広がるため、半導
体素子6と回路基板1との隙間は約80μm程度になって
いる。次に、信頼性向上のため、斜めに傾けたホットプ
レート上で回路基板1と半導体素子6との隙間に層間封
止樹脂9を注入する。本実施例においては、半導体素子
6と回路基板1の表面との隙間にレジスト4がないの
で、その膜厚である約20μm程度の分だけ従来の基板よ
りも広いため層間封止樹脂9の注入が行い易く、樹脂注
入不良のない回路基板を作成することができる。しか
も、層間封止樹脂9が容易に注入されていくため、作業
効率も大幅に向上する。こうして層間封止樹脂9が半導
体素子6の周囲に滲出してくるまで待ってから、これを
ホットプレートから下ろし静置させて層間封止樹脂9を
硬化させることにより行われる。A process of flip-chip mounting on the circuit board 1 configured as described above will be described. The solder bumps 8 printed in advance on the bump electrodes 7 of the semiconductor element 6 using a mask are aligned with the connection electrode portions 3 on the circuit board 1, and the semiconductor element 6 is mounted on the circuit board. Place. Then, when the solder bumps 8 and the connecting electrode portions 3 are brought into contact with each other and passed through a reflow furnace, the semiconductor elements 6 and the connecting electrode portions 3 are connected by melting the solder bumps 8. At this time, compared with the diameter of the solder bump before connection being about 150 μm, the solder of the solder bump 8 melts and spreads, so that the gap between the semiconductor element 6 and the circuit board 1 is about 80 μm. Next, in order to improve reliability, the interlayer sealing resin 9 is injected into the gap between the circuit board 1 and the semiconductor element 6 on a hot plate that is inclined. In this embodiment, since there is no resist 4 in the gap between the semiconductor element 6 and the surface of the circuit board 1, the film thickness is about 20 μm, which is wider than that of the conventional board. It is easy to perform, and a circuit board without resin injection defects can be produced. Moreover, since the interlayer sealing resin 9 is easily injected, the work efficiency is significantly improved. In this way, after waiting for the interlayer sealing resin 9 to seep around the semiconductor element 6, the interlayer sealing resin 9 is cured by lowering it from the hot plate and allowing it to stand.
【0012】次に、本発明の第2実施例について図3を
参照しながら説明する。なお、前記第1実施例と同一の
部分は同一の符号を付すものとする。図3において、1
は回路基板、2は導体回路パターン、3は半導体素子と
の接続用電極部、4はレジストである。図1の第1実施
例の構成と異なるのは、接続用電極部3のチップ内部側
に200μm程度の幅のレジスト4によりレジストダム10を
形成させている点である。このレジストダム10は図示の
ように隣接する四隅の部分には形成されていない。この
回路基板1を使ってフリップチップ実装する際には、溶
融した半田バンプ8の半田は、接続用電極部3のチップ
内部側外周部にレジストダム10が形成されていることに
より一定面積以上広がらず、半田広がりによる半導体素
子6の沈下を防ぐことができるため、半導体素子6と回
路基板1との隙間が狭まる割合を小さくすることができ
る。しかも、このレジストダム10は前記のように隣接す
る四隅の部分には形成されず、ここに隙間があるため、
層間封止樹脂9の注入をこの隙間の部分より行うことが
でき、ここにはレジスト4がないので層間封止樹脂9は
容易に注入され、作業効率も大幅に向上する。Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment are designated by the same reference numerals. In FIG. 3, 1
Is a circuit board, 2 is a conductor circuit pattern, 3 is an electrode portion for connecting to a semiconductor element, and 4 is a resist. The difference from the configuration of the first embodiment of FIG. 1 is that a resist dam 10 is formed on the inside of the chip of the connecting electrode portion 3 by a resist 4 having a width of about 200 μm. The resist dam 10 is not formed at the four corners adjacent to each other as shown in the figure. When flip-chip mounting is performed using this circuit board 1, the melted solder of the solder bumps 8 spreads over a certain area because the resist dam 10 is formed on the outer peripheral portion of the connecting electrode portion 3 on the chip inner side. In addition, since it is possible to prevent the semiconductor element 6 from sinking due to the spread of solder, it is possible to reduce the rate of narrowing the gap between the semiconductor element 6 and the circuit board 1. Moreover, since the resist dam 10 is not formed at the four corners adjacent to each other as described above, there is a gap here,
The interlayer sealing resin 9 can be injected from this gap portion, and since there is no resist 4 there, the interlayer sealing resin 9 is easily injected and the working efficiency is greatly improved.
【0013】[0013]
【発明の効果】以上のように、本発明の回路基板は、回
路基板表面層上の半導体素子実装エリアの略全域にレジ
ストを塗布しない部分を設けることにより、半導体素子
と回路基板との隙間が広がり、層間封止樹脂注入不良の
ない回路基板を作成することができる。しかも、半導体
素子と回路基板の隙間が広い分だけ層間封止樹脂の注入
速度も速くなり作業性も向上する。As described above, in the circuit board of the present invention, the gap between the semiconductor element and the circuit board is eliminated by providing the portion not coated with the resist on almost the entire area of the semiconductor element mounting area on the surface layer of the circuit board. It is possible to create a circuit board that does not spread and have a defective injection of the interlayer sealing resin. Moreover, since the gap between the semiconductor element and the circuit board is wide, the injection speed of the interlayer sealing resin is increased and the workability is improved.
【図1】本発明の第1実施例における半導体実装用回路
基板の平面図である。FIG. 1 is a plan view of a semiconductor mounting circuit board according to a first embodiment of the present invention.
【図2】本発明の実施例における半導体実装用回路基板
に半導体素子をフリップチップ実装したときの図1のA
−A線に沿う一部断面図である。FIG. 2A of FIG. 1 when a semiconductor element is flip-chip mounted on a semiconductor mounting circuit board according to an embodiment of the present invention.
FIG. 6 is a partial cross-sectional view taken along the line A.
【図3】本発明の第2実施例における半導体実装用回路
基板の平面図である。FIG. 3 is a plan view of a semiconductor mounting circuit board according to a second embodiment of the present invention.
【図4】従来の半導体実装用回路基板の平面図である。FIG. 4 is a plan view of a conventional semiconductor mounting circuit board.
【図5】従来の半導体実装用回路基板に半導体素子をフ
リップチップ実装したときの図4のB−B線に沿う一部
断面図である。5 is a partial cross-sectional view taken along line BB of FIG. 4 when a semiconductor element is flip-chip mounted on a conventional semiconductor mounting circuit board.
1…回路基板、 2…導体回路パターン、 3…接続用
電極部、 4…レジスト、 5…半導体素子実装エリ
ア、 6…半導体素子、 7…バンプ用電極、 8…半
田バンプ、 9…層間封止樹脂、 10…レジストダム。DESCRIPTION OF SYMBOLS 1 ... Circuit board, 2 ... Conductor circuit pattern, 3 ... Connection electrode part, 4 ... Resist, 5 ... Semiconductor element mounting area, 6 ... Semiconductor element, 7 ... Bump electrode, 8 ... Solder bump, 9 ... Interlayer sealing Resin, 10 ... Resist dam.
Claims (1)
表面層上の半導体素子実装エリアに半導体素子をフリッ
プチップ実装するフリップチップ実装用回路基板におい
て、前記半導体素子実装エリアの略全域にわたり、レジ
ストパターンを形成しない部分を設けたことを特徴とす
るフリップチップ実装用回路基板。1. A flip-chip mounting circuit board for flip-chip mounting a semiconductor element in a semiconductor element mounting area on a surface layer of a circuit board on which a conductor circuit pattern is wired, wherein a resist pattern is formed over substantially the entire area of the semiconductor element mounting area. A circuit board for flip-chip mounting, characterized in that a portion not formed with is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31986194A JPH08181239A (en) | 1994-12-22 | 1994-12-22 | Circuit board for mounting flip-chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31986194A JPH08181239A (en) | 1994-12-22 | 1994-12-22 | Circuit board for mounting flip-chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH08181239A true JPH08181239A (en) | 1996-07-12 |
Family
ID=18115058
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31986194A Pending JPH08181239A (en) | 1994-12-22 | 1994-12-22 | Circuit board for mounting flip-chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH08181239A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920126A (en) * | 1997-10-02 | 1999-07-06 | Fujitsu Limited | Semiconductor device including a flip-chip substrate |
US6049122A (en) * | 1997-10-16 | 2000-04-11 | Fujitsu Limited | Flip chip mounting substrate with resin filled between substrate and semiconductor chip |
JP2006253315A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus |
JP2007103733A (en) * | 2005-10-05 | 2007-04-19 | Nec Electronics Corp | Substrate and semiconductor device using the same |
-
1994
- 1994-12-22 JP JP31986194A patent/JPH08181239A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5920126A (en) * | 1997-10-02 | 1999-07-06 | Fujitsu Limited | Semiconductor device including a flip-chip substrate |
US6049122A (en) * | 1997-10-16 | 2000-04-11 | Fujitsu Limited | Flip chip mounting substrate with resin filled between substrate and semiconductor chip |
JP2006253315A (en) * | 2005-03-09 | 2006-09-21 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus |
JP2007103733A (en) * | 2005-10-05 | 2007-04-19 | Nec Electronics Corp | Substrate and semiconductor device using the same |
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