JPH10107613A5 - - Google Patents

Info

Publication number
JPH10107613A5
JPH10107613A5 JP1997196106A JP19610697A JPH10107613A5 JP H10107613 A5 JPH10107613 A5 JP H10107613A5 JP 1997196106 A JP1997196106 A JP 1997196106A JP 19610697 A JP19610697 A JP 19610697A JP H10107613 A5 JPH10107613 A5 JP H10107613A5
Authority
JP
Japan
Prior art keywords
threshold voltage
voltage transistor
transistor
high threshold
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997196106A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10107613A (ja
JP3894622B2 (ja
Filing date
Publication date
Priority claimed from US08/687,800 external-priority patent/US5831451A/en
Application filed filed Critical
Publication of JPH10107613A publication Critical patent/JPH10107613A/ja
Publication of JPH10107613A5 publication Critical patent/JPH10107613A5/ja
Application granted granted Critical
Publication of JP3894622B2 publication Critical patent/JP3894622B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

JP19610697A 1996-07-19 1997-07-22 異なるしきい値電圧を持つトランジスタを用いたダイナミック論理回路 Expired - Lifetime JP3894622B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/687,800 US5831451A (en) 1996-07-19 1996-07-19 Dynamic logic circuits using transistors having differing threshold voltages
US687800 1996-07-19

Publications (3)

Publication Number Publication Date
JPH10107613A JPH10107613A (ja) 1998-04-24
JPH10107613A5 true JPH10107613A5 (enExample) 2005-05-26
JP3894622B2 JP3894622B2 (ja) 2007-03-22

Family

ID=24761899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19610697A Expired - Lifetime JP3894622B2 (ja) 1996-07-19 1997-07-22 異なるしきい値電圧を持つトランジスタを用いたダイナミック論理回路

Country Status (6)

Country Link
US (1) US5831451A (enExample)
EP (1) EP0820147B1 (enExample)
JP (1) JP3894622B2 (enExample)
KR (1) KR100484460B1 (enExample)
AT (1) ATE279046T1 (enExample)
DE (1) DE69731035T2 (enExample)

Families Citing this family (41)

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JP3451579B2 (ja) * 1997-03-03 2003-09-29 日本電信電話株式会社 自己同期型パイプラインデータパス回路
US5910735A (en) * 1997-05-22 1999-06-08 International Business Machines Corporation Method and apparatus for safe mode in dynamic logic using dram cell
US6049231A (en) * 1997-07-21 2000-04-11 Texas Instruments Incorporated Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output
US6021087A (en) * 1997-09-25 2000-02-01 Texas Instruments Incorporated Dynamic logic memory addressing circuits, systems, and methods with decoder fan out greater than 2:1
US5982702A (en) * 1997-09-25 1999-11-09 Texas Instruments Incorporated Dynamic logic memory addressing circuits, systems, and methods with predecoders providing data and precharge control to decoders
US6009037A (en) * 1997-09-25 1999-12-28 Texas Instruments Incorporated Dynamic logic memory addressing circuits, systems, and methods with reduced capacitively loaded predecoders
JP3299151B2 (ja) * 1997-11-05 2002-07-08 日本電気株式会社 バス入出力回路及びそれを用いたバス入出力システム
US6090153A (en) * 1997-12-05 2000-07-18 International Business Machines Corporation Multi-threshold-voltage differential cascode voltage switch (DCVS) circuits
US6269461B1 (en) * 1998-04-27 2001-07-31 International Business Machines Corporation Testing method for dynamic logic keeper device
US6188247B1 (en) * 1999-01-29 2001-02-13 International Business Machines Corporation Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
US6266800B1 (en) * 1999-01-29 2001-07-24 International Business Machines Corporation System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination
US6278157B1 (en) 1999-01-29 2001-08-21 International Business Machines Corporation Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
US6365934B1 (en) 1999-01-29 2002-04-02 International Business Machines Corporation Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits
EP1028434A1 (en) * 1999-02-11 2000-08-16 Infineon Technologies North America Corp. Dynamic logic circuit
US6262615B1 (en) 1999-02-25 2001-07-17 Infineon Technologies Ag Dynamic logic circuit
US6242952B1 (en) * 1999-09-24 2001-06-05 Texas Instruments Incorporated Inverting hold time latch circuits, systems, and methods
US6344759B1 (en) * 1999-10-18 2002-02-05 Texas Instruments Incorporated Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation
US6552573B1 (en) * 2000-01-10 2003-04-22 Texas Instruments Incorporated System and method for reducing leakage current in dynamic circuits with low threshold voltage transistors
US6466057B1 (en) * 2000-01-21 2002-10-15 Hewlett-Packard Company Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method
US6433587B1 (en) 2000-03-17 2002-08-13 International Business Machines Corporation SOI CMOS dynamic circuits having threshold voltage control
US7149674B1 (en) * 2000-05-30 2006-12-12 Freescale Semiconductor, Inc. Methods for analyzing integrated circuits and apparatus therefor
US6369606B1 (en) * 2000-09-27 2002-04-09 International Business Machines Corporation Mixed threshold voltage CMOS logic device and method of manufacture therefor
US6462582B1 (en) * 2001-06-12 2002-10-08 Micron Technology, Inc. Clocked pass transistor and complementary pass transistor logic circuits
US6668357B2 (en) * 2001-06-29 2003-12-23 Fujitsu Limited Cold clock power reduction
US6621305B2 (en) * 2001-08-03 2003-09-16 Hewlett-Packard Development Company, L.P. Partial swing low power CMOS logic circuits
US6842046B2 (en) 2002-01-31 2005-01-11 Fujitsu Limited Low-to-high voltage conversion method and system
US6933744B2 (en) * 2002-06-11 2005-08-23 The Regents Of The University Of Michigan Low-leakage integrated circuits and dynamic logic circuits
US6774683B2 (en) * 2002-08-13 2004-08-10 Analog Devices, Inc. Control loop for minimal tailnode excursion of differential switches
US6708312B1 (en) * 2002-08-22 2004-03-16 Silicon Integrated Systems Corp. Method for multi-threshold voltage CMOS process optimization
JP4052923B2 (ja) * 2002-10-25 2008-02-27 株式会社ルネサステクノロジ 半導体装置
US6819152B1 (en) * 2003-07-30 2004-11-16 National Semiconductor Corporation Circuitry for reducing leakage currents in a pre-charge circuit using very small MOSFET devices
JP4606810B2 (ja) * 2003-08-20 2011-01-05 パナソニック株式会社 半導体集積回路
US8247840B2 (en) * 2004-07-07 2012-08-21 Semi Solutions, Llc Apparatus and method for improved leakage current of silicon on insulator transistors using a forward biased diode
US7898297B2 (en) * 2005-01-04 2011-03-01 Semi Solution, Llc Method and apparatus for dynamic threshold voltage control of MOS transistors in dynamic logic circuits
US7265589B2 (en) * 2005-06-28 2007-09-04 International Business Machines Corporation Independent gate control logic circuitry
JP4967264B2 (ja) * 2005-07-11 2012-07-04 株式会社日立製作所 半導体装置
US7863689B2 (en) * 2006-09-19 2011-01-04 Semi Solutions, Llc. Apparatus for using a well current source to effect a dynamic threshold voltage of a MOS transistor
KR100951102B1 (ko) 2008-01-24 2010-04-07 명지대학교 산학협력단 Ｍｔｃｍｏｓ 회로를 구비한 동적 논리 회로 및 동적 논리회로의 인버터
CN102098041A (zh) * 2010-12-06 2011-06-15 北京邮电大学 一种线性系统可重构逻辑门电路
JP6474280B2 (ja) * 2014-03-05 2019-02-27 株式会社半導体エネルギー研究所 半導体装置
TWI888172B (zh) * 2024-06-14 2025-06-21 世界先進積體電路股份有限公司 邏輯電路

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US4107548A (en) * 1976-03-05 1978-08-15 Hitachi, Ltd. Ratioless type MIS logic circuit
JPS5587471A (en) * 1978-12-26 1980-07-02 Fujitsu Ltd Mos dynamic circuit
US4430583A (en) * 1981-10-30 1984-02-07 Bell Telephone Laboratories, Incorporated Apparatus for increasing the speed of a circuit having a string of IGFETs
US5459693A (en) * 1990-06-14 1995-10-17 Creative Integrated Systems, Inc. Very large scale integrated planar read only memory
US5247212A (en) * 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family
JP3110129B2 (ja) * 1992-03-03 2000-11-20 日本電気株式会社 Ｃｍｏｓインバータ回路
US5408144A (en) * 1993-01-07 1995-04-18 Hitachi, Ltd. Semiconductor integrated circuits with power reduction mechanism
JPH06208790A (ja) * 1993-01-12 1994-07-26 Toshiba Corp 半導体装置
US5440243A (en) * 1993-09-21 1995-08-08 Apple Computer, Inc. Apparatus and method for allowing a dynamic logic gate to operation statically using subthreshold conduction precharging
US5483181A (en) * 1994-12-16 1996-01-09 Sun Microsystems, Inc. Dynamic logic circuit with reduced charge leakage
US5602497A (en) * 1995-12-20 1997-02-11 Thomas; Steven D. Precharged adiabatic pipelined logic

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