JPH0997790A - Forming method of oxide film and semiconductor device provided therewith - Google Patents

Forming method of oxide film and semiconductor device provided therewith

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Publication number
JPH0997790A
JPH0997790A JP25387695A JP25387695A JPH0997790A JP H0997790 A JPH0997790 A JP H0997790A JP 25387695 A JP25387695 A JP 25387695A JP 25387695 A JP25387695 A JP 25387695A JP H0997790 A JPH0997790 A JP H0997790A
Authority
JP
Japan
Prior art keywords
oxide film
stripe
groove
present
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP25387695A
Other languages
Japanese (ja)
Other versions
JP3162970B2 (en
Inventor
Junichiro Tojo
潤一郎 東條
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP25387695A priority Critical patent/JP3162970B2/en
Publication of JPH0997790A publication Critical patent/JPH0997790A/en
Application granted granted Critical
Publication of JP3162970B2 publication Critical patent/JP3162970B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]

Abstract

PROBLEM TO BE SOLVED: To provide a method of forming an oxide film thicker than one formed through LOCOS method without increasing crystal defects and the like in it and to lessen a semiconductor device further in stray capacitance by the use of the above oxide film. SOLUTION: An oxide film and a nitride film are deposited on a semiconductor substrate 11, an opening is provided in the oxide film and the nitride film, and a stripe-like deep groove is provided by etching the substrate 11 through the opening, the side face of the groove is oxidized, whereby a stripe-like part of the substrate is oxidized to from an oxide film 18 as thick as the depth of the groove. This semiconductor device is equipped with the thick oxide film 18 on the underside of a bonding pad 16.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は酸化膜の形成方法及
びその酸化膜を用いた半導体装置に係り、特に超高周波
トランジスタ等における電極配線の浮遊容量を低減する
のに好適な厚い酸化膜の形成方法、及びその酸化膜を利
用した半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an oxide film and a semiconductor device using the oxide film, and particularly to forming a thick oxide film suitable for reducing stray capacitance of electrode wiring in a super high frequency transistor or the like. The present invention relates to a method and a semiconductor device using the oxide film.

【0002】[0002]

【従来の技術】高周波トランジスタ、特にギガヘルツ帯
以上で動作する超高周波トランジスタにおいては、PG
(POWER GAIN)特性等の高周波特性の向上のため、電極
配線の浮遊容量の低減が要請されている。特にボンディ
ングパッドの電極直下は、面積が大きいため、その容量
を低減する必要がある。このため、超高周波トランジス
タ等においては、LOCOS法又はシャローエッチング
LOCOS法等で、ボンディングパッド直下の酸化膜の
膜厚を厚くして、浮遊容量を低減している。更に、多層
電極配線構造を採用し、浮遊容量の大きい第一層電極部
分の面積を小さくし、浮遊容量の比較的少ない第二層電
極部分の面積を大きくして対応している。
2. Description of the Related Art In high frequency transistors, especially ultra high frequency transistors operating above the GHz band, PG
In order to improve high frequency characteristics such as (POWER GAIN) characteristics, it is required to reduce the stray capacitance of electrode wiring. In particular, since the area directly under the electrode of the bonding pad is large, it is necessary to reduce the capacitance. Therefore, in the ultra-high frequency transistor and the like, the floating capacitance is reduced by increasing the film thickness of the oxide film immediately below the bonding pad by the LOCOS method or the shallow etching LOCOS method. Further, a multi-layer electrode wiring structure is adopted to reduce the area of the first layer electrode portion having a large stray capacitance and to enlarge the area of the second layer electrode portion having a relatively small stray capacitance.

【0003】しかしながら、LOCOS法で厚い酸化膜
を形成する場合に、バーズビーグ増による欠陥の増大
や、高温で長時間の酸化時間に伴う欠陥の増大という問
題があり、又酸化膜を厚くすることにより段差が増える
という問題がある。これ等の問題点を考慮すると、超高
周波トランジスタに現状で用いることができる酸化膜の
膜厚は12,000Å程度が限界であった。
However, when a thick oxide film is formed by the LOCOS method, there are problems that defects increase due to increase in bird's beag and defects due to long oxidation time at high temperature, and that thick oxide film causes problems. There is a problem that the steps increase. Considering these problems, the film thickness of the oxide film that can be used in the present invention for the ultra-high frequency transistor is limited to about 12,000Å.

【0004】又、シャローエッチングLOCOS法を用
いても、段差の低減は図れるものの、膜厚としては、バ
ーズビーグ増による欠陥の増大或いは酸化時間の増大に
伴う欠陥の増大により、同様に膜厚としては12,00
0Å程度が限界であった。又、多層電極配線構造を用い
ると、工程数が増加し、又、層間絶縁膜の緻密性という
点では、窒化膜の使用が望ましいが、窒化膜は誘電率が
高いので、同じ膜厚の酸化膜に比べ浮遊容量が大きく、
膜厚を厚くする必要がある。
Even if the shallow etching LOCOS method is used, the step difference can be reduced, but the film thickness is similarly increased due to the increase of defects due to the increase of bird's beag or the increase of defects due to the increase of oxidation time. 12,000
The limit was about 0Å. Further, when the multilayer electrode wiring structure is used, the number of steps is increased, and it is preferable to use the nitride film in terms of the denseness of the interlayer insulating film. However, since the nitride film has a high dielectric constant, the same thickness of oxide film is used. The stray capacitance is larger than the membrane,
It is necessary to increase the film thickness.

【0005】[0005]

【発明が解決しようとする課題】本発明は上述した事情
に鑑みて為されたもので、従来のLOCOS法以上の厚
い酸化膜を結晶欠陥等を増大することなく形成する酸化
膜の形成方法、及びその酸化膜を用いることにより、浮
遊容量を更に低減した半導体装置を提供することを目的
とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and is a method for forming an oxide film, which is thicker than the conventional LOCOS method without increasing crystal defects and the like. Another object of the present invention is to provide a semiconductor device in which stray capacitance is further reduced by using the oxide film.

【0006】[0006]

【課題を解決するための手段】本発明の酸化膜の形成方
法は、半導体基板上に酸化膜と窒化膜とを被着し、該酸
化膜と窒化膜に開口を設け、該開口より前記基板をエッ
チングすることによりストライプ状の深い溝を形成し、
該深い溝の側表面を酸化することにより、前記ストライ
プ状の基板部分を酸化して、前記溝の深さに相当する厚
みの酸化膜を形成することを特徴とする。
According to the method for forming an oxide film of the present invention, an oxide film and a nitride film are deposited on a semiconductor substrate, an opening is provided in the oxide film and the nitride film, and the substrate is opened from the opening. To form deep stripe-shaped grooves by etching
By oxidizing the side surface of the deep groove, the stripe-shaped substrate portion is oxidized to form an oxide film having a thickness corresponding to the depth of the groove.

【0007】又、本発明の半導体装置は上述した形成方
法による酸化膜を、少なくともボンディングパッドの下
面に備えたことを特徴とする。
Further, the semiconductor device of the present invention is characterized in that the oxide film formed by the above-mentioned forming method is provided at least on the lower surface of the bonding pad.

【0008】[0008]

【発明の実施の形態】上述した本発明の酸化膜の形成方
法によれば、シリコン基板にストライプ状の深い溝を形
成し、その深い溝の側表面を酸化することによりストラ
イプ部分を両側からストライプ全体を酸化することがで
きると共に、ストライプの側表面から成長する酸化膜に
より溝部分を完全に酸化膜で埋めることができる。これ
により、通常のLOCOS法による酸化条件で、ストラ
イプ溝の深さに相当する厚さの酸化膜を形成でき、通常
のLOCOS法による場合と比較して2〜3倍程度、膜
厚の厚い酸化膜を形成することができる。
According to the above-described method for forming an oxide film of the present invention, a stripe-shaped deep groove is formed in a silicon substrate, and the side surface of the deep groove is oxidized to stripe the stripe portion from both sides. It is possible to oxidize the entire structure, and the groove portion can be completely filled with the oxide film by the oxide film growing from the side surface of the stripe. As a result, an oxide film having a thickness corresponding to the depth of the stripe groove can be formed under the oxidation condition by the normal LOCOS method, and the oxide film having a thickness that is about 2-3 times thicker than that by the normal LOCOS method can be formed. A film can be formed.

【0009】又、係る厚い酸化膜を備えた半導体装置
は、少なくともボンディングパッドの下面に2〜3μm
程度の厚い酸化膜を備えることにより、電極配線部分の
浮遊容量を大幅に低減することができる。これにより高
周波特性を大幅に改善することができる。
A semiconductor device having such a thick oxide film has a thickness of at least 2-3 μm on the lower surface of the bonding pad.
By providing a thick oxide film, the stray capacitance in the electrode wiring portion can be significantly reduced. As a result, high frequency characteristics can be significantly improved.

【0010】[0010]

【実施例】以下、本発明の一実施例について添付図面を
参照しながら説明する。尚、各図中同一符号は、同一又
は相当部分を示す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. The same reference numerals in the drawings indicate the same or corresponding parts.

【0011】図1は、本発明の一実施例の超高周波トラ
ンジスタのパターン図を示す。図2は、図1に示す超高
周波トランジスタの部分断面構造を示す。半導体チップ
11上には、エミッタ領域13及びベース領域12から
なるアクティブ領域を備え、エミッタ領域13には配線
電極14が接続され、ベース領域12には配線電極15
が接続されている。それぞれの配線電極は、ボンディン
グパッド16,17に連通し、図示しないボンディング
ワイヤにより半導体パッケージのリード端子に接続され
る。ボンディングパッド16,17の下面には、LOC
OS法で形成されたフィールド酸化膜20よりも厚い、
以下に詳述する酸化膜18,19を備えている。
FIG. 1 is a pattern diagram of an ultra high frequency transistor according to an embodiment of the present invention. FIG. 2 shows a partial cross-sectional structure of the ultra high frequency transistor shown in FIG. An active region including an emitter region 13 and a base region 12 is provided on the semiconductor chip 11, a wiring electrode 14 is connected to the emitter region 13, and a wiring electrode 15 is provided in the base region 12.
Is connected. Each wiring electrode communicates with the bonding pads 16 and 17, and is connected to the lead terminal of the semiconductor package by a bonding wire (not shown). LOC is provided on the lower surfaces of the bonding pads 16 and 17.
Thicker than the field oxide film 20 formed by the OS method,
It is provided with oxide films 18 and 19 described in detail below.

【0012】この厚い酸化膜18、19は、シリコン半
導体基板上に極めて薄い酸化膜と窒化膜とを被着し、そ
の酸化膜と窒化膜とに開口を設け、その開口より基板を
エッチングすることによりストライプの深い溝を形成
し、深い溝の側表面を酸化することにより形成した厚い
酸化膜領域である。従って、この厚い酸化膜領域18、
19は、溝の深さに相当する厚さの酸化膜であり、結晶
欠陥や熱歪みを半導体基板中に発生することなくLOC
OS法で形成されたフィールド酸化膜20よりも厚い絶
縁膜領域が得られる。特にボンディングパッド下面の浮
遊容量を大幅に低減することができる。
The thick oxide films 18 and 19 are formed by depositing an extremely thin oxide film and a nitride film on a silicon semiconductor substrate, forming openings in the oxide film and the nitride film, and etching the substrate through the openings. Is a thick oxide film region formed by forming a deep groove of the stripe and oxidizing the side surface of the deep groove. Therefore, this thick oxide film region 18,
Reference numeral 19 is an oxide film having a thickness corresponding to the depth of the groove, and the LOC is formed without generating crystal defects or thermal strain in the semiconductor substrate.
An insulating film region thicker than the field oxide film 20 formed by the OS method can be obtained. In particular, the stray capacitance on the lower surface of the bonding pad can be significantly reduced.

【0013】図3乃至6は、シリコン半導体基板をエッ
チングすることにより形成した、各種のストライプ状の
深い溝のパターンを示す。符号21は、シリコンの基板
がエッチングされずに残ったストライプ部分を示し、符
号22はシリコン基板がエッチングにより除去された溝
部分を示す。本実施例では、ストライプ部分21とエッ
チングされた溝部分22の幅はそれぞれ約1μ程度であ
り、溝の深さは2μ程度である。厳密には、酸化膜はシ
リコン基板内方に向かって成長する割合と、シリコン基
板外方に向かって成長する割合との比が、 0.9/1.1 である。このため、溝部分の幅Sとストライプ部分の幅
Lとの比を L/S=0.9μm/1.1μm とすることにより、ストライプ部分が両側から丁度酸化
されたときに、ストライプ間の溝部分が外方に成長する
酸化膜で丁度埋められる。
3 to 6 show various stripe-shaped deep groove patterns formed by etching a silicon semiconductor substrate. Reference numeral 21 indicates a stripe portion that remains without etching the silicon substrate, and reference numeral 22 indicates a groove portion where the silicon substrate is removed by etching. In the present embodiment, the width of each of the stripe portion 21 and the etched groove portion 22 is about 1 μm, and the groove depth is about 2 μm. Strictly speaking, the ratio of the growth rate of the oxide film toward the inside of the silicon substrate to the growth rate of the outside toward the silicon substrate is 0.9 / 1.1. Therefore, by setting the ratio of the width S of the groove portion to the width L of the stripe portion to L / S = 0.9 μm / 1.1 μm, when the stripe portion is just oxidized from both sides, The part is just filled with an oxide film that grows outward.

【0014】図3は、ストライプパターンを円環(リン
グ)状に形成したものである。ボンディングパッドの下
面の全体の領域をこのような円環状の幅約1μの溝を形
成し、その後溝側表面を酸化することによりストライプ
を形成した領域の全体全面を厚い酸化膜領域とすること
ができる。図4は同様にストライプパターンを角帯状に
形成した場合である。図5は、ストライプのパターンを
細帯状に形成した場合である。図7はストライプパター
ンをセル・メッシュ状に形成した場合である。尚、スト
ライプのパターンは、ストライプ部分がその両側から丁
度酸化されたときに、丁度溝が酸化膜で埋まるような、
寸法比であればよいので、図3及び図6に示す以外に
も、種々の変形実施例が可能である。
FIG. 3 shows a stripe pattern formed in a ring shape. It is possible to form such an annular groove having a width of about 1 μ in the entire lower surface of the bonding pad and then oxidize the groove-side surface to make the entire stripe-formed area a thick oxide film area. it can. Similarly, FIG. 4 shows a case where the stripe pattern is formed in a square band shape. FIG. 5 shows a case where the stripe pattern is formed in a strip shape. FIG. 7 shows a case where the stripe pattern is formed in a cell mesh shape. In addition, the stripe pattern is such that when the stripe portion is just oxidized from both sides, the groove is just filled with the oxide film,
As long as the dimensional ratio is sufficient, various modifications other than those shown in FIGS. 3 and 6 are possible.

【0015】次に、図7乃至13を参照しながら厚い酸
化膜の形成方法について説明する。図7に示すように、
まずシリコン半導体基板11に薄い酸化膜25を被着
し、同様に窒化膜26を気相成長により被着する。酸化
膜の厚さは500Å程度が、窒化膜の厚さは1000Å
程度が好ましい。次に、図8に示すようにその上にノン
ドープの酸化膜27を同様に気相成長により被着する。
その厚さは、2000〜3000Åであることが好まし
い。
Next, a method for forming a thick oxide film will be described with reference to FIGS. As shown in FIG.
First, a thin oxide film 25 is deposited on the silicon semiconductor substrate 11, and a nitride film 26 is similarly deposited by vapor phase growth. The thickness of the oxide film is about 500Å, but the thickness of the nitride film is 1000Å
The degree is preferred. Next, as shown in FIG. 8, a non-doped oxide film 27 is similarly deposited thereon by vapor phase growth.
The thickness is preferably 2000 to 3000Å.

【0016】次に、レジストパターニングを行う。これ
はまずフォトレジスト28を全面に塗布し、前述した図
3及び図6に示すストライプパターンを有するマスクに
従って露光し、現像することにより図9に示すレジスト
パターン28を形成する。このレジストパターンの幅及
び開口部の幅は本実施例においてはそれぞれ1.1/
0.9μm程度である。そして、レジストパターン28
をマスクとしてノンドープ酸化膜27、シリコン窒化膜
26及び酸化膜25をドライエッチングする。そして、
フォトレジスト膜28を除去する。この段階を図10に
示す。
Next, resist patterning is performed. First, a photoresist 28 is applied on the entire surface, and is exposed and developed according to the mask having the stripe pattern shown in FIGS. 3 and 6 described above to form the resist pattern 28 shown in FIG. In this embodiment, the width of the resist pattern and the width of the opening are 1.1 /, respectively.
It is about 0.9 μm. Then, the resist pattern 28
Using the as a mask, the non-doped oxide film 27, the silicon nitride film 26, and the oxide film 25 are dry-etched. And
The photoresist film 28 is removed. This stage is shown in FIG.

【0017】そして、ノンドープシリコン酸化膜27を
マスクとして、シリコン半導体基板11を異方性エッチ
ングして深さ2μm程度の溝22を形成する。この段階
で、シリコン半導体基板11にストライプ部分21及び
溝部分22が形成される。これを図11に示す。次に酸
化膜27を除去した状態(図12参照)、又は酸化膜を
残した状態(図11参照)で酸化に入る。これらの窒化
膜等は、酸化終了後に除去する。
Then, using the non-doped silicon oxide film 27 as a mask, the silicon semiconductor substrate 11 is anisotropically etched to form a groove 22 having a depth of about 2 μm. At this stage, the stripe portion 21 and the groove portion 22 are formed on the silicon semiconductor substrate 11. This is shown in FIG. Next, oxidation is started with the oxide film 27 removed (see FIG. 12) or with the oxide film left (see FIG. 11). These nitride films and the like are removed after the oxidation is completed.

【0018】そして、ストライプ状に形成されたシリコ
ン基板をLOCOS法と同様なウェット酸化条件により
酸化する。酸化はストライプ21の表面から徐々に進行
し、ストライプ21内部に広がると共に溝22側にも酸
化膜が成長し、図13に示すように溝部分22の幅が徐
々に狭くなる。そして、更に酸化が進行すると図14に
示すように、ストライプ部分21が両側から丁度酸化さ
れると共に、溝部分22が完全に埋まり、厚い酸化膜1
8,19が形成される。この厚い酸化膜18、19は、
その周辺部とほとんど段差が無く、平坦に形成できる。
従って、電極配線を容易に形成できる。
Then, the silicon substrate formed in a stripe shape is oxidized under the same wet oxidation condition as the LOCOS method. Oxidation gradually progresses from the surface of the stripe 21, spreads inside the stripe 21, and an oxide film grows also on the groove 22 side, and the width of the groove portion 22 gradually narrows as shown in FIG. Then, as the oxidation further progresses, as shown in FIG. 14, the stripe portion 21 is just oxidized from both sides, and the groove portion 22 is completely filled, so that the thick oxide film 1 is formed.
8 and 19 are formed. The thick oxide films 18 and 19 are
It can be formed flat with almost no step difference from its peripheral portion.
Therefore, the electrode wiring can be easily formed.

【0019】超高周波トランジスタの製造に当たって
は、ボンディングパッドの配置部分に、前述した厚さ約
2μmの酸化膜をまず形成する。次に通常のLOCOS
法によりフィールド酸化膜を形成する。そして、アクテ
ィブ領域にベース及びエミッタの拡散領域を形成する。
次に、配線電極材料をスパッタリング等により被着し
て、レジストパターニングにより、ボンディングパッド
を含めた配線電極を形成する。
In manufacturing the ultra high frequency transistor, the oxide film having a thickness of about 2 .mu.m described above is first formed on the portion where the bonding pad is arranged. Then the normal LOCOS
A field oxide film is formed by the method. Then, base and emitter diffusion regions are formed in the active region.
Next, a wiring electrode material is deposited by sputtering or the like, and a wiring electrode including a bonding pad is formed by resist patterning.

【0020】尚、フィールド酸化膜の形成は、本発明の
厚い酸化膜の形成時に、ストライプパターンの形成に利
用した窒化膜を用いて、同時に行うようにしてもよい。
係る製造工程によれば、ストライプパターンの溝部形成
の工程が増加するだけで、本発明の厚い酸化膜を備えた
半導体装置を製造することができる。
The field oxide film may be formed simultaneously with the formation of the thick oxide film of the present invention by using the nitride film used for forming the stripe pattern.
According to such a manufacturing process, the semiconductor device having the thick oxide film of the present invention can be manufactured only by increasing the number of processes for forming the groove portion of the stripe pattern.

【0021】尚、以上の実施例の説明はストライプ部分
及び溝部分の幅を約1μm程度としたが、微細加工技術
の進歩によりストライプ部分の幅及び溝部分の幅をより
を狭くすることにより、更に酸化時間が短縮され、結晶
欠陥の発生等の問題を低減することができる。
In the above description of the embodiment, the width of the stripe portion and the groove portion is about 1 μm, but the width of the stripe portion and the groove portion are made narrower by the progress of the fine processing technology. Furthermore, the oxidation time can be shortened, and problems such as the occurrence of crystal defects can be reduced.

【0022】又、上述した実施例においては、シリコン
基板のエッチングを、ノンドープ酸化膜をマスクとして
行う例について説明したが、シリコン窒化膜/酸化膜を
エッチングする時のレジストをマスクとしてエッチング
するようにしても勿論良い。
Further, in the above-mentioned embodiment, the example of etching the silicon substrate using the non-doped oxide film as a mask has been described. However, the etching when the silicon nitride film / oxide film is etched is carried out using the resist as a mask. But of course it is good.

【0023】又、上述した実施例ではボンディングパッ
ドの部分のみを本発明の厚い酸化膜で形成したが、電極
配線の下部全体、或いはアクティブ領域を除くチップ全
体にわたって本発明の厚い酸化膜としても良い。このよ
うにすることによって、チップの表面が平坦化され、段
差が無くなることにより微細パターンの電極配線が容易
となる。
Further, in the above-described embodiment, only the bonding pad portion is formed of the thick oxide film of the present invention, but the thick oxide film of the present invention may be formed over the entire lower portion of the electrode wiring or the entire chip except the active region. . By doing so, the surface of the chip is flattened and the steps are eliminated, so that the electrode wiring of the fine pattern is facilitated.

【0024】[0024]

【発明の効果】以上に説明したように本発明の厚い酸化
膜の形成方法によれば、ストライプ部分の溝の深さのコ
ントロールにより、必要な酸化膜の厚さを稼ぐことがで
きる。そして、この時の酸化条件は、本実施例では通常
のLOCOS法による12000Å成長時の酸化時間で
よく、高温長時間の酸化に伴う結晶欠陥の発生は、通常
のLOCOS酸化法におけるのと同程度に抑えることが
できる。
As described above, according to the method for forming a thick oxide film of the present invention, the required oxide film thickness can be obtained by controlling the depth of the groove in the stripe portion. In this embodiment, the oxidation condition at this time may be an oxidation time at the time of 12000Å growth by the normal LOCOS method, and the generation of crystal defects due to the oxidation at a high temperature for a long time is similar to that in the normal LOCOS oxidation method. Can be suppressed to

【0025】又、本発明の厚い酸化膜の形成方法によれ
ば、酸化がストライプ部分の表面から基板の表面方向に
進行するため、基板の上面方向への盛り上がり成長がほ
とんど無い。このため、本発明の酸化方法を用いること
により、厚い酸化膜を、その周辺に対してほぼ平坦な面
に形成することができる。
Further, according to the method for forming a thick oxide film of the present invention, since oxidation proceeds from the surface of the stripe portion toward the surface of the substrate, there is almost no bulging growth in the direction of the upper surface of the substrate. Therefore, by using the oxidation method of the present invention, a thick oxide film can be formed on a surface which is almost flat with respect to the periphery thereof.

【0026】又、本発明の厚い酸化膜を用いた超高周波
トランジスタ等の半導体装置は、比較的面積が大きいボ
ンディングパッド部分の下部に、上述した厚い酸化膜を
用いることにより、電極配線の浮遊容量を著しく低減す
ることができ、パワーゲイン特性等の高周波特性を改善
することができる。そして、表面が平坦で、且つ十分な
厚さの酸化膜を得ることができることから、電極配線は
単層構造で十分であり、製造工程を簡素化することがで
きる。
Further, in the semiconductor device such as an ultra-high frequency transistor using a thick oxide film of the present invention, the above-mentioned thick oxide film is used under the bonding pad portion having a relatively large area, whereby the stray capacitance of the electrode wiring is reduced. Can be significantly reduced, and high frequency characteristics such as power gain characteristics can be improved. Further, since the oxide film having a flat surface and a sufficient thickness can be obtained, the electrode wiring has a single-layer structure, and the manufacturing process can be simplified.

【0027】更に、ボンディングパッド直下以外のフィ
ールド領域を通常のLOCOS酸化法で得る場合には、
フィールド領域の酸化膜厚を従来の厚さの半分程度で十
分な高周波特性が得られる。このため、酸化時間、温度
等を低減することができ、バーズビーグによる結晶欠陥
等の発生を抑制することができる。総じて本発明によれ
ば、厚い酸化膜を備えることにより高周波特性の改善さ
れた超高周波トランジスタ等を、より高い品質で製造す
ることが可能となる。
Further, when the field region other than directly under the bonding pad is obtained by the usual LOCOS oxidation method,
Sufficient high-frequency characteristics can be obtained when the oxide film thickness in the field region is about half the conventional thickness. Therefore, it is possible to reduce the oxidation time, the temperature, and the like, and it is possible to suppress the occurrence of crystal defects and the like due to bird's beag. In general, according to the present invention, it becomes possible to manufacture an ultra high frequency transistor or the like having a high frequency characteristic improved by providing a thick oxide film with higher quality.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の超高周波トランジスタチッ
プのパターン図。
FIG. 1 is a pattern diagram of an ultra high frequency transistor chip according to an embodiment of the present invention.

【図2】図1における超高周波トランジスタの部分断面
図。
FIG. 2 is a partial cross-sectional view of the ultra high frequency transistor in FIG.

【図3】本発明の一実施例の円環状のストライプパター
ンの説明図。
FIG. 3 is an explanatory diagram of an annular stripe pattern according to an embodiment of the present invention.

【図4】本発明の一実施例の角帯状のストライプパター
ンの説明図。
FIG. 4 is an explanatory diagram of a square striped stripe pattern according to an embodiment of the present invention.

【図5】本発明の一実施例の細帯状のストライプパター
ンの説明図。
FIG. 5 is an explanatory diagram of a striped stripe pattern according to an embodiment of the present invention.

【図6】本発明の一実施例の酸化前のセル・メッシュ状
のストライプパターンの説明図。
FIG. 6 is an explanatory diagram of a cell mesh-shaped stripe pattern before oxidation according to an embodiment of the present invention.

【図7】本発明の一実施例の厚い酸化膜を形成する工程
の説明図。
FIG. 7 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図8】本発明の一実施例の厚い酸化膜を形成する工程
の説明図。
FIG. 8 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図9】本発明の一実施例の厚い酸化膜を形成する工程
の説明図。
FIG. 9 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図10】本発明の一実施例の厚い酸化膜を形成する工
程の説明図。
FIG. 10 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図11】本発明の一実施例の厚い酸化膜を形成する工
程の説明図。
FIG. 11 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図12】本発明の一実施例の厚い酸化膜を形成する工
程の説明図。
FIG. 12 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図13】本発明の一実施例の厚い酸化膜を形成する工
程の説明図。
FIG. 13 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

【図14】本発明の一実施例の厚い酸化膜を形成する工
程の説明図。
FIG. 14 is an explanatory diagram of a process of forming a thick oxide film according to an embodiment of the present invention.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に酸化膜と窒化膜とを被着
し、該酸化膜と窒化膜に開口を設け、該開口より前記基
板をエッチングすることによりストライプ状の深い溝を
形成し、該深い溝の側表面を酸化することにより、前記
ストライプ状の基板部分を酸化して、前記溝の深さに相
当する厚みの酸化膜を形成することを特徴とした酸化膜
の形成方法。
1. A semiconductor substrate is coated with an oxide film and a nitride film, openings are formed in the oxide film and the nitride film, and the substrate is etched through the openings to form deep stripe grooves. A method for forming an oxide film, characterized in that the side surface of the deep groove is oxidized to oxidize the stripe-shaped substrate portion to form an oxide film having a thickness corresponding to the depth of the groove.
【請求項2】 前記請求項1に記載の厚い酸化膜を少な
くともボンディングパッドの下面に備えることを特徴と
した半導体装置。
2. A semiconductor device comprising the thick oxide film according to claim 1 on at least a lower surface of a bonding pad.
JP25387695A 1995-09-29 1995-09-29 Method for manufacturing semiconductor device Expired - Fee Related JP3162970B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25387695A JP3162970B2 (en) 1995-09-29 1995-09-29 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25387695A JP3162970B2 (en) 1995-09-29 1995-09-29 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0997790A true JPH0997790A (en) 1997-04-08
JP3162970B2 JP3162970B2 (en) 2001-05-08

Family

ID=17257367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25387695A Expired - Fee Related JP3162970B2 (en) 1995-09-29 1995-09-29 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3162970B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10302623A1 (en) * 2003-01-23 2004-08-05 Infineon Technologies Ag Semiconductor structure with a reduced connection capacity and a method for producing the semiconductor structure
JP2005223325A (en) * 2004-02-09 2005-08-18 Semiconductor Components Industries Llc Semiconductor device with reduced capacity with respect to substrate, and manufacturing method therefor
JP2006100825A (en) * 2004-09-29 2006-04-13 Agere Systems Inc Thick oxide region in semiconductor device and its forming method
JP2008153685A (en) * 2001-05-18 2008-07-03 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153685A (en) * 2001-05-18 2008-07-03 Fuji Electric Device Technology Co Ltd Method for manufacturing semiconductor device
DE10302623A1 (en) * 2003-01-23 2004-08-05 Infineon Technologies Ag Semiconductor structure with a reduced connection capacity and a method for producing the semiconductor structure
WO2004066385A2 (en) * 2003-01-23 2004-08-05 Infineon Technologies Ag Semiconductor structure having a reduced connecting capacitance and method for producing the semiconductor structure
WO2004066385A3 (en) * 2003-01-23 2005-04-14 Infineon Technologies Ag Semiconductor structure having a reduced connecting capacitance and method for producing the semiconductor structure
DE10302623B4 (en) * 2003-01-23 2006-12-28 Infineon Technologies Ag Semiconductor structure with a reduced terminal capacitance and a method for producing the semiconductor structure
JP2005223325A (en) * 2004-02-09 2005-08-18 Semiconductor Components Industries Llc Semiconductor device with reduced capacity with respect to substrate, and manufacturing method therefor
JP2006100825A (en) * 2004-09-29 2006-04-13 Agere Systems Inc Thick oxide region in semiconductor device and its forming method

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