JPS6212663B2 - - Google Patents
Info
- Publication number
- JPS6212663B2 JPS6212663B2 JP14526277A JP14526277A JPS6212663B2 JP S6212663 B2 JPS6212663 B2 JP S6212663B2 JP 14526277 A JP14526277 A JP 14526277A JP 14526277 A JP14526277 A JP 14526277A JP S6212663 B2 JPS6212663 B2 JP S6212663B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon nitride
- nitride film
- oxide film
- silicon oxide
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 description 23
- 239000000758 substrate Substances 0.000 description 16
- 239000011347 resin Substances 0.000 description 15
- 229920005989 resin Polymers 0.000 description 15
- 238000000034 method Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000149 argon plasma sintering Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910021339 platinum silicide Inorganic materials 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
Description
【発明の詳細な説明】
本発明は半導体素子製造方法に於ける電極形成
技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electrode forming technique in a semiconductor device manufacturing method.
超高周波トランジスタの如き高信頼度を要求さ
れる半導体素子には、一般に、チタン―白金―金
の様な多層構造の電極が使用されているが、半導
体基板と電極との接着強度を得るために、前記チ
タン―白金―金を被着する前に、半導体基板上の
シリコン酸化膜上にシリコン窒化膜層を被着する
ことが採用されている。 Semiconductor devices that require high reliability, such as ultra-high frequency transistors, generally use multilayer electrodes such as titanium-platinum-gold. , it has been adopted to deposit a silicon nitride film layer on the silicon oxide film on the semiconductor substrate before depositing the titanium-platinum-gold film.
この様な構造を有する半導体素子の製造方法と
しては、半導体基板にベース領域を形成した後
に、シリコン酸化膜を形成し、該酸化膜上に気相
成長によりシリコン窒化膜を、およそ1000〜2000
Åの厚さで成長せしめ、しかる後にフオトエツチ
ング法により、将来エミツタ窓部若しくはベース
電極付設用窓部と成るべき部分のシリコン窓化膜
を開孔し、その後新たにフオトエツチング法によ
り前記シリコン窒化膜の開孔部内のシリコン酸化
膜にエツチングを施し、エミツタ窓若しくはベー
ス電極付設用窓を形成していく方法がある。 As a manufacturing method for a semiconductor element having such a structure, after forming a base region on a semiconductor substrate, a silicon oxide film is formed, and a silicon nitride film is deposited on the oxide film by vapor phase epitaxy.
The silicon windowed film is grown to a thickness of 1.5 Å, and then a photoetching method is used to open a hole in the silicon window film in the area that will become the emitter window or the base electrode attachment window in the future. There is a method of etching the silicon oxide film within the opening of the film to form an emitter window or a base electrode attachment window.
しかるにこの様な方法を用いると、シリコン窒
化膜の厚みによる段差が1000〜2000Å発生する理
由で、エミツタ窓若しくはベース電極付設用窓を
半導体基板上のフオトレジストに形成する場合に
光の散乱によつて、所望の寸法の窓が形成しにく
いという欠点があつた。 However, when such a method is used, a step difference of 1000 to 2000 Å occurs due to the thickness of the silicon nitride film, and when forming an emitter window or a window for attaching a base electrode in a photoresist on a semiconductor substrate, it is difficult to prevent light scattering. However, there was a drawback in that it was difficult to form windows of desired dimensions.
かかる欠点を解消せしめるために、本発明は、
将来半導体素子の外部引出し電極の外部リート線
との接続部分（いわゆるボンデイングパツド）の
形成される領域のみにシリコン窒化膜を残し、そ
の他の領域の半導体基板上のシリコン窒化膜をフ
オトエツチング法により除去することを特徴とす
る。 In order to eliminate such drawbacks, the present invention
The silicon nitride film is left only in the area where the connection part (so-called bonding pad) with the external lead wire of the external lead electrode of the semiconductor element will be formed in the future, and the silicon nitride film on the semiconductor substrate in other areas is photoetched. It is characterized by removal.
本発明によれば、その後エミツタ窓若しくはベ
ース電極付設用窓を前記半導体基板上のフオトレ
ジストに形成する場合に、その近傍にシリコン窒
化膜の厚みによる段差が無い理由で、１〜２μの
細いエミツタ窓も容易に形成できる。 According to the present invention, when an emitter window or a base electrode attachment window is subsequently formed in the photoresist on the semiconductor substrate, a thin emitter window of 1 to 2 μm is formed because there is no step in the vicinity of the window due to the thickness of the silicon nitride film. Windows can also be easily formed.
次に従来の電極形成方法について図面を用いて
説明する。 Next, a conventional electrode forming method will be explained using the drawings.
まず第１図に示すように、従来公知の方法によ
り、半導体基板４にベース領域１を形成した後
に、熱成長シリコン酸化膜２を形成し、その上に
気相成長法によりシリコン窒化膜３を1000〜2000
Å成長せしめた後、フオトエツチング法により将
来エミツタ窓部若しくはベース電極付設用窓とな
るべき部分の感光性樹脂膜５を開孔する。 First, as shown in FIG. 1, a base region 1 is formed on a semiconductor substrate 4 by a conventionally known method, a thermally grown silicon oxide film 2 is formed, and a silicon nitride film 3 is formed thereon by a vapor phase growth method. 1000~2000
After the growth, a hole is formed in the photosensitive resin film 5 at a portion that will become an emitter window or a window for attaching a base electrode in the future by photoetching.
次に第２図に示すように、前記感光性樹脂膜５
をマスクに将来エミツタ窓部若しくはベース電極
付設用窓部となるべき領域のシリコン窒化膜を除
去する。シリコン窒化膜のエツチングには弗化炭
素系のガスによるプラズマガスエツチング法が用
いられる。 Next, as shown in FIG. 2, the photosensitive resin film 5
Using this as a mask, remove the silicon nitride film in the area that will become the emitter window or base electrode attachment window in the future. For etching the silicon nitride film, a plasma gas etching method using a carbon fluoride gas is used.
次いで第３図に示すように、前記半導体基板上
に感光性樹脂膜５′を被覆しエミツタ拡散窓を設
けるためのパターン形成を行なう。 Next, as shown in FIG. 3, a photosensitive resin film 5' is coated on the semiconductor substrate and a pattern is formed to provide an emitter diffusion window.
しかしシリコン窒化膜を開孔した領域にエミツ
タ窓を形成しようとすると、シリコン酸化膜表面
とシリコン窒化膜との段差が1000〜2000Åあるの
で、その上に被覆した感光性樹脂膜にも凹凸を生
じる。従つて、感光性樹脂膜の露光の際に光の散
乱を招き、例えば第３図に示すように、感光性樹
脂膜に穿孔したい幅寸法１に対して実際には幅寸
法１′のごとき小さな開孔部しか得られなくなる
ことがきわめて多い。 However, when trying to form an emitter window in the area where the silicon nitride film is opened, there is a step difference of 1000 to 2000 Å between the silicon oxide film surface and the silicon nitride film, so the photosensitive resin film coated on top of it also becomes uneven. . Therefore, light scattering occurs during exposure of the photosensitive resin film, and for example, as shown in FIG. Quite often, only open holes are obtained.
然る後、第４図に示すように、前記半導体基板
のシリコン酸化膜をエツチングしてエミツタ窓を
形成するが、前述のように感光樹脂膜に所望の寸
法のパターンが得られていないので、シリコン酸
化膜にも所望寸法のパターンが得られないことに
なる。 Thereafter, as shown in FIG. 4, the silicon oxide film of the semiconductor substrate is etched to form an emitter window, but as mentioned above, a pattern with the desired dimensions was not obtained on the photosensitive resin film. Also, a pattern with the desired size cannot be obtained in the silicon oxide film.
このように、１〜２μの微細なエミツタ窓を前
記シリコン窒化膜の開孔した領域内に形成するこ
とは非常に困難であり、製造歩留りもきわめて悪
いものとなる。 As described above, it is very difficult to form a fine emitter window of 1 to 2 μm in the open area of the silicon nitride film, and the manufacturing yield is also extremely poor.
本発明はかかる欠点を解消せしめるため、ベー
ス領域を形成した後にシリコン酸化膜を形成し、
該酸化膜上に気相成長によりシリコン窒化膜をお
よそ1000〜2000Åの厚さで成長せしめた後、フオ
トエツチング法により将来半導体素子の引出し電
極と外部リード線との接続部となる部分（ボンデ
イングパツドが形成されるべき領域）のみにシリ
コン窒化膜を残し、その他の領域の半導体基板上
のシリコン窒化膜を除去することにより、エミツ
タ窓若しくはベース電極付設用窓を設けるために
感光性樹脂膜をパターン化するさいに、シリコン
窒化膜の段差に起因する感光性樹脂膜の凹凸によ
る光の散乱によつて、解像力が低下するのを防ぐ
事を特徴とする。 In order to eliminate such drawbacks, the present invention forms a silicon oxide film after forming the base region,
After growing a silicon nitride film to a thickness of approximately 1000 to 2000 Å on the oxide film by vapor phase growth, a bonding patch is formed on the portion that will become the connection between the extraction electrode of the semiconductor element and the external lead wire in the future using the photoetching method. By leaving the silicon nitride film only on the area where the electrode is to be formed and removing the silicon nitride film on the other areas of the semiconductor substrate, a photosensitive resin film is formed in order to provide an emitter window or a window for attaching the base electrode. The feature is that during patterning, resolution is prevented from decreasing due to light scattering due to unevenness of the photosensitive resin film caused by steps in the silicon nitride film.
次に本発明をその好ましい実施例に基づき図面
を参照して詳細に説明する。 Next, the present invention will be explained in detail based on preferred embodiments thereof with reference to the drawings.
まず第５図に示すように、従来公知の方法によ
り、半導体基板４にベース領域１を形成した後に
熱成長シリコン酸化膜２を形成し、その上に気相
成長法によりシリコン窒化膜３を形成し、その後
将来半導体素子の引出し電極と外部リード線との
接続部となる部分のみに感光性樹脂５を形成す
る。 First, as shown in FIG. 5, a base region 1 is formed on a semiconductor substrate 4 by a conventionally known method, a thermally grown silicon oxide film 2 is formed, and a silicon nitride film 3 is formed thereon by a vapor phase growth method. Thereafter, photosensitive resin 5 is formed only on the portion that will become the connecting portion between the extraction electrode of the semiconductor element and the external lead wire in the future.
次に第６図に示すように、前記半導体基板のシ
リコン窒化膜を弗化炭素系のガスプラズマエツチ
ング法により除去する。 Next, as shown in FIG. 6, the silicon nitride film on the semiconductor substrate is removed by carbon fluoride gas plasma etching.
次いで第７図に示すように、前記半導体基板表
面に感光性樹脂膜５′を新たに形成し、エミツタ
拡散用窓を形成するため該感光性樹脂膜をパター
ン化して開孔ａを形成する。同図から明らかな如
く、本発明によれば、シリコン窒化膜の厚みに起
因する段差は、エミツタ窓を設ける領域から非常
に遠くに離れているので、当該領域においては感
光性樹脂膜は平坦に形成される。従つて、露光時
の光の散乱がきわめて少なくなり、エミツタ窓と
して１〜２μの微細な寸法を有するパターンも容
易に形成する事ができるようになつた。次に第８
図に示すように、前記感光性樹脂膜５をマスクに
エミツタ窓a′をシリコン酸化膜２に穿設する。し
かる後に不純物拡散を行なつてエミツタ領域１０
を形成する。 Next, as shown in FIG. 7, a photosensitive resin film 5' is newly formed on the surface of the semiconductor substrate, and the photosensitive resin film is patterned to form openings a in order to form emitter diffusion windows. As is clear from the figure, according to the present invention, the step caused by the thickness of the silicon nitride film is very far away from the region where the emitter window is provided, so the photosensitive resin film is flat in that region. It is formed. Therefore, scattering of light during exposure is extremely reduced, and it has become possible to easily form patterns having minute dimensions of 1 to 2 μm as emitter windows. Then the 8th
As shown in the figure, an emitter window a' is formed in the silicon oxide film 2 using the photosensitive resin film 5 as a mask. Thereafter, impurity diffusion is performed to form the emitter region 10.
form.
次に第９図に示すように、ベース電極付設用窓
ｂをフオトエツチング法にて穿設する。この場合
もエミツタ窓を形成した場合と同じ理由で電極付
設窓の形成が従来より著しく容易になり、また寸
法精度も改善された。次に半導体基板の前記エミ
ツタ及びベースのコンタクト窓部に白金シリサイ
ド層を形成し、その後チタン１２―白金１３―金
１４からなる多層構造の電極を形成する。 Next, as shown in FIG. 9, a base electrode mounting window b is formed by photoetching. In this case as well, for the same reason as in the case of forming the emitter window, the formation of the electrode-attached window has become much easier than in the past, and the dimensional accuracy has also been improved. Next, a platinum silicide layer is formed in the contact windows of the emitter and base of the semiconductor substrate, and then an electrode having a multilayer structure consisting of 12 titanium, 13 platinum, and 14 gold is formed.
第９図に示す本発明の構造によつても、従来の
構造と比べて、電極とシリコン窒化膜、シリコン
窒化膜とシリコン酸化膜との接着強度は全く劣る
事が無い事が確認された。 It was confirmed that even with the structure of the present invention shown in FIG. 9, the adhesion strength between the electrode and the silicon nitride film, and between the silicon nitride film and the silicon oxide film is not inferior at all compared to the conventional structure.
以上説明してきた如く本発明は、電極金属と半
導体基板の接着強度を向上させるために、シリコ
ン窒化膜を引出し電極部の外部リード線との接続
部（いわゆるボンデイングパツド部）の下にのみ
形成することによつて、電極金属と半導体基板の
接着度を良好に保つと共に、シリコン窒化膜によ
る段差のエミツタ窓開け及びベース電極付設用窓
開けに対する悪影響を極力減少せしめる事により
半導体素子製造における製造歩留りを向上せしめ
る事を可能とするものである。 As explained above, in order to improve the adhesive strength between the electrode metal and the semiconductor substrate, the present invention involves forming a silicon nitride film only under the connection part of the electrode part with the external lead wire (so-called bonding pad part). By doing so, the degree of adhesion between the electrode metal and the semiconductor substrate is maintained at a good level, and the adverse effects of the steps caused by the silicon nitride film on the opening of the emitter window and the opening of the base electrode attachment window are minimized, thereby improving the production yield in semiconductor device manufacturing. This makes it possible to improve the
尚本発明は上記実施例に示したトランジスタに
限らず、他のあらゆる半導体素子の引出し型電極
の形成に実施する事が可能である。即ち実施例に
あげた具体的な材料、形状に限られるものでなく
本発明の目的を遂行するものであればその種類を
問うものではない。 The present invention is not limited to the transistors shown in the above embodiments, but can be applied to the formation of lead-out electrodes of all other semiconductor elements. That is, the material is not limited to the specific materials and shapes mentioned in the examples, but any type can be used as long as it achieves the purpose of the present invention.
第１図〜第４図は従来の製造方法を説明するた
めの断面図であり、第５図〜第９図は本発明をシ
リコン拡散型トランジスタ素子の引出し電極の製
造に実施した場合の断面図である。
１……ベース領域、２……熱成長シリコン酸化
膜、３……気相成長シリコン窒化膜、４……シリ
コン基板、５，５′……感光性樹脂膜、１０……
エミツタ領域、１１……白金シリサイド層、１２
……チタン層、１３……白金層、１４……金属、
ａ……感光性樹脂膜に穿設された開孔、a′……シ
リコン酸化膜に穿設されたエミツタ窓。
FIGS. 1 to 4 are cross-sectional views for explaining the conventional manufacturing method, and FIGS. 5 to 9 are cross-sectional views when the present invention is applied to manufacturing an extraction electrode of a silicon diffused transistor element. It is. DESCRIPTION OF SYMBOLS 1... Base region, 2... Thermally grown silicon oxide film, 3... Vapor phase grown silicon nitride film, 4... Silicon substrate, 5, 5'... Photosensitive resin film, 10...
Emitter region, 11...Platinum silicide layer, 12
...Titanium layer, 13...Platinum layer, 14...Metal,
a...Aperture made in the photosensitive resin film, a'...Emit window made in the silicon oxide film.
Claims (1)
し、これらベースおよびコレクタ領域の表面をシ
リコン酸化膜で被覆する工程と、前記シリコン酸
化膜上にシリコン窒化膜を形成する工程と、前記
シリコン窒化膜を前記ベース領域の平面的な大き
さよりも広い範囲にわたつて選択的に除去し前記
シリコン窒化膜を前記コレクタ領域の表面を覆う
前記シリコン酸化膜上にのみ残す工程と、前記ベ
ース領域の表面を覆う前記シリコン酸化膜の一部
を除いて前記残つたシリコン窒化膜およびシリコ
ン酸化膜上にマスク層を形成する工程と、前記マ
スク層を用いて前記シリコン酸化膜を選択的に除
去し前記ベース領域内にエミツタ領域を形成する
工程と、前記ベース領域および前記エミツタ領域
の一部にそれぞれ接触し前記シリコン酸化膜を経
て前記残つたシリコン窒化膜上に延在形成され、
かつ前記残つたシリコン窒化膜上に位置する部分
をボンデイングパツド部分とするベース電極およ
びエミツタ電極を形成する工程とを有することを
特徴とする半導体素子の製造方法。1. A step of selectively forming a base region in the collector region and covering the surfaces of the base and collector regions with a silicon oxide film, a step of forming a silicon nitride film on the silicon oxide film, and a step of forming a silicon nitride film on the silicon oxide film. selectively removing the silicon nitride film over a wider area than the planar size of the base region, leaving the silicon nitride film only on the silicon oxide film covering the surface of the collector region; and covering the surface of the base region. a step of forming a mask layer on the remaining silicon nitride film and silicon oxide film by removing a part of the silicon oxide film; and a step of selectively removing the silicon oxide film using the mask layer and forming a mask layer in the base region. forming an emitter region on the remaining silicon nitride film through the silicon oxide film in contact with a portion of the base region and the emitter region, respectively;
and forming a base electrode and an emitter electrode in which the portions located on the remaining silicon nitride film serve as bonding pad portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14526277A JPS5477569A (en) | 1977-12-02 | 1977-12-02 | Production of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14526277A JPS5477569A (en) | 1977-12-02 | 1977-12-02 | Production of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5477569A JPS5477569A (en) | 1979-06-21 |
| JPS6212663B2 true JPS6212663B2 (en) | 1987-03-19 |
Family
ID=15381054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14526277A Granted JPS5477569A (en) | 1977-12-02 | 1977-12-02 | Production of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5477569A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6260249A (en) * | 1985-09-09 | 1987-03-16 | Nec Corp | Semiconductor device |
-
1977
- 1977-12-02 JP JP14526277A patent/JPS5477569A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5477569A (en) | 1979-06-21 |
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