JPH0114709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for connecting wiring between elements during an integrated circuit manufacturing process.

Conventional wiring technology for integrated circuits has generally involved a method of forming wiring metal only by etching, as shown in FIG. The semiconductor element 12 on the surface of the semiconductor substrate 11 is covered with an insulating film 13, and a connection hole 14 is opened. The insulating film 13 almost directly reflects the undulations of the element 12, and the surface of the insulating film 13 also has undulations. Therefore, the wiring metal 15 deposited on the entire surface also has undulations (see FIG. 1a). In this state, if the wiring metal 15 is etched to form a wiring connection between elements, the wiring metal 15' remains under the insulating film step, as shown in FIG. It was hot. In order to prevent short circuits, a method of flattening the insulating film is to deposit a thick insulating film 23 and flatten the resist 24 thereon, as shown in FIG. 2a.
A method of planarizing the resist and insulating film by etching an appropriate amount (Fig. 2b) (for example, ACAdams
“Plasma Planarization”Solid State
Technology (1981) vol 4, 178-181), but it has the disadvantage that the process is complicated. In the figure, 21 indicates a semiconductor substrate.

There is also a method of forming wiring metal by a lift-off method as shown in FIG. 3, but there is a drawback that the wiring resistance cannot be reduced because the thickness of the wiring metal is limited. In the figure, 31 is a semiconductor substrate, 32 is a semiconductor element, 33 is an insulating film, 34 is a connection hole, 35 is a photoresist, and 36 is a wiring metal.

The present invention was proposed in order to improve the above-mentioned drawbacks, and its characteristic point is that in the wiring connection process of a plurality of semiconductor elements formed on a semiconductor substrate, A step of coating the protective film A made of photoresist or polyimide on the surface of the protective film A, a step of removing the protective film A of the portion to be connected to the wiring to expose the portion to be connected to the wiring, and a step of heating the protective film made of photoresist or polyimide. A step of thermally deforming and planarizing A, a step of depositing a wiring metal layer on the main surface, a step of forming a protective film B covering the wiring area on the surface of the wiring metal layer, and using the protective film B as a mask. , an inter-element wiring connection method characterized by comprising a step of etching away an unnecessary metal layer and a step of removing protective films A and B.

In other words, the main features of the present invention are that (a) photoresist or polyimide is used to form the protective film A, and (b) the protective film is thermally deformed and flattened by heat treatment.

Next, examples of the present invention will be described. In addition,
The embodiments are merely illustrative, and it goes without saying that various changes and improvements can be made without departing from the spirit of the invention.

FIG. 4 shows an embodiment of the method of the invention. A semiconductor element 42 is formed on a semiconductor substrate 41.
On the surface of the semiconductor substrate 41 and the semiconductor element 42
Insulating film 43 such as CVD-SiO ₂ or P-CVD-SiN
A thickness of about 0.3 to 1 .mu.m is deposited, and a hole 44 for connection with the element is etched by a known method (see FIG. 4a).

Next, in order to flatten the surface, a protective film 45 made of, for example, photoresist, polyimide, etc. is applied to a thickness of 1 to 10 μm.
The protective film A is formed by uniformly depositing the protective film A on the entire surface to a certain thickness. Next, the photoresist or polyimide in the wiring area is removed by a known photo process (see FIG. 4b). Even if the surface of the insulating film 43 has undulations of about 1 to 5 μm and has an inverted trapezoidal cross section, the protective film 45 has a sufficiently flat surface. Further, after this step, when heat treatment is performed at 130 to 300°C for about 5 to 60 minutes, the protective film 45 is thermally deformed, flattening progresses further, and the pattern openings also become more obtuse (see Figure 4). b′). Next, as the wiring metal 46, for example, Al, Mo, Ti/Au, Ti/Pt/Au, Ti/
Mo/Au or the like is deposited on the entire surface by vapor deposition or sputtering to a thickness of about 0.5 to 5 μm (see Figure 4c).
At this time, since the surface of the protective film 45 is flattened without being affected by the undulations of the underlying layer, the area where the wiring metal 46 is unnecessary is flattened.

Next, a photoresist 47 covering the wiring area is formed by a known photo process to form a protective layer B. Next, unnecessary metal is removed by reactive ion etching, plasma etching, ion milling, etc. (see FIG. 4d). At this time, since the unnecessary metal region is flattened, it is completely removed and no short circuit occurs in the same wiring layer. In addition, since the etching is a flat metal region, over-etching is almost unnecessary, and the thickness of the insulating film 43 remains unchanged, so that if a further wiring process is required after this, an increase in wiring capacitance can be avoided. hinder.

Finally, the unnecessary resist 47 and protective film 45 are removed to complete the inter-element wiring connection process (see FIG. 4e).

In this embodiment, since the final wiring layer is assumed, a resist 47 is formed so as to overlap the open protective film 45, and the cross section of the wiring metal 46 has an overhang shape (Fig. 4e). reference)
However, if a further upper layer wiring process is required, by forming a resist 47' in the opening of the protective film 45 as shown in FIG. It is possible to obtain wiring connections between elements that are not required.

In a conventional process of this type, there is a method in which a photoresist is used as the protective film A of the present invention, but in this case, an aluminum electrode is formed while being covered with the photoresist. However, when forming an aluminum electrode, a sputtering method, a vapor deposition method, etc. are used, but in this case, the temperature of the substrate surface usually rises to about 100 to 200° C. due to radiant heat of plasma or electron beam. Photoresist exposed to such high temperatures in a vacuum generates bubbles and pattern sag, and cannot be used in the electrode forming process.

However, in the present invention, after patterning the photoresist or polyimide, it is heat-treated until it is thermally deformed (for example, at 120 to 300°C for 10 to 100 minutes), so even if it is exposed to the radiant heat during the metal electrode formation described above, , it is possible to stably form wiring metal without generating any bubbles or pattern sag.

In the present invention, the protective film forming materials are limited to polyimide and photoresist because they need to be patterned, require photosensitivity, can be coated for flattening, and require heat treatment (100 to 300°C).
This is because it is thermally deformed and becomes even more flat.

As explained above, according to the present invention, even when exposed to radiant heat in the electrode forming process, no bubbles or pattern sag occur, and at the same time, the photoresist surface is flattened by thermal deformation, so wiring The over-etching time for the metal layer can be greatly reduced, fine wiring can be formed, and the yield can be improved.

Furthermore, according to the present invention, damage, contamination, etc. that occur during the formation of upper-layer wiring are wiped away when the underlying protective film is removed, so even if the wiring process is performed for a device that is sensitive to surface conditions such as a field effect transistor, the device Changes in characteristics can be prevented. Furthermore, since the thickness of the wiring metal can be made sufficiently thick, the wiring resistance can be reduced, and the operating speed of the integrated circuit can be improved.

[Brief explanation of drawings]

1A and 1B are cross-sectional and perspective views of the wiring process according to the prior art, FIGS. 4a to 4f show an embodiment of the wiring process according to the present invention. 11, 21, 31, 41...semiconductor substrate, 1
2, 22, 32, 42... semiconductor element, 13, 2
3, 33, 43...Insulating film, 14, 34, 44...
... Connection hole, 15, 36, 46, 46'... Metal for wiring, 15'... Metal residue for wiring, 24, 35,
47,47'...Photoresist, 45,45'...
Protective film for flattening.

Claims (1)

[Claims] 1. In the wiring connection process for a plurality of semiconductor elements formed on a semiconductor substrate, the process of coating the semiconductor elements and the semiconductor substrate with a protective film A made of photoresist or polyimide, and the protective film for the parts where the wiring connections will be made. A step of removing the protective film A to expose a portion to be connected to the wiring, a step of thermally deforming and flattening the protective film A made of photoresist or polyimide by heat treatment, and a step of depositing a wiring metal layer on the main surface. , a step of forming a protective film B covering the wiring area on the surface of the wiring metal layer, a step of etching away unnecessary portions of the metal layer using the protective film B as a mask, and a step of removing the protective films A and B. An inter-element wiring connection method characterized by: