JP3157012B2 - Semiconductor element wiring forming method - Google Patents
Semiconductor element wiring forming methodInfo
- Publication number
- JP3157012B2 JP3157012B2 JP17192891A JP17192891A JP3157012B2 JP 3157012 B2 JP3157012 B2 JP 3157012B2 JP 17192891 A JP17192891 A JP 17192891A JP 17192891 A JP17192891 A JP 17192891A JP 3157012 B2 JP3157012 B2 JP 3157012B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- substrate
- antireflection
- point conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体素子における
配線形成方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring in a semiconductor device.
【０００２】[0002]
【従来の技術】半導体素子において配線は従来、図２に
示すように形成されている。まずＩＣ基板１に素子分離
のための絶縁膜２（例えばＳｉＯ2 膜）と拡散層３を形
成した後、層間絶縁膜４（例えばＢＰＳＧ膜）をＣＶＤ
法にて形成する。その後コンタクト孔５を層間絶縁膜４
に形成した後、配線となるＡｌ−Ｓｉ系合金膜６をスパ
ッタ法で形成し、配線パターンにホトリソ・エッチング
でパターニングすることにより配線を完成させる。2. Description of the Related Art Wiring in a semiconductor device is conventionally formed as shown in FIG. First, after an insulating film 2 (for example, SiO 2 film) for element isolation and a diffusion layer 3 are formed on an IC substrate 1, an interlayer insulating film 4 (for example, BPSG film) is formed by CVD.
It is formed by a method. Then, contact holes 5 are formed in interlayer insulating film 4.
Then, an Al—Si alloy film 6 to be a wiring is formed by a sputtering method, and the wiring is completed by patterning the wiring pattern by photolithography and etching.
【０００３】しかしながら、Ａｌ−Ｓｉ系合金膜６単層
で配線を形成した場合は、コンタクト孔５底部のＳｉと
Ａｌ−Ｓｉ系合金界面においてＡｌ−Ｓｉ系合金膜６中
に含まれるＳｉが固相エピタキシャル成長を起し、コン
タクト部における抵抗増大を起す問題点がある。また、
Ａｌ−Ｓｉ系合金膜６の反射率が高いため、ホソリソ工
程において、ノッチが発生し、安定してパターニングが
できない問題点がある。However, when the wiring is formed of a single layer of the Al-Si alloy film 6, the Si contained in the Al-Si alloy film 6 is solidified at the interface between Si at the bottom of the contact hole 5 and the Al-Si alloy. There is a problem that phase epitaxial growth occurs and the resistance at the contact portion increases. Also,
Since the reflectance of the Al—Si alloy film 6 is high, notches are generated in the lithography process, and there is a problem that patterning cannot be performed stably.
【０００４】そこで、これらの問題点を解決するため、
バリアメタル／Ａｌ−Ｓｉ系合金／反射防止膜の３層で
配線を形成する技術が開発されている。その例を図３に
示す。この場合は、ＩＣ基板１１上に先程と同様に素子
分離絶縁膜１２と拡散層１３を形成した後、層間絶縁膜
１４を形成し、この層間絶縁膜１４にコンタクト孔１５
を形成する。そしてスパッタ法によりバリアメタルとし
て高融点導電膜１６を形成し、その上にＡｌ−Ｓｉ系合
金膜１７をスパッタ法で形成し、さらにその上に反射防
止膜として高融点導電膜１８をスパッタ法で形成する。
その後、これら３層をホトリソ・エッチングによりパタ
ーニングして配線を完成させる。この配線形成法によれ
ば、コンタクトの抵抗増大を抑え、かつ安定したパター
ニングができ、良好な特性を持つ半導体素子が得られる
ようになる。[0004] In order to solve these problems,
A technique of forming a wiring with three layers of a barrier metal / Al-Si alloy / antireflection film has been developed. An example is shown in FIG. In this case, after forming the element isolation insulating film 12 and the diffusion layer 13 on the IC substrate 11 in the same manner as before, an interlayer insulating film 14 is formed, and a contact hole 15 is formed in the interlayer insulating film 14.
To form Then, a high-melting-point conductive film 16 is formed as a barrier metal by a sputtering method, an Al-Si-based alloy film 17 is formed thereon by a sputtering method, and a high-melting-point conductive film 18 is further formed thereon as an antireflection film by a sputtering method. Form.
Thereafter, these three layers are patterned by photolithography and etching to complete the wiring. According to this wiring forming method, an increase in contact resistance can be suppressed, stable patterning can be performed, and a semiconductor element having good characteristics can be obtained.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記図
３の配線形成法では、高融点導電膜１６，１８をスパッ
タ法で形成する際、形成方法によっては、膜応力が大き
く変わってしまい、基板の反りが生じる。ホトリソ工程
では、基板上にレジストを塗布した後、露光機で露光す
る場合、基板を固定し焦点深度などの露光調整を行う
が、基板が反っていると、基板面内で一様な露光調整が
行えないこと、さらには基板の固定が不十分なため露光
パターンのずれが生じるという問題点が発生する。However, in the wiring forming method shown in FIG. 3, when the high-melting-point conductive films 16 and 18 are formed by the sputtering method, the film stress is greatly changed depending on the forming method, and the substrate stress is changed. Warpage occurs. In the photolithography process, after applying resist on the substrate, when exposing with an exposure machine, exposure adjustment such as fixing the substrate and depth of focus is performed, but if the substrate is warped, uniform exposure adjustment within the substrate surface Cannot be performed, and the exposure pattern shifts due to insufficient fixing of the substrate.
【０００６】この発明は上記の点に鑑みなされたもの
で、半導体基板上に高融点導電膜／配線膜／反射防止膜
の３層構造で配線を形成する場合に、基板の反りを防止
し、その結果ホトリソ工程を正確にして、高精度の配線
形成を可能にする半導体素子の配線形成方法を提供する
ことを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and when a wiring is formed on a semiconductor substrate in a three-layer structure of a high melting point conductive film / wiring film / antireflection film, the substrate is prevented from warping. As a result, it is an object of the present invention to provide a method for forming a wiring of a semiconductor element, which makes a photolithography process accurate and enables a wiring to be formed with high precision.
【０００７】[0007]
【課題を解決するための手段】この発明は、半導体基板
上に高融点導電膜／配線膜／反射防止膜の３層構造で配
線を形成する場合に、配線膜が持つ引っ張り応力に対し
て、高融点導電膜および反射防止膜のうち少なくとも反
射防止膜の生成条件および膜厚を制御することにより圧
縮応力を制御し、最終的に基板の反りがなくなるように
したものである。According to the present invention, when a wiring is formed on a semiconductor substrate in a three-layer structure of a high melting point conductive film / wiring film / anti-reflection film, the tensile stress of the wiring film is reduced. The compressive stress is controlled by controlling at least the formation conditions and the film thickness of the antireflection film out of the high-melting-point conductive film and the antireflection film, so that the substrate is finally warped.
【０００８】[0008]
【作用】高融点導電膜および反射防止膜のうち少なくと
も反射防止膜の生成条件および膜厚を制御して、配線膜
が持つ引っ張り応力に対して圧縮応力を制御すれば、両
応力による互いに反対方向の基板の反りが相殺されて、
該基板の反りがなくなる。By controlling at least the formation conditions and the film thickness of the anti-reflection film out of the high melting point conductive film and the anti-reflection film, and controlling the compressive stress with respect to the tensile stress of the wiring film, the two directions are opposite to each other due to both stresses. Substrate warpage is offset
The substrate does not warp.
【０００９】[0009]
【実施例】以下この発明の一実施例を図面を参照して説
明する。図１はこの発明の一実施例を示す工程断面図で
ある。まず図１（ａ）に示すように、ＩＣ基板２１上に
絶縁膜２２（例えばＢＰＳＧ膜）を６０００Å形成した
後、３層構造配線のバリアメタル層としてＴｉＮ膜２３
をリアクティブスパッタ法にて１０００Å形成する。こ
の時、スパッタ条件は、圧力オールＮ2 の６ｍtorr，パ
ワー５．０ｋＷ，無加熱とする。この時点で基板２１は
ＴｉＮの圧縮応力により、該基板２１側を凹部として最
大２３μm 反る。その後、ＴｉＮ膜２３上に、３層構造
配線の中間層（配線膜）として図１（ｂ）に示すように
Ａｌ−Ｓｉ系合金膜２４を５０００Åスパッタ法にて形
成する。このとき基板２１はＡｌの引っ張り応力によっ
て逆の方向（基板２１側を凸部とする方向）へ平均９．
６μm 反る。その後、Ａｌ−Ｓｉ系合金膜２４上に、３
層構造配線の反射防止膜層として図１（ｃ）に示すよう
にＴｉＮ膜２５を上記と同条件にてリアクティブスパッ
タ法にて５００Å形成する。すると、この時のＴｉＮの
圧縮応力により基板２１は、該基板２１側を凸とする平
均９．６μm の前記の反りが戻り、基板２１の反りは０
μm となる。その後、ＴｉＮ膜２５、Ａｌ−Ｓｉ系合金
膜２４およびＴｉＮ膜２３の３層を通常のホトリソ・エ
ッチング法で配線パターンにパターニングすることによ
り、３層構造の配線を完成させる。この時のホトリソ工
程時、基板２１が平坦であるから該工程が正確に行わ
れ、高精度の配線形成が可能となる。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view showing one embodiment of the present invention. First, as shown in FIG. 1A, an insulating film 22 (for example, a BPSG film) is formed on an IC substrate 21 at 6000.degree.
Is formed at a thickness of 1000 ° by a reactive sputtering method. At this time, sputtering conditions, the pressure-ol N 2 6 mTorr, power 5.0 kW, and no heating. At this point, the substrate 21 is warped at a maximum of 23 μm with the substrate 21 side as a concave portion due to the compressive stress of TiN. Thereafter, as shown in FIG. 1B, an Al-Si alloy film 24 is formed on the TiN film 23 as an intermediate layer (wiring film) of the three-layer structure wiring by a 5000 ° sputtering method. At this time, the substrate 21 averages in the opposite direction (the direction in which the substrate 21 has a convex portion) due to the tensile stress of Al.
Warp 6 μm. After that, on the Al-Si based alloy film 24, 3
As shown in FIG. 1C, a TiN film 25 is formed to a thickness of 500.degree. By a reactive sputtering method under the same conditions as described above, as an antireflection film layer of a layered wiring. Then, due to the compressive stress of the TiN at this time, the warpage of the average of 9.6 μm with the substrate 21 side being convex is returned, and the warpage of the substrate 21 is zero.
μm. Thereafter, the three layers of the TiN film 25, the Al—Si alloy film 24, and the TiN film 23 are patterned into a wiring pattern by a normal photolithography etching method, thereby completing a wiring having a three-layer structure. In the photolithography process at this time, since the substrate 21 is flat, the process is performed accurately, and highly accurate wiring can be formed.
【００１０】なお、高融点導電膜に前記のようにリアク
ティブスパッタ法のＴｉＮ膜を使用した場合、その生成
条件および膜厚を次の範囲とすることにより、どのよう
な場合においても基板の反りを除去できた。 Ｎ2 ／Ａｒ比はバリアメタル層、反射防止膜層共に３
０％〜１００％。 スパッタ圧力はバリアメタル層、反射防止膜層共に３
ｍtorr〜１６ｍtorr。 スパッタパワーはバリアメタル層、反射防止膜層共に
２ｋＷ〜５ｋＷ。 スパッタ温度はバリアメタル層が無加熱〜３５０℃、
反射防止膜層が無加熱〜２５０℃。 膜厚はバリアメタル層が５００〜１０００Å、反射防
止膜層が２００〜１０００Å。In the case where the TiN film formed by the reactive sputtering method is used for the high-melting-point conductive film as described above, the warpage of the substrate can be obtained in any case by setting the formation conditions and the film thickness in the following ranges. Could be removed. The N 2 / Ar ratio is 3 for both the barrier metal layer and the antireflection film layer.
0% to 100%. The sputtering pressure is 3 for both the barrier metal layer and the antireflection film layer.
mtorr to 16 mtorr. The sputtering power is 2 kW to 5 kW for both the barrier metal layer and the antireflection film layer. The sputtering temperature is from no heating of the barrier metal layer to 350 ° C.
The antireflection film layer is not heated to 250 ° C. The thickness of the barrier metal layer is 500 to 1000 °, and the thickness of the antireflection film layer is 200 to 1000 °.
【００１１】また、上記は高融点導電膜としてＴｉＮ膜
を使用した場合であるが、高融点導電膜としては、他に
１００％高融点金属あるいはその合金、あるいはＴｉＮ
以外の高融点金属のナイトライドまたはシリサイドある
いはカーバイドを使用できる。具体的には、ＴｉＷ，Ｗ
Ｓｉ，Ｗなどである。それらの場合にも、Ａｌ−Ｓｉ系
合金膜が持つ引っ張り応力に対して、高融点導電膜の生
成条件および膜厚を制御して、高融点導電膜による圧縮
応力を制御することにより、基板の反りを除去できる。
さらに、上記実施例ではＡｌ−Ｓｉ系合金膜を使用した
が、これに限定するものではなく、引っ張り応力を有す
る配線膜であれば、本発明の実施によって、基板の反り
をなくすことができる。また、バリアメタルとしての高
融点導電膜と、Ａｌ−Ｓｉ系合金膜等の配線膜は従来と
同様の工程で形成し、その過程で発生した引っ張り応力
による基板の反りを、高融点導電膜等からなる反射防止
膜の生成条件および膜厚を制御することにより圧縮応力
を制御し、解消することも可能である。The above description is for the case where a TiN film is used as the high melting point conductive film. Other examples of the high melting point conductive film include a 100% high melting point metal or alloy thereof, or TiN film.
Other high melting point metal nitrides or silicides or carbides can be used. Specifically, TiW, W
Si, W, etc. In these cases, too, the tensile stress of the Al—Si alloy film is controlled by controlling the conditions and thickness of the high melting point conductive film to control the compressive stress of the high melting point conductive film. Warpage can be removed.
Furthermore, although the Al-Si based alloy film is used in the above embodiment, the present invention is not limited to this. If the wiring film has a tensile stress, the warping of the substrate can be eliminated by implementing the present invention. Also, a high melting point conductive film as a barrier metal and a wiring film such as an Al-Si alloy film are formed in the same process as the conventional one, and the warpage of the substrate due to the tensile stress generated in the process is reduced. It is also possible to control and eliminate the compressive stress by controlling the formation conditions and the film thickness of the antireflection film made of.
【００１２】[0012]
【発明の効果】以上詳細に説明したように、この発明に
よれば、半導体基板上に高融点導電膜／配線膜／反射防
止膜の３層構造で配線を形成する場合に、配線膜が持つ
引っ張り応力に対して、高融点導電膜および反射防止膜
のうち少なくとも反射防止膜の生成条件および膜厚を制
御して圧縮応力を制御することにより、基板の反りをな
くすことができる。その結果、ホトリソ工程を正確にし
て、高精度に配線を形成することが可能となる。As described above in detail, according to the present invention, when a wiring is formed in a three-layer structure of a high melting point conductive film / wiring film / antireflection film on a semiconductor substrate, the wiring film has By controlling the compressive stress by controlling at least the generation conditions and the film thickness of the antireflection film of the high-melting-point conductive film and the antireflection film against the tensile stress, the warpage of the substrate can be eliminated. As a result, it is possible to form the wiring with high accuracy by making the photolithography process accurate.
【図１】この発明の半導体素子の配線形成方法の一実施
例を示す工程断面図である。FIG. 1 is a process sectional view showing one embodiment of a method for forming a wiring of a semiconductor device according to the present invention.
【図２】従来の配線形成法を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional wiring forming method.
【図３】従来の改良された配線形成法を示す断面図であ
る。FIG. 3 is a cross-sectional view showing a conventional improved wiring forming method.
２１ ＩＣ基板 ２３ ＴｉＮ膜 ２４ Ａｌ−Ｓｉ系合金膜 ２５ ＴｉＮ膜 Reference Signs List 21 IC substrate 23 TiN film 24 Al-Si alloy film 25 TiN film
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/3205 H01L 21/3213 H01L 21/768 H01L 21/28 - 21/288 H01L 21/44 - 21/445 H01L 29/40 - 29/43 H01L 29/47 H01L 29/872 Continued on the front page (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/3205 H01L 21/3213 H01L 21/768 H01L 21/28-21/288 H01L 21/44-21/445 H01L 29 / 40-29/43 H01L 29/47 H01L 29/872
Claims (1)
応力を有する配線膜，反射防止膜を順次形成し３層構造
の配線を形成する場合に、 前記配線膜が持つ引っ張り応力に対して、前記高融点導
電膜と前記反射防止膜のうち少なくとも前記反射防止膜
の生成条件および膜厚を制御することにより圧縮応力を
制御し、最終的に基板の反りがなくなるようにしたこと
を特徴とする半導体素子の配線形成方法。When a high-melting conductive film, a wiring film having a tensile stress, and an antireflection film are sequentially formed on a semiconductor substrate to form a three-layered wiring, the tensile stress of the wiring film is reduced. The compression stress is controlled by controlling at least the generation conditions and the film thickness of the antireflection film among the high-melting-point conductive film and the antireflection film, so that the substrate is finally warped. wire-shaped formation method of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192891A JP3157012B2 (en) | 1991-06-18 | 1991-06-18 | Semiconductor element wiring forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17192891A JP3157012B2 (en) | 1991-06-18 | 1991-06-18 | Semiconductor element wiring forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05102153A JPH05102153A (en) | 1993-04-23 |
| JP3157012B2 true JP3157012B2 (en) | 2001-04-16 |
Family
ID=15932440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17192891A Expired - Fee Related JP3157012B2 (en) | 1991-06-18 | 1991-06-18 | Semiconductor element wiring forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3157012B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500312A (en) * | 1994-10-11 | 1996-03-19 | At&T Corp. | Masks with low stress multilayer films and a process for controlling the stress of multilayer films |
| US6184157B1 (en) * | 1998-06-01 | 2001-02-06 | Sharp Laboratories Of America, Inc. | Stress-loaded film and method for same |
| JP2006041182A (en) | 2004-07-27 | 2006-02-09 | Oki Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP5096675B2 (en) * | 2005-12-15 | 2012-12-12 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
| US7982286B2 (en) * | 2006-06-29 | 2011-07-19 | Agere Systems Inc. | Method to improve metal defects in semiconductor device fabrication |
| FR2958754B1 (en) * | 2010-04-12 | 2012-10-26 | Centre Nat Rech Scient | HOT WIRE SENSOR OF SUBLIMILLIMETRIC SIZE AND METHOD OF MAKING THE SAME. |
| JP2012038885A (en) * | 2010-08-06 | 2012-02-23 | Panasonic Corp | Semiconductor device and method of manufacturing the same |
| CN111584580B (en) * | 2020-05-15 | 2022-09-09 | 武汉华星光电半导体显示技术有限公司 | Preparation method of flexible display panel and flexible display panel |
-
1991
- 1991-06-18 JP JP17192891A patent/JP3157012B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH05102153A (en) | 1993-04-23 |
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